7/29/2019 Do Practice CO

1/2

i. The common bus architecture system for 30 processor registers. How many selectionlines are required for each multiplexer for the destination decoder. (1)

ii. How subroutine call is different from branching?iii. Define the term selective set with example.iv. What are the four basic types of operations that need to be supported by an instruction

set?

v. The memory unit of a computer has 256 K words of 32 bits each. The computer has aninstruction format with four fields: an operation code field, a mode field to specify one

of seven addressing modes, a memory address. Specify the instruction format and the

number of bits in each field if the instruction is in one memory word.vi. Why is transfer of control instructions needed?

vii. Name and explain the types of control organizations?viii. Discuss the race round condition in J-K flip flop.

ix. What is the benefit of using multiple bus architecture compared to single busarchitecture?

x. Explain the steps of an instruction cycle.

Q1.a) Draw the logic diagram of a full subtractor using hallf subtractor and required gates.

b) Show the block diagram that executes the statement

ABBAxT ,:3 (

c) Draw the logic diagram of a bit encoder circuit with four input lines, exactly one of

which is high at any instant and two output lines whose 2-bit binary value tells whichinput is high.

d) It is stated that both an arithmetic left shift and a logical left shift corresponds to a

multiplication by 2 when there is no overflow, and if overflow occurs, arithmetic and logical

left shift operations produce different results, but the arithmetic left shift retains the sign of thenumber. Demonstrate that these statements are true/false for 5-bit twos complement integers.

Q2.a) Show how a shift register with parallel load can be used to convert serial input to parallel

output and parallel output and parallel input to serial output

b) Draw a timing diagram assuming that SC is cleared to 0 at time T3 if control signal C7 is

active 037 SCTC

C7 is activated with the positive clock transition associated with T1.

c) Design an arithmetic circuit with one selection variable S and two n-bit data inputs A

and B the circuit generates the following four arithmetic operations in conjunction withthe input carry Cin . Draw the logic diagram for the first two stages.

S Cin=0 Cin=1

1 D=A-1 D=A+B+1

0 D=A+B D=A+1

Q3.a) A digital system has 16 registers, each with 32 bits it is necessary to provide parallel datatransfer from each register to every other register.

i) How many lines are needed for transfer along 4 common bus? (

ii) How many lines are needed for direct parallel transfer?

7/29/2019 Do Practice CO

2/2

iii) List the sequence of micro operations for a transfer of contents R6 to R13.

b) Consider a hypothetical microprocessor generating 64 bit instructions composed of twofields: first two bytes contain opcode and remainder the immediate operand or an

operand address

a. What is the maximum directly addressable memory capacity (in bytes)?b. Discuss the impact on the system speed if the microprocessor bus has

i. A 64 bit local address bus and a 32 bit local data bus orii. A 32 bit local address bus and a 32 bit local data bus

c. How many bits are needed for the program counter and the instruction register?Q4.

a) Consider a computer system that contains an I/O module controlling as simple key-board/printer teletype. The following registers are contained in the processor and

connected directly to the system bus:

INPR : Input Register, 8 bits

OUTR : Output Register, 8 bitsFGI : Input Flag, 1 bit

FGO : Output Flags, 1 bit

IEN : Interrupt Enable, 1 bitKeystroke input from the teletype and printer output to the teletype are controlled by the

I/O module. The teletype is able to encode an alphanumeric symbol to an 8-bit word and

decode an 8-bit word into an alphanumeric symbol.

a) Describe how the processor, using the first four register listed in this problemcan achieve I/O with the teletype.

b) Describe how the function can be performed more efficiently by also employingIEN

b) Consider a hypothetical computer with an instruction set of only two n-bit instructions. Thefirst bit specifies the opcode, and the remaining bits specify one of the 2n-1 n-bit words of

main memory. The two instructions are follows:

SUBS X Subtract the contents of location X from the accumulator and store theresult in location x and the accumulator

JUMPX Place address X in the program counter

A word in main memory may contain either an instruction or a binary number in twoscomplement notation. Demonstrate that this instruction repertoire is reasonably complete

by specifying how operations can be programmed.

a. Data transfer: Location X to accumulator, accumulator to location X

b. addition: add content of location X to accumulatorc. Conditional branch

d. Logical OR

e. I/O operations