Đồ án HDL

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TRNG I HC CN THKHOA CNG NGH

HDL PROJECT REPORT

VERILOG HDL SIMULATION

LABS

Group: 5

InstructorL Hi Ton

Group M!"r :

#$ N%u&'n () *u+c Hu& M,,- : (#./0#5/1$ N%u&'n L 234n3 M,,- : (#./0#5.$ L *u+c Hu& M,,- : (#./0#676$ 89n% -;n o4n M,,- : (#./0#.55$ N%u&'n T

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T?(L@ AB CANT@NT

-rio% H8L ,i!u4tion L4"s DDDDDDDDDDDDEEEEF4% .

L4" # : (uiin% Hir4rc3& DDDDDDDDDDDDDDEF4% 6

L4" 1 : ,i!u4tion$-riic4tion DDDDDDDDDDDDEEF4% >

L4" . : M!or& DDDDDDDDDDDDDDDDDDDF4% ##

L4" 6 : n"it "in4r& countr DDDDDDDDDDDDDDF4% #0

L4" 5 : Co!p4r4tor DDDDDDDDDDDDDDDDDEF4% 11

L4" 0 :?rit3!tic Lo%ic Jnit K?LJDDDDDDDDDDEEF4% 10

HDL PROJECT REPORT PAGE 2

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-rio% H8L ,i!u4tion L4"sAri

The Verilog simulation labs in this course are designed to maximize yourhands on introduction to Verilog coding There!ore" you are as#ed tocreate all hard$are modules and testbenches !rom scratch A!ter !inishingthese labs" you $ill gain the le%el o! coding s#ill" syntax &ro!iciency" andunderstanding that can only be achie%ed through meaning!ul &ractice ande!!ort'ost o! the early lab exercises are standalone tas#s that rein!orce andillustrate language conce&ts that are !undamental to all Verilog codingA"OctisA!ter com&leting these labs" you $ill be able to() *rite +T, descri&tions !or sim&le circuits) Create a structural Verilog descri&tion !or sim&le circuits) -uild hierarchy by using Verilog) Create a Verilog testbench to %eri!y the hierarchical structure created inthe

&re%ious ste&s) .se the simulation so!t$are) Create basic in&ut stimulus) +un a simulation

L4"s Autin,ab /( -uilding Hierarchy,ab 0( 1imulation2Veri!ication,ab 3( 'emory,ab 4( n5bit -inary Counter,ab 6( Com&arator,ab 7( Arithmetic ,ogic .nit 8A,.9


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L4" #: (uiin% Hir4rc3&

RPust :

:n this lab" you $ill $rite a com&lete +T, descri&tion !or the modules';

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-rio% Co:

// This is module AND_OR in Labs 1// Design name : AND_OR

// File name : AND_OR.v// Coder : Nhom 5module AND_OR !N"# O$T1 %&

in'u( )*:+, !N"&

ou('u( O$T1&-ire sig1# sig&

and $+sig1#!N")+,#!N")1,%&

and $1sig#!N"),#!N")*,%& or $*O$T1#sig1#sig%&

endmodule


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,&nt3sis output:


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L4" 1: ,i!u4tion$-riic4tion

RPust ::n this lab" you $ill $rite a Verilog testbench !or theAND_OR modulecom&leted in the &re%ious exercise As &art o! the testbench" you $illcreate a sim&le in&ut stimulus by using both concurrent and seuentialstatementsBxamine the circuit belo$ 8>igure 09 :n this lab" you $ill $rite a

com&lete Verilog testbench descri&tion !or the moduleAND_OR

This lab com&rises !our &rimary ste&s( ;ou $ill create a ne$ &ro?ect and

im&ort Verilog source !iles@ create a testbench $ith the Verilog testbench$izard in the simulation so!t$are@ create initial and always in&ut stimulusstatements@ and" !inally" %eri!y the logic structure and !unctionality byrunning a simulation and examining the resulting $a%e!orms


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module AND_OR_T%& reg )*:+, in'_(b& -ire ou(_vie-&ini(ial begin

01+ in'_(b 23b++++& 01+ in'_(b 23b1111& 01+ in'_(b 23b++11& 01+ in'_(b 23b++++& endal-a4s begin

01+ in'_(b in'_(b 1& endini(ial begin

6moni(or7!N" 8b # O$T 8d 7 #in'_(b#ou(_vie-%& 0*++ 6s(o'& end

AND_OR $_(es( in'_(b # ou(_vie-%&endmodule


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,i!u4tion Rsut:


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Q4or!s:


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L4" .: M!or& KRAM

RPust :

:n this lab" you $ill $rite a com&lete +T, descri&tion !or a +O' moduleby using a one5dimensional array and a Verilog reg data ty&e and a casestatement

The memory $as modeled as a +O'" $hich is a constant@ there!ore" you$ere reuired to assign %alues at the time o! declarationThis lab com&rises three &rimary ste&s( ;ou $ill create a one dimensionalmemory array using case statement@ create a testbench $ith the Verilogtestbench $izard in the simulation so!t$are@ !inally" %eri!y the logicstructure and !unctionality by running a simulation and examining theresulting $a%e!orms


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// This is a RO9 module b4 using aonedimensional arra4// and a ;erilog reg da(a (4'e and a

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Tst"nc3:

module rom_

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,i!u4tion rsut:


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Q4MHor!s

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L4" 6 Countr

RPust :

:n this lab" you $ill $rite a com&lete +T, descri&tion !or the moduleCNTRby usingparameter statements to s&eci!y the bit $idth This is ann5bit binary" u&2do$n" loadable counter" $ith acti%e5,o$ asynchronousreset ;ou $ill then build a Verilog H=, testbench to %eri!y the!unctionality o! the +T, code as $ell as the hard$are it models

Bxamine the circuit belo$ 8>igure 39 :n this exercise" you $ill create a!ully !unctional binary counter that can be dynamically scaled to anylength The use o!parameter statements is an im&ortant tool !or modulereuse and source code readability The circuit is an n5bit binary" u&2do$nloadable counter" $ith acti%e5 ,o$ asynchronous reset

This lab com&rises three &rimary ste&s( ;ou $ill create a so!t$are &ro?ect@ declaretheparameter statements@ and" !inally" create a testbench to %eri!y the designCreate the in&ut stimulus(/ 1et the CLAC2 input to toggle at a rate o! 100 MHz0 Assert the R@,@T input at time 15 ns" hold !or 25 ns" then de5assert3 1et the C@ input initiallyHig" de5assert 8set!"w9 at time #00" hold !or 100 ns$reassert4 1et the LA?8 input initially!"w" toggleHig at time 500 ns" !or one !ull cloc#cycle

6 1et .=N to initiallyHig" then!"w at time %50 nsD 1et the 8IN input %alue to &'0( or EFb00001111


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// This is an nbi( binar4# u'/do-n# loadable

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Tst"nc3

// This is an (es(ben:+, _ou(_(b&

al-a4s 01+

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Q4MHor!

s:

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L4" 5 Co!p4r4tor

RPust :

:n this lab" you $ill $rite descri&tion !or the module COM)81ynchronous Com&arator9 using an i*+else statementBxamine the circuit belo$ 8>igure 49(

This lab com&rises !our &rimary ste&s( ;ou $ill create a so!t$are &ro?ect@create an +T, %ersion o! COM)@ and" !inally" create a testbench to %eri!ythat the beha%ioral model !unctions correctly:! the ex&ected result and the data are eual" the result is T+.B@other$ise" the result is >A,1B=eclarations o! in&ut and out&ut are sho$n in the !ollo$ing table(


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-rio% co:

// 9odule name :

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Tst"nc3:

//9odule name :

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Q4or!


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L4" 0 ?rit3!tic Lo%ic Jnit K?LJ

RPust :

:n this lab" you $ill $rite a com&lete +T, descri&tion !or the moduleA!, The o&5codes and !unctionality o! the synchronousA!, isdescribed belo$

.se a case statement to describe the !unctionality !or theA!, as sho$nin the !ollo$ing table" $hich sho$s the -.!.CT/ON O)COD. and theo&eration2!unction !or each =o not !orget the BNA-,B in&ut


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-rio% Co:

// 9odule name : alu// File name : alu.v

// Coder : Nhom 5

module alu a_in# b_in# o'

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Tst"nc3:

module alu_(b%& reg )*:+, a_in&

reg )*:+, b_in& reg )*:+, o'

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,i!u4tion Rsut:


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Q4or! :

Q4MHor!s:

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