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Implementation

DMA channel entityDMA channel's interface is composed of:

interface to the upper entity (DMA controller)o cmd

This bus tells the DMA channel how to interpret the data on the

`addr_in' bus (basically, tells what register to load with data on

'addr_in').

The following commands can be sent (they are shown together

with the values sent through the `cmd' and `addr_in' buses):

commandcmd bus

contentsaddr_in bus contents

nop 0 any

set transfer count 1 transfer count

set source address 2 source address

set destination address 3 destination address

set RAM read delay

clocks number4 RAM read delay clocks number

set RAM write delayclocks number

5RAM write delay clocksnumber

set IO read delay clocksnumber

6 IO read delay clocks number

set IO write delay clocksnumber

7 IO write delay clocks number

set source type as RAM 8 any

set source type as IO 9 any

set destination type as

RAM10 any

set destination type as IO 11 any

set transfer type 12 transfer type (0 for nop, 1 forcopy, 2 for swap)

o addr_inMaybe `addr_in' is not the best name, as long as through this bus

are also sent many other things than source/destination addresses

(see table above).

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o runIf the channel is ready (no transfer in progress), and suspend is not

requested, raising this line for at least a clock triggers a new

transfer. Otherwise, it is ignored.

o readySignalizes that no transfer is in progress.

o suspendWhen raised, the channel is requested to suspend. It completes the

current elementary operation (copy or swap a location), then

enters suspend mode and activates the `suspend_ack' line.

o suspend_ackAcknowledges that the channel is in suspend mode.

interface to RAMo ram_wro ram_addro ram_dio ram_do

interface to IOo io_wro io_addro io_dio io_do

The DMA channel schematics is shown below:

DMA channel timings:

DMA channel test entity

The testing strategy was to build a dedicated upper layer that wraps around theDMA channel entity and contains all the ingredients for a realistic simulation.

That is, it contains a DMA channel, two RAMs, some additional logic and a

dedicated testing interface.

Testing can be done through VHDL bench tests or through simulator macros.

Included in this package is a set of Modelsim macros for this purpose (please

find the .do macro files in the same directory as the VHDL sources).

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Whatever the testing method, through bench tests or macros, the test consists of

the following steps:

gain control over the RAMs and set up their contents grant the DMA channel access to RAMs issue commands to the DMA channel (setup channel and make transfers) gain control over the RAMs and check RAMs contents to see if the data

was moved correctly

DMA controller entityDMA controller's interface is composed of:

interface to the host:o cmd

This bus tells the DMA controller how to interpret the data on the

`addr_in' bus (what register to load with data on 'addr_in').

The following commands can be sent, on a per-DMA channel

basis. They are shown together with the values sent through the

`cmd' and `addr_in' buses:

commandcmd bus

contents

addr_in bus contents

nop 0 any

set next channel inchain

1 next channel in chain

set availableclocks (per

transfer quanta)

2 available clocks

request transfer 3request flag (1 for actually requesting atransfer, 0 if trying to cancel a transfer

request that was not acknowledged yet)

o addr_inUsed in conjunction with `cmd' bus (see table above)

o readyWhen the controller raises this line, it signalizes that all channels

have completed their transfers. It can be used as an overall

interrupt line.

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o suspendGeneral suspend input. When the host raises it, the controller

suspends all channels and then signalizes `suspend acknowledge'

by raising the `suspend_ack' line.

o suspend_ackSee the above entry (`suspend').

o selchThis bus is used to select the specific DMA channel to which

commands are sent via the `ch_cmd' and `ch_addr_in' buses.

o ch_cmdThis is the DMA channel-level cmd bus (see the DMA channel

entity description, the`cmd'bus).

o ch_addr_inThis is the DMA channel-level addr_in bus (see the DMA channel

entity description, the`addr_in'bus).

o ch_readySignalizes whether the currently selected channel is ready or not.

Can be used, for example, if the host choses not to use the

interrupts to find when a transfer is complete, but rather to directly

check channel's `ready' flag.

interface to RAMo ram_wro ram_addro ram_dio

ram_do interface to IO

o io_wro io_addro io_dio io_do

DMA controller timings:

When setting up an individual channel, put on `selch' the proper data to select

http://doru.info/projects/hdl/dma/group__dma__implem.html#ch_cmdhttp://doru.info/projects/hdl/dma/group__dma__implem.html#ch_cmdhttp://doru.info/projects/hdl/dma/group__dma__implem.html#ch_cmdhttp://doru.info/projects/hdl/dma/group__dma__implem.html#ch_addr_inhttp://doru.info/projects/hdl/dma/group__dma__implem.html#ch_addr_inhttp://doru.info/projects/hdl/dma/group__dma__implem.html#ch_addr_inhttp://doru.info/projects/hdl/dma/group__dma__implem.html#ch_addr_inhttp://doru.info/projects/hdl/dma/group__dma__implem.html#ch_cmd

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the channel and use the `ch_cmd' and `ch_addr_in' buses to set up channel

parameters, as shown in the DMA channel entity -timings.

DMA controller test entityFor testing the DMA controller, the same methodology was chosen as for DMA

channel. A DMA controller test entity was built, that wraps around the DMA

controller. It contains a DMA controller, 2 RAMs and additional logic forswitching RAMs buses towards the DMA controller or towards the test entity's

interface.

http://doru.info/projects/hdl/dma/group__dma__implem.html#dma_ch_timinghttp://doru.info/projects/hdl/dma/group__dma__implem.html#dma_ch_timinghttp://doru.info/projects/hdl/dma/group__dma__implem.html#dma_ch_timinghttp://doru.info/projects/hdl/dma/group__dma__implem.html#dma_ch_timing