1/3January 2002

DK4_XAUSER MANUAL

DK4000-XA Development KitFor PSD4000 Series of Flash PSDs

CONTENTS

■ (Please see next pages)

DK4000-XADEVELOPMENT KIT

For PSD4000 Series of Flash PSDsRev 0.98

Contents:

� PSDsoft Express - Point and Click Windows based Development Software� DK4000 Eval Board with PSD4135G2� FlashLINK JTAG In-System Programmer (ISP)� Ribbon and "Flying Lead" JTAG cables for FlashLINK� Serial UART cable� CDROM - Data Book, Software and Videos� 110V or 220V Power supply

2

DK4000 – XA DEVELOPMENT KIT ................................................................................... 3

Introduction ...................................................................................................................................3A couple of definitions:....................................................................................................................................3Hardware ........................................................................................................................................................3Software..........................................................................................................................................................3

Detailed Descriptions ....................................................................................................................5

Other board features .....................................................................................................................5Step-By-Step Instructions for ISP Programming: ...........................................................................................6

Using DK4000 as a Development Platform for P51XA users: ....................................................8Concept...........................................................................................................................................................8Downloading to the Development Board ........................................................................................................8JTAG - ISP......................................................................................................................................................8

P51XA Design Overview ...............................................................................................................9Memory Swapping in the PSD......................................................................................................................10What really happens .....................................................................................................................................12Creating your own IAP code bundle .............................................................................................................12

References ...................................................................................................................................12Application notes...........................................................................................................................................12

APPENDIX ........................................................................................................................ 13

Appendix A - Jumper configuration on DK4000 ........................................................................14

Appendix B Software functional description ...........................................................................15

Appendix C Development Board Schematic and parts list .....................................................16Main Schematic ............................................................................................................................................16Power Supply Schematic..............................................................................................................................17XA Daughter Board Schematic.....................................................................................................................18DK4000 Parts List .........................................................................................................................................19

Appendix D: FlashLINK Information ..........................................................................................21Features........................................................................................................................................................21Overview .......................................................................................................................................................21Operating considerations..............................................................................................................................21FlashLINK pinouts.........................................................................................................................................23Loop back connector schematic ...................................................................................................................26

Appendix E Results codes and debug tree for htestXA.obj ...................................................27Results codes............................................................................................................................................27

Success Code...............................................................................................................................................27Debug tree.................................................................................................................................................27

Appendix F: Board errata ...........................................................................................................28

3

DK4000 – XA Development Kit

IntroductionCongratulations on purchasing ST's DK4000 Development kit. The DK4000 (110V or 220 Voltversion) is a low cost kit for evaluating the PSD4000 series of FLASH Programmable System Devices calledPSDs. The DK4000 kit is extremely versatile, and can be used in several different modes. For example, itcan be used to demonstrate the PSD4000's capability of JTAG In-System Programmability (ISP). Also, onceinitial code is resident in the PSD, the program code can be updated while the MCU is running, called In-Application Programming (IAP). Philips P51XA family users can utilize the DK4000 as an evaluationplatform for code development.

The DK4000 – XA Development Board is specific to the Philips P51XA microcontroller family. However,other proliferation boards are be available. Check the website at www.st.com/psm for availability.

A couple of definitions:In-System Programming (ISP)- A JTAG interface (IEEE 1149.1 compliant) is included on the PSDenabling the entire device to be rapidly programmed while soldered to the circuit board (MainFLASH, Secondary Boot FLASH, the PLD and all configuration areas). This requires no MCUparticipation, so the PSD can be programmed or reprogrammed anytime, anywhere, even whilecompletely blank. The MCU is not required for ISP.In-Application Programming (IAP) – Since two independent FLASH memory arrays are included inthe PSD, the MCU can execute code from one memory while erasing and programming the other.Robust product firmware updates in the field are possible over any communication channel (a fewexamples are CAN, Ethernet, UART, J1850) using this unique architecture. For IAP, all code isupdated through the MCU.

Hardware• PSD4135G2 - 4Mb Main FLASH(512kx8), 256Kb Boot FLASH(32kx8), 64Kb SRAM(8kx8). See

website for data sheet www.waferscale.com .• Eval/Demo Board with P51XA or other MCU, LCD Display, JTAG and UART ports for ISP/IAP• FlashLINK JTAG ISP Programmer (uses PC's parallel port)• Straight thru serial cable (Male-Female)• Power Supply

SoftwareTo ensure you have the latest versions, check the website often.

1. PSDsoft Express - Point and Click Windows programming development software. Thiswill install to its own directory.

• MCU Selection by manufacturer and part number• Graphical definition of pin functions• Easy creation of memory map• JTAG ISP Programming.

2. The distribution disk contains the following directories, each with executable code. Forconvenience, copy each distribution disk directory to your machine under…\PSDexpress\dk4kp-XA\… . For example, …PSDexpress\dk4kp-XA\hwtest-XA\,…PSDexpress\ dk4kp-XA\demo1-XA\, etc.

• Hwtest-XA. Validates DK4000 board hardware including serial port• Demo1-XA. Simple program for IAP demo, displays “have no fear…”

Each directory contains the following• *.zip for the psd• *.zip for the C level source code• readme.txt file containing late breaking information• *.obj file suitable for direct PSD programming.

4

Since the *.obj file is the natural format needed by PSDsoft for direct programming of thePSD, no unzipping is necessary to change the executing code in the development board.

The hardware test (hwtest_xa.obj) is resident on the development board. A detaileddescription of each software bundle is included in the appendix.

The following table is a specific listing of the files and their locations on the distribution disk.

Directory Files DescriptionHwtest-XA Hardware test

XAp_hwt_10s_.zip Contains all PSD source filesXAc_hwt_10s_.zip Contains all C level code files (a)Readme.txt Late breaking informationhtestXA.obj Duplicate obj file (also in PSD zip file above)

Demo1-XA “no need to fear…”UXAdemop10_.zip Contains all PSD source filesUXAdemoc10_.zip Contains all C level code files (a)Readme.txt Late breaking informationdemo_xa.obj Duplicate obj file (also in PSD file above)

Notes

a. TASKING C for XA 3.0r5 or later

*** Notice:An additional code bundle will be posted on the web in the future to cover the IAPfunctionality. Please go to www. st.com /psm, and select "Development Tools" andscroll down to DK4000 where the latest software and manual can then be downloaded.

5

Detailed Descriptions

Figure 1 DK4000-XA Development Board

The following features are included in the development board and shown graphically in the above figure.• Display - A two line by 16 character LCD display.• Power switch• UART Serial Port(female) - Connected to MCU serial port; used for In-Application Programming

(IAP)• Philips P51XA or other MCU• PSD4000 software - The PSD4000 is programmed with HWTest demonstration code. User can

program alternative programs via JTAG ISP.• JTAG programming Port - Used in conjunction with FlashLINK programmer for ISP.• Reset Button - For resetting the MCU and PSD.

Other board featuresOther features of the DK4000 board are listed below. These elements are unpopulated to provide lowestcost to the user.

• Provision for chaining JTAG connector is provided in P2 and JP2.• Provision for off board expansion is provided by board connectors suitable for 0.025 square

posts• Provision for 9v battery input is provided near power connector(solder pads only).

6

Step-By-Step Instructions for ISP Programming:a) Install PSDsoft Express on your PC running Windows 95/98/NT/2000. Check web for latest

version.b) Plug the FlashLINK Programmer into your PC’s parallel port and plug in the ribbon cable to the

JTAG port on the eval board. For help, see the Appendix C of the FlashLINK manual.c) Plug in power supply and turn on power. An LCD contrast control is provided as R11. The

typical setting is near the counterclockwise stop.d) Run PSDsoft Express. Here is the initial screen if no project was open in a prior session.

Figure 2 Opening screen upon PSDsoft Express invocation

Use cancel at this point since all we need to do is program the PSD with an existingdemonstration file (*.obj) and there is no need to create a new project. Later, in the “Using theDK4000 as a development platform”, a further tutorial is given on using PSDsoft Express withthe Eval Board for development.

Figure 3 Invocation reminder screen

e) In the Design Flow (shown below), click on the ST JTAG/ISP button. Bottom row ofboxes left side.

Figure 4 PSDsoft Express flow

7

The following screen appears inquiring if it’s desired to program a single device or multiple devices inthe JTAG chain. Select “Only one” and OK.

Figure 5 JTAG-ISP Operations dialog

Clicking OK brings up the JTAG Operations - Single device dialog shown in the following figure.

Figure 6 PSDsoft Express, JTAG Operations dialog

f) In Step 1, browse to find the *.obj file shown in the above figureg) In “select device” box, choose the PSD4000 device you have installed on the boardh) In step 3, select the operation of “Program”. Click execute.i) Observe in the lower pane the JTAG activities that occur while programming your device.j) Watch the display. When the download has completed, as indicated in the log window, push thereset button on the Development Board. The displays below will sequence one time and thenoperation will stop.

N o n e e d t o f e a r

E a s y F L A S H i s h e r e

* * * C O M P L E T E * * *

Figure 7 Eval Board Displays for Demo1 (demo_xa.obj)

8

If you cycle power to the board, you will see that the display will resequence, confirming that theprogram and all configuration information are stored in the PSD's non-volatile FLASH Memory.

k) For better understanding of the program you may want to examine the following references:1. System memory map in the “P51XA Design Overview” section of this document .2. PSDsoft Express project (demo_xa.ini)3. The file source code (included) to see how the executing code was configured

*** Notice:An additional code bundle will be posted on the web in the future to cover the IAPfunctionality. Please go to www. st.com /psm, and select "Development Tools" andscroll down to DK4000 where the latest software and manual can then be downloaded.

Using DK4000 as a Development Platform for P51XA users:

ConceptThe ST DK4000 Development Board provides the following capabilities

• Demonstrate design concepts early, optimizing “time to market”• Jump start user application with proven framework (hardware and software)• Substitute for user target system until target prototypes are available• Gives instant platform for testing ISP and IAP demonstration• Allows programming the PSD using included FlashLINK cable

Downloading to the Development BoardExecutable code can be downloaded to the Development Board two different ways: via the JTAG(ISP) or via the UART (IAP). This manual only describes the ISP capabilities at this time. The IAPcapabilities will be supported in the future using PSDload available on the website.

JTAG - ISPThe PSD4000 series JTAG interface provides the capability of programming all memory areas withinthe PSD ( PLD, configuration, main and secondary FLASH memories). This interface can also beused to program a completely blank component as JTAG is enabled as the default PSD state. SeeApplication Note 54 (AN054) for further description of the JTAG interface on our CD or our website.

The LCD will be non operational during JTAG - ISP since the MCU is not operating. During thisinterval, the PSD is not connected to the MCU bus. To restrain the MCU during this interval, theJTAG interface contains a signal, ( RST ) that is connected to the MCU reset pin.

ST provides a FlashLINK programmer to facilitate the JTAG programming operation. TheFlashLINK programmer connects the PC parallel port to the Eval Board JTAG header and is drivenby PSDsoft Express, the PSD development tool.

9

P51XA Design OverviewThe following figure depicts how the memory is allocated in this project for the htestXA.obj.

The default configuration is 16 bit multiplexed for the following system resources;

• PSD code memory (flash and boot areas)• PSD SRAM• LCD• CSIOP space (PSD registers).

P51XA-G 3 Regs/SR AM

P51XAData Space

00000 - 003FF

06000 - 06001csiop, PSD cntl regs 07000 - 070FF

lcd_e, ext LC D chip sel

08000 - 09FFF

noth ing m apped

rs0 , 8K bytes PSD S RAM

noth ing m apped

0A000

00400 - 05FFF

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

10000

fs164K bytes PSD

M ain Flash

fs264K bytes PSD

M ain Flash

fs364K bytes PSD

M ain Flash

fs464K bytes PSD

M ain Flash

fs564K bytes PSD

M ain Flash

fs664K bytes PSD

M ain Flash

fs764K bytes PSD

M ain Flash

1FFFF20000

2FFFF

3FFFF

4FFFF

5FFFF

6FFFF

7FFFF

30000

40000

50000

60000

70000

P51XAProgram Space

8FFFF fs064K bytes PSD

M ain Flash

8FFFF

80000

00000 - 01FFF02000 - 03FFF csboot1 , 8KB PSD 2nd F lash

csboot0 , 8KB PSD 2nd F lash

08000

04000 - 05FFF06000 - 07FFF

csboot2 , 8KB PSD 2nd F lash

csboot3 , 8KB PSD 2nd F lash

noth ing m apped

noth ing m apped

Figure 8 Memory Map of DK4000/P51XA Board

10

Memory Swapping in the PSD

For this test (htestXA.obj), the dip switch should be in the following position . As a component of thistest, a copy of the executing code that resides in csboot0/1 is made. The destination of this copy is the mainflash area FS0, as shown in the figure below. After the copy operation, the following map applies.

P 51XA -G 3 R egs /S R A M

P51XAData Space

00000 - 003FF

06000 - 06001csiop, P S D cntl regs 07000 - 070FF

lcd_e, ext LC D chip se l

08000 - 09FFF

noth ing m apped

rs0 , 8K bytes P S D S R A M

noth ing m apped

0A 000

00400 - 05FFF

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

64K bytes

10000

fs164K bytes P S D

M ain F lash

fs264K bytes P S D

M ain F lash

fs364K bytes P S D

M ain F lash

fs464K bytes P S D

M ain F lash

fs564K bytes P S D

M ain F lash

fs664K bytes P S D

M ain F lash

fs764K bytes P S D

M ain F lash

1FFFF20000

2FFFF

3FFFF

4FFFF

5FFFF

6FFFF

7FFFF

30000

40000

50000

60000

70000

P51XAProgram Space

8FFFF fs0Copy o f Boot area

M ain F lash

8FFFF

80000

00000 - 01FFF02000 - 03FFF csboot1 , 8KB PSD 2nd Flash

csboot0 , 8KB PSD 2nd Flash

08000

04000 - 05FFF06000 - 07FFF

csboot2 , 8KB PSD 2nd Flash

csboot3 , 8KB PSD 2nd Flash

noth ing m apped

noth ing m apped

Figure 9 Memory map after running of htestXA.obj

For normal boot, the second LCD screen shows “executing from, BOOT area”. The message exists in afixed location in the code and is read from this location and copied to the LCD at boot up.

When the code copy is performed, a different message is inserted into the same fixed location based on thedestination of the copy (as shown in FS0). When this version of the code is executed, the message isdisplayed “executing from MAIN FLASH”. This method yields a single unambiguous confirmation of theexecution source, which is very convenient for demonstrating memory swapping operations.

11

Now let’s boot from FS0 to demonstrate the swapping capability of the PSD. Place the dip switch in the

following position and press the reset button. You should see the execution source annunciated tothe display “booting from MAIN FLASH”. The following memory map applies.

P 51XA -G 3 R egs/S R A M

P51XAData Space

00000 - 003FF

06000 - 06001csiop, P S D cntl regs 07000 - 070FF

lcd_e, ext LC D ch ip se l

08000 - 09FFF

noth ing m apped

rs0 , 8K bytes P S D S R A M

0A 000

00400 - 05FFF

10000

P51XAProgram Space

8FFFF 8FFFF

noth ing m apped

fs164K bytes P S D

M ain F lash

fs264K bytes P S D

M ain F lash

fs364K bytes P S D

M ain F lash

fs464K bytes P S D

M ain F lash

fs564K bytes P S D

M ain F lash

fs664K bytes P S D

M ain F lash

fs764K bytes P S D

M ain F lash

1FFFF20000

2FFFF

3FFFF

4FFFF

5FFFF

6FFFF

7FFFF

30000

40000

50000

60000

70000

fs0Copy of Boot area

M ain F lash

0FFFF

00000

10000

80000

noth ing m apped64K by tes

64K by tes

64K by tes

64K by tes

64K by tes

64K by tes

64K by tes

64K by tes

64K by tes

80000 - 81FFF82000 - 83FFFcsboot1 , 8KB PSD 2nd F lash

csboot0 , 8KB PSD 2nd F lash

84000 - 85FFF86000 - 87FFF

csboot2 , 8KB PSD 2nd F lash

csboot3 , 8KB PSD 2nd F lash

V M re g = 0x0 C

Figure 10 Memory map for alternate memory boot

The memory movement within the MCU memory map is accomplished via the logic contained in the PLDequations in the PSD. Each segment that moves must have dual ranged defined in these equations. Theselection is made based on a single logic bit (exe_src_a) that resides in the PSD PAGE register. Followingare the equations for the system. These can bee seen in the PSDsoft Express project included with the kit.Note that “#” indicates a logical OR and “&” indicates a logical AND.

Csboot0 = ( (0x0 – 0x01FFF) & exe_src_a )#( (80000 – 81FFF) & exe_src_a )Csboot1 = ( (0x02000 – 0x03FFF) & exe_src_a ) #( (82000 – 83FFF) & exe_src_a )

Fs0 = ( (0x80000 – 0x8FFFF) & exe_src_a ) # ( ( 0x0 – 0x03FFF) & exe_src )

Note that the logic variable (bit) controlling the actual location of the memory is “exe_src_a”. When this bit iszero (0), the memory segments are as shown in Figure 9. When exe_src_a is one (1), FS0 appears in theexecution location as shown in Figure 10, and the csboot areas are not in the map at all. The physicallocation of this logic bit, exe_src_a, is in the bit6 position of the PAGE register. Actually this bit can beanywhere, the only important element is that it is contained in the PLD equations, as shown above, andaccessible by the MCU. Control of this bit is via a board mounted dip switch.

12

The power up sequence is as follows:a. Execute C startupb. Read the dip switchc. Modify the PSD PAGE and VM registers to obtain the correct memory map.

Once the PAGE and VM register write operations have completed, the next instruction is fetched from thenew memory location (FS0).

This same sequence of events occurs every time power is applied to the board. Since the PAGE register isalways 00h at power up, the software always executes steps a) and b) from the boot area. Then, based onthe DIP switch selection, the code will either stay in the boot area or jump to the main FLASH area.

What really happensThere is a subtlety involved in the transfer of execution described above. This subtlety is due to the fact thatthe MCU really doesn’t know the source of the instruction bytes; boot area or main FLASH. All the MCUknows is that valid instructions on valid address boundaries are presented on the bus when the MCU needsthem. Then the MCU executes the instruction and generates the next address. The key element involved isthe generation of the address by the MCU.

To understand this critical transfer of control, let’s examine the instruction-by-instruction transition from onememory to the other. After the reset signal is deasserted, the MCU is executing from the csboot areanormally. This continues until the exe_src_a bit is written, moving FS0 into the execution location (0x0-0x3FFF). At this same time, csboot area is, for all practical purposes, gone from the system memory map.At this point, the MCU is generating the next address from the instruction received from the csboot area.However, the next instruction will come from the FS0 area. This next instruction fetch must be appropriate tomaintain the program flow. That is, the next instruction must be received by the MCU on an instructionboundary and be appropriate for the program flow. In addition, any issues with the stack and stack pointermust be resolved so program flow can continue (subroutine return addresses, temporary variables, etc.).Pipelining operations can result in execution from the pipeline instead of the new memory, but the pipelinewill continue to be filled from the new memory.

The method we’ve used to ensure correct operation is to place identical code at identical locations in bothapplications through the point of the swap. After the point of the swap, the code bundles can diverge withoutproblems. While this result is inherently ensured in a code copy scenario like htestXA.obj, it’s not soautomatic when the applications are different such as those existing in a true IAP scenario.

Creating your own IAP code bundleA few easy steps can ensure that program flow for this critical area is guaranteed to occur properly. Thesesteps involve the absolute location of certain modules within the base application and the new IAPapplication. Locating these modules is accomplished using linker controls. With this framework, bootingfrom one application to another is EASY.

References

IEEE Std 1149.1-1990 IEEE Test Access Port and Boundary Scan ArchitectureFlashlink User Manual (included in the Appendix of this document)

Application notesAN054 JTAG InformationAN069 - Design Guide, PSDsoft Express and PSD4135G2AN070 Design Guide, P51XA

13

Appendix

14

Appendix A - Jumper configuration on DK4000

Jumper Description Default position(shown by dotted line)

Boardposition

JP1 Measure PSD current No measure Upper centerJP2 JTAG chaining No chain Upper rightJP3 Internal / external power supply Internal power supply Lower rightJP4 9v battery connector None (no jumper) Lower rightJP10(rev C only)

Display control XA (non defaultposition)

Lower center

ba tte ryconnection

M C U area

PSD

se ria lpo rt

JT A G , P 1

onof

f

LC DC on tras t

d7 -14LC D D isp lay

JP2

JP1

NO CHAIN

JP3

PS

D I

Mea

s

P ow e r S upp ly In t E xt

P ow er onind ica to r

JP10

XA

NO

RM

R ese t

Figure 11 Assembly Drawing with default jumper positions

15

Appendix B Software functional description

1. htestXAThis code exercises all components of the development board: the display, PSD memory and chipselects, as well as the UART channel (single character only on receive and transmit). This confirmsfunctionality and is used as a production test. The following list describes the viewable LCD screens.

• Invocation banner, software version• Display execution source. (boot area or main flash)• Motherboard LED test• PSD RAM test• Code Copy. Executing boot code is copied to main flash block FS0 (BOOT-> FLASH)

Displays flash ID and does erase of FS0 prior to the copy operation.• UART test (waiting for host to send “0”, dev board reply is a “1”, baud rate is19200 with 8 data

bits, no parity and one stop bit)

After this code has run one time, a copy of the executing code exists in the FLASH area. The systemcan run from this code copy by placing the dip switch in the appropriate configuration as described in the“Memory Swapping in the PSD” section of this document.

2. DemoThis is a simple program that displays the following text on the LCD display.

No Need to fear, EASYflash is here .The intent is to show a minimal level of functionality. No UART support is provided.

An additional code bundle will be posted on the web in the future to cover the IAP functionality.

.

16

Appendix C Development Board Schematic and parts list

Main SchematicNote. In the XA design, the C167 component is not populated on the main board shown below. The daughter board supplies the MC U.

D K 4 0 0 0 B

DK4000 Deve lopment Board, 167CR

B

1 2Tuesday, May 16, 2000

Title

Size Document Number Rev

Date: Sheet of

V C C

V C C

V C C

V C C

V C C

V C C

V C C

V C C

V C C

V C C V C C

PE[7. .0]

ADIO[15. .0 ]A[23. .16]

A[15. .8]

A[7..0]

P6.[7. .0]

PD[3. .0]

PA[7. .0]

P8.[7. .0]

C N T L 0 ( _ W R )

CNTL1(_RD)

CNTL2(_BHE)

R E S E T

N M I

M R P B 0

P5.[15. .0]

G N D

P6.[7. .0]

T X D 0

R X D 0

RS-232

left side

PSD42xxG

Icc meas

emulator10k

10k

ADIO0ADIO0ADIO1ADIO1ADIO2ADIO2ADIO3ADIO3ADIO4ADIO4ADIO5ADIO5ADIO6ADIO6ADIO7ADIO7

ADIO8ADIO8ADIO9ADIO9ADIO10ADIO10ADIO11ADIO11ADIO12ADIO12ADIO13ADIO13

ADIO15ADIO15

R D

CNTL1(_RD)

W R / W R L

C N T L 0 ( _ W R )

A19A18A17A16

A16A17A18A19

ADIO14ADIO14

CNTL2(_BHE)

E A

R E S E T

T X D 0

ADIO7ADIO6ADIO5ADIO4ADIO3ADIO2ADIO1ADIO0A 0

A 1A 2A 3A 4A 5A 6A 7

A 8A 9A10A11A12A13A14

P B 2P B 3

P B 4

CNTL1(_RD)

P A 1P A 2P A 3P A 4P A 5P A 6P A 7

P B 0P B 1P B 2

P B 4P B 5P B 6P B 7

C N T L 0 ( _ W R )

A 0A 1A 2A 3A 4A 5A 6A 7

A 8A 9A10A11A12A13A14A15

P1L0P1L1P1L2P1L3P1L4P1L5

P1L6P1L7

P 1 H 1P 1 H 2P 1 H 3P 1 H 4P 1 H 5P 1 H 6P 1 H 7

P 1 H 0

P D 1P D 2P D 3

P E 0P E 1P E 2P E 3P E 4P E 5P E 6P E 7

A20A14A15A12A13A10A11A 8A 9

A 7A 6A 5A 4A 3A 2A 1A 0

ADIO15ADIO14ADIO13ADIO12ADIO11ADIO10ADIO9ADIO8ADIO7ADIO6ADIO5ADIO4

ADIO2

ADIO0ADIO1

ADIO3

P B 7P B 6P B 5P B 4P B 3P B 2P B 1P B 0

P A 7P A 6P A 5P A 4P A 3P A 2P A 1P A 0

V C CG N D G N D

V C C

P B 3

A21A22

V C CG N D

A23A22A21A20A19A18A17A16P D 0P D 1P D 2P D 3

P D 0

M R

R X D 0

P3.0P3.1P3.2P3.3P3.4P3.5P3.6P3.7P3.8P3.9P3.10P3.11P3.12P3.13

P3.15

G N DV C C

V C CG N D

V C CG N D

A[23. .16]

ADIO[15. .0 ]

A[7..0]

A[15. .8]

PB[7. .0]

PD[3. .0]

PE[7. .0]

P3 .11P3.12

P8.7P8.6P8.5P8.4P8.3P8.2P8.1P8.0

P7.7P7.6P7.5P7.4P7.3P7.2P7.1P7.0

P6.7P6.6

P6.0

P5.15

P5.0

P3.15

P3.0

P5.1P3.[13. .0]

P3.1P3.2

P3.3P3.4P3.5P3.6P3.7P3.8P3.9

P3.13

P5.2P5.3P5.4P5.5P5.6P5.7P5.8P5.9P5.10P5.11P5.12P5.13P5.14

P6.1P6.2

P6.3P6.4P6.5

P5.0P5.1P5.2P5.3P5.4P5.5P5.6P5.7P5.8P5.9P5.10P5.11P5.12P5.13P5.14P5.15

P8.0P8.1P8.2P8.3P8.4P8.5P8.6

P8.7P7.0P7.1P7.2P7.3P7.4P7.5P7.6P7.7

P2.0P2.1P2.2P2.3P2.4P2.5P2.6P2.7P2.8P2.9P2.10P2.11P2.12P2.13P2.14P2.15

A23

P6.7P6.6P6.5P6.4P6.3P6.2P6.1P6.0

P1L[7. .0]

P2.0 P 1 H 7

P2.15 P1L0

P2.[15. .0]

P 1 H 6P 1 H 5P 1 H 4P 1 H 3P 1 H 2P 1 H 1P 1 H 0P1L7P1L6P1L5P1L4P1L3P1L2P1L1

P2.1P2.2P2.3P2.4P2.5P2.6P2.7P2.8P2.9P2.10P2.11P2.12P2.13P2.14

V C CG N D

V C CG N D

V C CG N D

G N DV C C

P5.[15. .0]

P6.[7. .0]

P B 4P B 5P B 6P B 7

PA[7. .0]

R E S E T

P7.[7. .0]

P8.[7. .0]

A20A21A22A23

P A 0

N M I

P B 0

R E A D Y

P3.10T X D 0R X D 0

P E 6P E 7

C N T L 0 ( _ W R )CNTL1(_RD)CNTL2(_BHE)

R E S E T

VrefAgnd

Agnd

ADIO0ADIO1ADIO2ADIO3ADIO4ADIO5ADIO6ADIO7

A 0P B 0P B 1

R 11 0 M

C 222pf

C 122pf

U 5

M S 6 2 8 1 2 8

A 012

A 111

A 210

A 39

A 48

A 57

A 66

A 75

A 827

A 926

A1023

A1125

A124

A1328

A143

A1531

A162

C S 122

C S 230

O E24

W E29

D 013

D 114

D 215

D 317

D 418

D 519

D 620

D 721

U 3

C 1 +1

C 2 +4

C2-5

C1-3

V +2

V-6

V C C16

T2in10

R2out9R1out12

T1in11

T1out14

T2out7

R1 in13

R2in8

R 2100

R 3 100

C 60.1

C 5

0.1

C 7

0.1

C 30.1

C 4

0.1

R 5

10k

J4

D B 9 F

594837261

R 4

100

P4123456789

1011121314151617181920

P12123456789

1011121314151617181920

P10123456789

1011121314151617181920

P11123456789

1011121314151617181920

R 7

10K typ

P9123456789

1011121314151617181920

P3123456789

1011121314151617181920

S 1

R E S E T

R 6

0805

R 8R 9R 1 0

C 8

0.1

C 9

0.1

C 1 80.1

C 1 91

P5123456789

1011121314151617181920

S 2

1 2 3 4

8 7 6 5

P61234567891011121314151617181920

P71234567891011121314151617181920

P81234567891011121314151617181920

U 2

ADIO03

ADIO14

ADIO25

ADIO36

ADIO47

ADIO510

ADIO611

ADIO712

ADIO813

ADIO914

ADIO1015

ADIO1116

ADIO1217

ADIO1318

ADIO1419

ADIO1520

C N T L 0 ( W R )59

CNTL1( RD)60

CNTL2( BHE)40

P F 031

Vcc

_19

GN

D8

Vcc

_129

Vcc

_169

PD0(ALE)79

PD1(CLKIN)80

PD2( CSI )1

P D 3 ( W R H )2

PE0(TMS)71

PE1(TCK/ST)72

PE2(TDI )73

PE3(TDO)74

PE4(TSTAT/RDY)75

PE5(TERR)76

PE6(VSTBY)77

PE7(VBATON)78

P F 132

P F 233

P F 334

P F 435

P F 536

P F 637

P F 738

P G 021

P G 122

P G 223

P G 324

P G 425

P G 526

P G 627

P G 728

P A 051

P A 152

P A 253

P A 354

P A 455

P A 556

P A 657

P A 758

P B 061

P B 162

P B 263

P B 364

P B 465

P B 566

P B 667

P B 768

P C 041

P C 142

P C 243

P C 344

P C 445

P C 546

P C 647

P C 748

GN

D30

GN

D49

GN

D50

GN

D70

R E S E T39

1 2 3

JP1

1 3

2

R 1 110K

13

2

R 5 4

Y 1

xx_MHz

12

34 C 3 80.01Y 2xx_MHz

12

3

C 4 0100pf

U 1

C167CR

A D 0100

A D 1101V

cc10

9

A D 2102

A D 3103

A D 4104

A D 5105

A D 6106

A D 7107

A D 8108

A D 9111

A D 1 0112

A D 1 1113

A D 1 2114

A D 1 3115

A D 1 4116

A D 1 5117

E A99A L E98R E A D Y97W R / W R L96R D95

Vcc

93

XTAL1138

XTAL2137

RSTIN140

R S T O U T141

N M I142

P4.0 /A1685

A1786

A1887

A1988

A2089

A2190

A2291

P4.7 /A2392

P3.0/T0IN65

P3.1 /T6OUT66

P3.2 /CAPIN67

P3.3 /T3OUT68

P3.4 /T3EUD69

P3.5/T4IN70

P3.6/T3IN73

P3.7/T2IN74

P3 .8 /MRST75

P3 .9 /MTSR76

P3.10 /TXD077

P3.11 /RXD078

P 3 . 1 2 / B H E / W R H79

P3.13 /SCLK80

P3 .15 /CLKOUT81

P1L0118P1L1119P1L2120P1L3121P1L4122P1L5123P1L6124P1L7125P 1 H 0128P 1 H 1129P 1 H 2130P 1 H 3131P 1 H 4132P 1 H 5133P 1 H 6134P 1 H 7135

P2.0 /CC0IO47

P2.1 /CC1IO48

P2.2 /CC2IO49

P2.3 /CC3IO50

P2.4 /CC4IO51

P2.5 /CC5IO52

P2.6 /CC6IO53

P2.7 /CC7IO54

P2.8 /CC8IO/EX0IN57

P2.9 /CC9IO/EX1IN58

P2.10 /CC10IO/EX2IN59

P2.11 /CC11IO/EX3IN60

P2.12 /CC12IO/EX4IN61

P2.13 /CC13IO/EX5IN62

P2.14 /CC14IO/EX6IN63

P2.15 /CC15IO/EX7IN64

P5.0 /AN027

P5.1 /AN128

P5.2 /AN229

P5.3 /AN330

P5.4 /AN431

P5.5 /AN532

P5.6 /AN633

P5.7 /AN734

P5.8 /AN835

P5.9 /AN936

P5.10 /AN10 /T6UED39

P5.11 /AN11 /T5UED40

P5.12 /AN12/T6IN41

P5.13 /AN13/T5IN42

P5.14 /AN14 /T4UED43

P5.15 /AN15 /T2UED44

P6.0 / CS01

P6.1 / CS12

P6.2 / CS23

P6.3 / CS34

P6.4 / CS45

P6 .5 / HOLD6

P6.6 / HLDA7

P6 .7 / BREQ8

P7.0 /POUT019

P7.1 /POUT120

P7.2 /POUT221

P7.3 /POUT322

P7.4 /CC28IO23

P7.5 /CC29IO24

P7.6 /CC30IO25

P7.7 /CC31IO26

P8.0 /CC16IO9

P8.1 /CC17IO10

P8.2 /CC18IO11

P8.3 /CC19IO12

P8.4 /CC20IO13

P8.5 /CC21IO14

P8.6 /CC22IO15

P8.7 /CC23IO16

Vss

143

Vss

139

Vss

127

Vss

110

Vss

94

Vss

83

Vss

71

Vss

55

Vss

45

Vss

18

Agn

d38

Vcc

144

Vcc

136

Vcc

126

Vcc

82

Vcc

72

Vcc

17

Vcc

56

Vcc

46

V re f37

O W E84

12

3

JP8 13

2

12

3

JP9 13

2

U 4

M A X 6 3 1 5

R E S E T2

M R3

D S 1

HC16201 -AD 0

7D 18D 29D 310D 411D 512D 613D 714

E6

R / W5

R S4

V 03

Vcc2

G N D1

R 5 7 100

R 5 5

17

Power Supply Schematic

D K 4 0 0 0 B

DK4000 Dev board, 167CR

B

2 2Tuesday, May 16, 2000

Title

Size Document Number Rev

Date: Sheet of

V C C

V C C V C C

V C C

V C C

V C C

V C C

M R

P B 0

N M I

ADIO[15. .0 ]

PD[3. .0]

A[7..0]

A[15. .8]

P6.[7. .0]

P8.[7. .0]

PA[7. .0]

PE[7. .0]

C N T L 0 ( _ W R )CNTL1(_RD)

R E S E TCNTL2(_BHE)

P5.[15. .0]

G N D

A[23. .16]

T X D 0R X D 0

EXTERNAL POWERSUPPLY

+

9 -12 VDCR E G U L A T E D SOURCE

pads for 9VBATTERY

INTERNALPOWERSUPPLY

JTAG IN JTAG OUT

NO CHAIN

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

167CR Clock Options

Power On

G N D

G N D

PE0 /TMS

J E N

R S T

TRST

STAT

PE3/ TSTAT

G N D

G N D

G N D

V C C

PE4 / TERRT E R R

R S T

STAT

PE3/ TSTATTSTATTDITDIP E 2

T D O

T D O _ 1

T D OP E 3

TDI_2

TDI_2

TSTATP E 4

T M SP E 0

PE4 / TERR

T C KG N D

T C KP E 1

T E R RP E 5

V C C

M R

TRST

J E N

J E N

PE0 /TMST M S

STAT

T C K

P A 5

P A 6

P A 4

P A 1

P A 0

P A 2

P A 3

P A 7

ADIO0ADIO1ADIO2ADIO3ADIO4ADIO5ADIO6ADIO7ADIO8ADIO9ADIO10ADIO11ADIO12ADIO13ADIO14ADIO15

G N DV C C V C C

G N D

R E S E TCNTL2(_BHE)

C N T L 0 ( _ _ W R )P D 3P D 2P D 1P D 0

A23A22A21A20A19A18A17A16

A15A14A13A12A11A10A 9A 8

A 7A 6A 5A 4A 3A 2A 1A 0

G N DV C C

ADIO[15. .0 ]

PD[3. .0]

A[15. .8]

P6.0P6.1P6.2

P6.4P6.5P6.6P6.7

P8.0P8.1P8.2P8.3P8.4P8.5P8.6

P8.7

G N DV C C

T D O _ 2

P6.[7. .0]

P8.[7. .0]

PA[7. .0]

P6.3

PA[7. .0]

PE[7. .0]

P5. [15. .0]

P5.0 P5.8

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

P5.9

P5.10

P5.11

P5.12

P5.13

P5.14

P5.15

ADIO15

ADIO14

ADIO13

A[7..0]

CNTL1 (__RD)

A[23. .16]

T X D 0R X D 0

R 1 3

10k

C 1 7

0.01 uF

D 3

1 N 4 0 0 4

C 1 10.1 uF

D 4

1 N 4 0 0 4

D 2

1 N 4 0 0 4

C 1 21 uF

+ C 1 01

C 1 5

0.01 uF

D 1

1 N 4 0 0 4

C 1 4

0.1 uF

D 6 1 N 4 1 4 8

R 1 2

10k

J7

12

C 1 3

0.1 uF

C 1 6

0.01 uF

D 5

15V

P 2

C O N 1 4

1234567891011121314

R22

10K R23

10K

P 1

C O N 1 4

1234567891011121314

R21

10K

typ

R14

R15

R16

R17

R18

R19

R20

D 7 L E D

D 8 L E D

D 9 L E D

D 1 0 L E D

D 1 1 L E D

D 1 2 L E D

D 1 3 L E D

D 1 4 L E D

R 2 4

820R 2 5

820R 2 6

820R 2 7

820

R 2 8

820R 2 9

820R 3 0

820R 3 1

820

P13123456789

1011121314151617181920

P14123456789

1011121314151617181920

P15123456789

1011121314151617181920

C 2 0

0.01 uF

C 2 2

0.01 uF

C 2 4

0.01 uF

+C 2 1

1

+C 2 3

1

+C 2 5

1

P16123456789

1011121314151617181920

C 2 6

0.01 uF

+C 2 7

1

1 2 3

JP3

1 3

2

12

12

S 3

P O W E R1 2

R 3 910k

R 3 810k

R 3 710k

R 3 610k

R 3 510k

R 3 410k

R 3 310k

R 3 210k

R 4 710k

R 5 610k

R 4 510k

R 4 410k

R 4 310k

R 4 210k

R 4 110k

R 4 010k

C 3 6

0.1 uF

C 3 7

0.1 uF

C 2 8

0.1 uF

C 2 9

0.1 uF

C 3 0

0.1 uF

C 3 1

0.1 uF

C 3 2

0.1 uF

C 3 3

0.1 uF

C 3 4

0.1 uF

C 3 5

0.1 uF

TP_PS1

1

T P _ G N D

1

JP7

13

2

R 5 0

10k

R 4 9

10k

R 4 8

10k

JP5

13

2

JP6

13

2

U 6 MIC5237-5 .0

IN1

GN

D2

O U T3

TA

B4

JP2

1

5

3

6

4

2

D 1 5 L E D R 5 3

820

18

XA Daughter Board Schematic

A

1 1Fr iday, August 25, 2000

BXA Daughte r Board Schemat ic , DK4000Size D o c u m e n t N u m b e r R e v

Date : Sheet of

V C C

A D I O 0A D I O 1A D I O 2A D I O 3A D I O 4A D I O 5A D I O 6A D I O 7A D I O 8A D I O 9A D I O 1 0A D I O 1 1A D I O 1 2A D I O 1 3A D I O 1 4A D I O 1 5

G N DV C C

C N T L 2 ( _ P S E N )C N T L 1 ( _ R D )

P D 3P D 2P D 1

A 2 3A 2 2A 2 1A 2 0A 1 9A 1 8A 1 7A 1 6

T X D 0R X D 0

V C C

A 0A 1A 2A 3A 4A 5A 6A 7

A 8A 9

A 1 1A 1 2A 1 3A 1 4A 1 5

V C C

ADIO[15. .0 ]

PD[3. .0 ]

R E S E T

C N T L 0 ( _ W R )

P D 0

A[23. .16]

V C C

G N D

A D I O 0A D I O 1A D I O 2A D I O 3A D I O 4A D I O 5A D I O 6A D I O 7

A D I O 9A D I O 1 0A D I O 1 1A D I O 1 2A D I O 1 3A D I O 1 4A D I O 1 5A 1

A 2A 3

A D I O 8

A 0

P D 3

P D 0

R X D 1T X D 1T2T 2 E X

INT1T0

INT0INT1

T0

A 1 0

G N D

INT0

J13123456789

1011121314151617181920

J14123456789

1011121314151617181920

J15123456789

1011121314151617181920

J16123456789

1011121314151617181920

R 11 0 M

C 1 022p f

C 922p f Y1

x x _ M H z

12

34 Y2x x _ M H z

12

3C 20.1 uF

+ C 1

1

C 40.1 uF

+ C 3

1

C 80.1

+C 71

C 60.1 uF

+ C 5

1

U 1

XA-G3

P0.0 /A4D043

P0.0 /A5D142

P0.2 /A6D241

P0.3 /A7D340

P0.4 /A8D439

P0.5 /A9D538

P0.6 /A10D637

P0.7 /A11D736

P2.0 /A12D824

P S E N32

A L E33

X T A L 121

X T A L 220

R S T10

Vss

1

P 1 . 0 / A 0 / W R H2

P1.1 /A13

P1.2 /A24

P1.3 /A35

P1 .4 /RxD16

P1.5 /TxD17

P1.6 /T28

P1.7 /T2EX9

P3 .0 /RxD011

P3.1 /TxD013

P3.2 / INT014

P3.3 / INT115

P3.4 /T016

P 3 . 5 / T 1 / B U S W17

P 3 . 6 / W R L18

P3 .7 / RD19

Vss

22

Vdd

23

Vdd

44

P2 .1 /A13D925

P2.2 /A14D1026

P2.3 /A15D1127

P2.4 /A16D1228

P2.5 /A17D1329

P2.6 /A18D1430

P2.7 /A19D1531

E A / V p p / W A I T35

C 1 20.1 uF

+ C 1 1

1

R 21 0 K

R 31 0 K

R 41 0 K

19

DK4000 Parts List

eval board parts list 5/17/2000 tmwDK4000 QTY GENERIC ref des PER P/N DESCRIPTION VENDOR PART NUMBER 1 pcbevm0002 asian 21insq, us 25 in sq@ ds1 1 dis101-0001 display hantronix hdm16216h-b y1 1 y101-0002 crystal, 11.059MHZ digikey CTX078-ND u1 1 umcu0002 microcontroller Phillips P51XAu2 1 PSD42xxG ST PSD42xxG psd socket Yamiachi IC149-080-030-S5

u3 1 u232-0001 232 driveranalogdevices adm202jrn

u4 1 usup0002 max 6315 maxim, 5v max6315leuk u6 1 ureg-0001 regulator micrel mic5237-5.0bt d1-4 4 cr101-0001 diode s1abd5 1 vr101-0001 zener diode, 15v motorola mmsz5254bt1d6 1 cr101-0002 signal diode national fdLL4148d7-15 9 led101-0002 led, t5(t1.75) lumex SLX-LX5093ID c1-2 2 cap0805-2209 22 pf caps, cer murata grm40c0g22050adc10,c21,c23,c25 4 cap1206-1004 cap, 1uf tant murata grm42-6y5v105z016adc12,c19 2 cap1206-1004 cap, 1uf cer, 1206 AVX 1206zc105mat2ac3-9,c11, c13-18,c20,c22, c24 18 cap0805-1003 0.1 cap, smt, cer murata grm40z5u104z016ad

20

C40 1 cap0805-1009 r1 1 res0805-1005 resistor, smt, 10M, 1/8 watt, 0805 samsung rm10j106ctr2-4, R57 3 res0805-1000 resistor, smt, 100, 1/8 watt samsung rm12j101ctr5-10, r12-r23, r32-47, R54, R55 35 res0805-1002 resistor, smt, 10k, 1/8 watt, 0805 samsung rm10f1002ctr11 1 variable resistor, 10k digikey 3309P-103-NDR24-31, R53 9 res0805-8200 resistor, smt. 820, 1/8 watt rm10f820ctjp1, jp3 2 con225-1003 3 position header samtec tsw-103-23-L-s-LLj1,j3 2 rec225-1002 shunt (use with jpx above) samtec snt-100-bk-gjp2 1 con225-3003 post 3x3 samtec tsw-103-23-L-T-LLj2 1 rec225-3002 triple shunt (use with jp3) samtec mnt-103-bk-g

j4 1 con232-0001rt angle rs232 connector(female, 9pin) amp 745988-4

s1 1 sw102-0001 reset switch, momentary bourns 7914gs2 1 swdip0004 4 position dip switch,side actuated cts 195-4msts3 0 sw101-0002 on-off switch digikey EG1906-ND 1 t1 1 tr101-0001 class 2 transformer, 500ma,female digikey dpd090050-p-5j7 1 con103-0001 connector for ps, male digikey pj-202a 1 7x2 ribbon connector samtec p1 1 con104-2007 jtag connectors samtec tst-107-01-L-D-LL P13-P16 4

1 con225-101414 pin single in line connector/spacer(display) samtec dw-14-17-T-S-250-LL

4 std102-0250 standoffs for board richco SRS4-5-01 2 std101-0250 standoffs for display, 0.250 richco dlcbsat-4-01tp_ps,tp_gnd 2 tp101-0001 test points koa rcw 2 riv101-0281 rivet rivet king c-1 (std tubular rivet)

21

Appendix D: FlashLINK Information

Features• Allows PC parallel port to communicate with PSD9xx via PSDsoft Express• Provides interface medium for JTAG communications• Supports basic IEEE 1149.1 JTAG signals (TCK, TMS, TDI, TDO)• Supports additional signals to enhance download speed ( TERR, TSTAT)• Can be used for programming and/or testing• Wide power supply range of 2.7 to 5.5v• Pinout independent with target side flying leads• Convenient desktop packaging allows varying applications (desk, lab or production)• Synchronous JTAG interface allows speeds as fast as pc parallel port can drive

OverviewFlashlink is a hardware interface from a standard PC parallel port to one or more PSD8xx/9xxdevices located within a target PC board, as shown below. This interface cable allows the PSDto be exercised for purposes of programming and/or testing. PSDsoft Express/PSDsoft2000 isthe source for driving FlashLINK.

M ate s w ithP C pa ra lle l

po rt

F la sh L in kad ap te r

6 feet

12 W IR ES

6 inches

T a rge tde v ic e

F ly ing le adca b le

Figure 12 Typical FlashLINK application

Operating considerationsOperating power for FlashLINK is derived from the target system in the range of 2.7 to 5.5 v.Compatibility over this voltage range is ensured by the design of FlashLINK. No settings areinvolved.

On a cautionary note, it is recommended that the target system be powered by a regulated andstable source of power, which is energized at the final value of Vcc. It is not recommended thatthe input voltage be varied using the verneer on a regulated power supply, as this may cause theinternal FlashLINK IC’s (74VHC240) to misoperate toward the lower end of the supply range.

Each FlashLINK is packaged with a six-inch "flying lead" cable for maximum adaptability. Aribbon cable requires the use a certain connector and pin configuration on the target assembly.This flying lead cable mates to the FlashLINK adapter on one end and has loose sockets on theother end to slide onto 0.025” square posts on the target assembly.

22

The signals are defined in the following table.

PIN#

SIGNALNAME

DESCRIPTION Type Flashlink isSignal

1 JEN\ Enables JTAG-ISP pins on PSD. Onlyused when JTAG-ISP signals aremultiplexed with other I/O.(optional)

OC,100K Source

2 TRST\ * JTAG reset on target (optional per1149.1)

OC,10K Source

3 GND Signal ground4 CNTL * Generic control signal, (optional) OC,10K Source5 TDI JTAG IEEE 1149.1 serial data input Source6 TSTAT JTAG-ISP programming status (optional) Destination7 Vcc VDC Source from target (2.7 - 5.5 VDC)8 RST\ Target system reset (recommended) OC,10K Source9 TMS JTAG IEEE 1149.1 mode select Source10 GND Signal ground11 TCK JTAG IEEE 1149.1 clock Source

12 GND Signal ground13 TDO JTAG IEEE 1149.1 serial data output Destination14 TERR\ JTAG-ISP programming error (optional) Destination

Notes 1. Bold signals are required connections 2. All signal grounds are connected inside FlashLINK adapter 3. OC = open collector, pulled-up to Vcc inside FlashLINK adapter 4. * = Not supported by PSDsoft, signals remain inactive. 5. The target device must supply Vcc to the FlashLINK Adapter (2.7 to 5.5 VDC, 15mA max @ 5.5V).

Figure 13 Pin descriptions for FlashLINK adapter assembly

All 14 signals may not be needed for a given application. Here's how they break down:

(6) Required signals (four JTAG-ISP pin config): TDI, TDO, TMS, TCK, Vcc, GND

(2) Optional signals for faster ISP (6 JTAG-ISP pin config): TSTAT, TERR\

(1) Optional signal to control multiplexing of the JTAG signals: JEN\

(1) Recommended signal to allow FlashLINK to reset target system during and after ISP: RST\

(1) Optional IEEE-1149.1 signal for JTAG chain reset: TRST\

(1) Optional generic control signal from FlashLINK to target system: CNTL

(2) Two additional ground lines to help reduce EMI if a ribbon cable is used. These ground lines "sandwich" the TCK signal in the ribbon cable. These lines are not needed for use with the flying lead cable. That is why the flying lead cable has only 12 of 14 wires populated.

23

FlashLINK pinoutsThere is still no industry "standard" JTAG connector. Each manufacturer differs. ST has aspecific connector and pinout for the FlashLINK programmer adapter. The connector scheme onthe FlashLINK adapter can accept a standard 14 pin ribbon connector (2 rows of 7 pins on 0.1"centers, standard keying) or any other user specific connector that can slide onto 0.025" squareposts. The pinout for the FlashLINK adapter connector is shown in the previous Figure.

A standard ribbon cable is good way to quickly connect to the target circuit board. If a ribboncable is used, then the receiving connector on the target system should be the same connectortype with the same pinout as the FlashLINK adapter shown in Figure 4. Keep in mind that theJTAG signal TDI is sourced from the FlashLINK adapter and should be routed on the target circuitcard so that it connects to the TDI input pin of the PSD device. Although the name "TDI" infers"Data In" by convention, it is an output from FlashLINK and an input to the PSD device. Alsokeep in mind that the JTAG signal TDO is an input received by the FlashLINK adapter and issourced by the PSD device on the TDO output pin. See App note 54 for further details.

Figure 7 - Pinout for FlashLINK Adapter and Target System

Each FlashLINK is sold with a six-inch "flying lead" cable for maximum adaptability since a ribboncable requires the use a certain connector on the target assembly. This flying lead cable mates tothe FlashLINK adapter on one end and has loose sockets on the other end to slide onto 0.025square posts on the target assembly.

7'2

7&.

706

9&&

7',

*1'

-(1

7(55

*1'

*1'

567

767$7

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7567

14

12

10

13

11

9

78

6 5

4 3

2 1

K E YW A Y

VIEW : LO O K IN G IN T O FA C E O FS H R O U D E D M A LE C O N N E C T O R .0 .025" P O S T S O N 0 .1 " C E N T E R S .

C onnec to r re fe rence : M o lex 70247-1401

S T JTAG-ISP CONNECTOR DEFINITION

R ecom m ended ribbon cab le fo r qu ickconnec tion o f F lashL ink adap te r to endproduc t:S am tec : H C S D -07-D -06 .00 -01 -S -N o rD ig ikey : M 3C C K -14065-N D

N ote :T D I is a s igna l source on the F lash linkand a s igna l des tina tion on the ta rge tboa rd .

T D O is a s igna l des tina tion on theF lashL ink and a s igna l sou rce on theta rge t boa rd .

24

Figure 14 JTAG Chaining Example

V cc

TM STC K

TD I

TS TA TT ER R

TD O

JENT RS TG N D*C N TL

R S TG N D*G N D*

Device 1

F lash PS D

TM STC K

TD ITD O

TS TA TTE R R \

13

6

9

11

5

14

Target System , 3v or 5v

stra ight throughribbon cable

2 row, 7 position

V cc

7

op tiona lop tiona l

op tiona l

op tiona l

op tiona lrecom m ended

12348

1012

* a ll ground p ins areconnected toge the r ins ide

flash link assem bly

F lash PS D

TM STC K

TD ITD O

A ny JTAGD evice in

B yP ass M ode

Device 2

Device N

FlashLinkAdapterConncetor

S ystemR eset

C ircu itry

9

11

13

5

614

7

12

12348

10

TM S

TC K

TD ITD O

TS TA TTE R R \

R ec om m e nde dbu ffe r ing fo r so m e

P S D s 1

1 B uffering recom m ended for PS D 813/833 /834/ 913 /934 only. N ot requ ired on P S D4000 series o r P S D835 /935.

25

Flas hL ink PCB G 1

Flas hL ink Sc hematic

Wa fers c ale Integr a tion

47280 Kato RoadFre mont , CA 94538

B

1 1Monday , Ju ly 26 , 1999

Title

S iz e Doc ument Number Rev

Date: Sheet of

V CC

V CC

V CC V CC

V CC

V CC

V CC

V CC

SOLDERING PAD PATTERN

(DRAIN WIRE)

(FRAME GND)

(FOR U2) (FOR U3)

(FOR U1)

white

redorgpinkyellowgreenlt green

greyblackorgtbrnt

TDI

V CCIN

TMS

TCK

TS TA TN

TRSTN/JEN

CO NTROL

RSTN

TDOTERRN

SHIELD

D6 DB8

SEL DB13

G ND

D4(TRST)DB6

ERRN DB15

D0(TCK) DB2

A CKN DB10

D5(RST) DB7

D2(TDI) DB4D1(TMS) DB3

BUSY DB11

D3(J EN\) DB5

DB14A UTO LINE FEED

DB12PA P

G ND

G ND DB18

D16. 2V

P1

70247- 1401MO LEX

1234567891011121314

R1247R1347

R1447

R50 10

C50

1UF

C240. 01UF

R51

100K

R810

U1B

74V HC240

A 417

A 315

A 213

A 111

G19

Y 43

Y 35

Y 27

Y 19 R1547

R1847

R1747

R1647

R2047

R1947

U2B

74A C05

3 4

U2C

74A C05

5 6

R2210K

U3C

74A C05

56

U3B

74A C05

3 4

U3E

74A C05

1110

R2147

U3D

74A C05

98

U3A

74A C05

1 2

R2310K

R39

10K

R41 4. 7K

R26

10K

C250. 01UF C260. 01UF

U2D

74A C05

9 8

R3010K

R31100K

R32100K

R33100K

U2E

74A C05

11 10

U2F

74A C05

13 12

U3F

74A C05

13 12

S1

PA D1

1

S2

PA D1

1R800

R3510K

R34

100K

R3610K

R3710K

R3810K

C51

0. 01UF

D3

4148

Q 12N3904

3

2

1

D2

4148

R40

10K

R25470K

R424. 7K

R434. 7K

R284. 7K

C52

100p

f

R294. 7K

C55

100p

f

C53

100p

f

C54

100p

f

R647

U1A

74V HC240

A 12

A 24

A 36

A 48

G1

Y 118

Y 216

Y 314

Y 412R447

R847

U2A

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R247

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R947

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26

Loop back connector schematic

14 pin dual row 0.02 5 sqrecepta cle(polarized , same as cab le 5)

to flas hlinkassy

VCC

GND

PC outp utsignal

PC intp utsignal

TDI !TSTAT

!TERRTMS

TCK !TDO

PC conn ectorline

ACKN (8 )

ERRN (1 0)

PAP (9)

TS TA T

TMS

TDO

V CC

TCK

TDI

TERR

G ND

J1

CO N1

1

J2

CO N2

1

J1

CO N14

123456789

1011121314

Figure 15 Loop Back Tester, Passive, FlashLINK

27

Appendix E Results codes and debug tree for htestXA.obj

Results codes

binaryResults = abcd

0 0000Success Code

1 00012 00103 00114 01005 01016 01107 01118 10009 1001A 1010B 1011C 1100D 1101E 1110F 1111

Table 1 Hex to Binary Conversion

Debug tree

X = don’t carea b c d action

x x x 1 Page register test Replace PSD ( U1 on EVD) and retestx x 1 x PSD ram error Replace PSD ( U1 on EVD) and retestx 1 x x External Ram error Replace SRAM (U3 EVM) and retest1 x x x UART error Repair U4 or surrounding circuitry,

EVM (this is under the EVD board)

Table 2 Debug Tree

28

Appendix F: Board errataFollowing is a brief list of issues with correlated on a revision level basis

Mother boardRev C. JP10 added for XA display functionality.

Rev B. hardware mod for display-XA functionality.

Daughter board (XA)Rev B initial release

DK4_XA - USER MANUAL

2/3

Table 1. Document Revision History

Date Rev. Description of Revision

1.0 Document written in the WSI format

31-Jan-2002 1.1

DK4_XA: DK4000-XA Development Kit For PSD4000 Series of Flash PSDsFront page, and back two pages, in ST format, added to the PDF fileAny references to Waferscale, WSI, EasyFLASH and PSDsoft 2000updated to ST, ST, Flash+PSD and PSDsoft Express

3/3

DK4_XA - USER MANUAL

For current information on PSD products, please consult our pages on the world wide web:www.st.com/psm

If you have any questions or suggestions concerning the matters raised in this document, please sendthem to the following electronic mail addresses:

apps.psd@st.com (for application support)

ask.memory@st.com (for general enquiries)

Please remember to include your name, company, location, telephone number and fax number.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

© 2002 STMicroelectronics - All Rights Reserved

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