Distributed Architecture for Robust and Optimal Control of ...web.eecs.umich.edu/~mayankb/docs/tie_preprint.pdf · IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Distributed Architecture

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Distributed Architecture for Robust and OptimalControl of DC Microgrids

Mayank Baranwal 1,a, Alireza Askarian, 1,b, Student Member, IEEE, Srinivasa Salapaka, 1,c, Member, IEEE,and Murti Salapaka, 2,d, Senior Member, IEEE

Abstract—This article presents a distributed, robust andoptimal control architecture for a network of multiple DC-DC converters. The network of converters considered forma DC microgrid in order to regulate a desired DC bus voltageand meet prescribed time-varying power sharing criteriaamong different energy sources. Such coordinated micro-grids provide an important framework for leveraging thebenefits of distributed power generation and consumption.The proposed control design seamlessly accommodatescommunication architectures that range from centralized todecentralized scenarios with graceful degradation of per-formance with lessened communication ability. Moreover,methods developed are applicable to the case where thedesired proportion in which the sources provide powervaries with time. A distinguishing feature of the controldesign approach is that it regards the net load current as adisturbance signal, lending itself to tractable analysis withtools from robust and optimal control theory. A quantifiableanalysis of the closed-loop stability and performance of thenetwork of converters is performed; the analysis simpli-fies to studying closed-loop performance of an equivalentsingle-converter system. The control approach is demon-strated through simulations and experiments.

Index Terms—Microgrid, Converters, Power Sharing, Ro-bust Control, Distributed Control.

I. INTRODUCTION

INCREASING use of renewable generation and dis-tributed energy resources (DERs), such as residen-

tial solar, and electric vehicles coupled with customers’changing energy usage patterns are leading to greateruncertainty and variability in the electric grid. Newflexible architectures are required that can accommodatethe increase in renewable generation and DERs, whileproviding the quality of service, resiliency, and reliabilitythat customers expect.

Coordinated microgrids provide an important frame-work for leveraging benefits of distributed power gen-eration and consumption. Microgrids also help mitigatechallenges arising from DERs penetration into the grid

1Department of Mechanical Science and Engineering, University ofIllinois at Urbana-Champaign, 61801 IL, USA

2Department of Electrical and Computer Engineering, University ofMinnesota, Minneapolis, 55455 MN, USA

[email protected], [email protected],[email protected], [email protected]∗The authors would like to acknowledge ARPA-E NODES program

for supporting this work. Part of this work was presented at the IEEEAmerican Control Conference (ACC), May 24-26, 2017 [1].

by enabling management of demand response and gen-eration [2], [3]. Fig. 1 shows a schematic view of a

Fig. 1: A schematic of a microgrid. A network of multiple DCsources are arranged in parallel through an array of DC-DCconverters to regulate voltage and provide power at the DC-link. The DC-link either interfaces with DC loads directly, or toa DC/AC inverter to satisfy the power demands of AC loads.

microgrid system with multiple DC sources in parallel.The power aggregated at the DC-link can directly feedDC loads, and can be used by a DC-AC inverter tointerface with AC loads and the utility grid. The voltageand power at the DC-link is manipulated by suitablycontrolling duty-cycle of the switches of DC-DC con-verters at each power source. The primary objectivesof controller are to regulate the voltage at the DC-link,while ascertaining that the various power generationsources are utilized in the specified priority order andproportion to meet the load demand.

The main challenges in the control of microgrids arisefrom uncertainties in renewable power sources such as,solar and wind due to intermittent power generation,uncertainties in load demands and schedules, and indistributed topology of power sources that are spatiallyscattered due to location and size constraints. In viewof these challenges, a robust and distributed controltechnology is needed for reliable operation of smartmicrogrids. In the multiple-input multiple-output settingnecessitated by the need to control multiple generationsources, it is difficult to address robustness and per-formance criteria in the conventional PID-based con-trol synthesis framework. Recently robust and optimal


control methodologies have received attention. In [4],a linear-matrix-inequality (LMI) based robust controldesign is presented for boost converters which demon-strates significant improvements in voltage regulationover PID based control designs. In [5]–[7], robust H∞-control framework is employed in the context of invertersystems. While the issue of current sharing is extensivelystudied (see [8] and [9]), most prior methods reportedassume a single power source. Our preliminary work[10] uses tools from robust control theory [11], [12] topartially address control objectives pertaining to man-aging multiple generation sources. However, a majordrawback of the design suggested in [10] is that it failsto provide analyzable guarantees to time-varying powersharing requirements, and is thus suited for cases wherepower sharing is required in a fixed prespecified propor-tion. Although, there is significant literature on controland power management techniques for AC microgrids[13], [14], recent works [15], [16] have emphasized theimportance of DC microgrids due to their islandingcapabilities in presence of voltage fluctuations and ca-pability to facilitate integration of DERs. In this article,we present a distributed robust control architecture fora network of parallel DC-DC converters that simultane-ously addresses multiple objectives of regulating the DClink voltage and ascertaining that the specification onthe prioritization and proportion of power generationare met robustly in the presence of modeling, powergeneration, and load demand uncertainty.

The main contributions of this article are (a) robustregulation and sharing performance: Appropriate maps ofthe duty cycle are identified that facilitate a commonframework for analyzing and synthesizing controllers fordifferent types of converters while rendering models thatare linear. Modern robust control tools are employed toto address multiple objectives that include regulation ofthe DC-link voltage to a desired set-point reference, anda prescribed sharing of power among different DERs.The sharing requirements can be time-varying and areoften dictated by the availability and relative costs ofdifferent power sources. Our architecture allows sharingspecifications that include priorities on the order inwhich different sources and loads are utilized. For ex-ample, a priority specification of the form, PV ≺ Battery≺ EV, is natural which codifies the following objective:irrespective of the changing power generation of the PV,the state of charge of the battery and the EV, the EV willsource power only if the battery and the PV cannot meetthe power demand, while the battery sources power onlyif the PV is not able to meet the load demand. Apartfrom meeting performance guarantees including priori-tization, our control design also addresses the challengesof interfacing AC loads, including the 120 Hz ripplethat has to be provided by the DC sources. It providesa means for achieving a trade off between the 120 Hzripple on the total current provided by the power sourcesand the ripple on the DC-link voltage.

The networked system resulting from our architecture

is robust to uncertainties in load demands and sched-ules, communication topologies, system parameters, andnoise in measurement signals. (b) modular and structuredarchitecture: The control architecture presented in thiswork is modular and facilitates plug and play operation.Here, a new converter module can be added or removedfrom the network, without any need to redesign con-trollers and without compromising the voltage regula-tion performance of the network. Furthermore, addinga module, which is agnostic to sharing ratios of othermodules, to the networked system does not affect theoverall performance of the networked system. The intra-module and inter-module control is structured in such away that it allows easy multi-converter network analysisand synthesis. In the framework developed, the networkof parallel converters can be analyzed, and the corre-sponding control systems synthesized, in terms of anequivalent single-converter system. (c) robustness to com-munication uncertainties: The synthesis procedure resultsin a single controller which functions for the entire rangeof communication capabilities; from decentralized tocentralized. Here, it guarantees precise regulation of theDC-link voltage and power sharing specifications whencommunication allows for a centralized operation, andmeets gracefully degraded specifications with lessenedcommunication capabilities among converters.

II. PRELIMINARIES: FACILITATING LINEAR MODELS OFDC-DC CONVERTERS

Fig. 2a shows a schematic of a boost converter withoutput voltage V and input voltage Vg. If d(t) representsthe duty-cycle (or the proportion of ON duration) forthe semiconductor switch at time t, then the averageddynamic model of a boost converter is described by:

LdiL(t)

dt= −(1− d(t))V(t) + Vg,

CdV(t)

dt= (1− d(t))iL(t)− iload(t), (1)

where, iL(t) is the averaged inductor current, and Land C denote the converter inductance and capacitance,respectively [17], [18]. By defining d′(t) , 1− d(t) as thecomplementary duty-cycle and D′ , (Vg/Vref), whereVref > Vg is the desired output voltage, (1) can berewritten as:

L ˙iL(t) = u, CV(t) = (D′ + d(t))︸︷︷︸≈α

iL(t)− iload(t), (2)

where u(t) := Vg − d′(t)V(t). In this model, the con-stant α = D′ approximates the term D′ + d(t), sinced(t) = d′(t) − D′ is typically small. Note that theequivalent duty cycle d(t) can be obtained from u via

d(t) = 1−Vg − u(t)

V(t). In (2) load current iload appears as

a disturbance signal, and thus an appropriate controllercan be synthesized for rejecting this disturbance.

The averaged dynamical equations for other convertertopologies (see Figs. 2b and 2c) can be derived in asimilar manner, and they result in dynamic models thatare structurally identical to the boost converter model


(a) (b) (c)

Fig. 2: Circuit representing (a) Boost converter, (b)Buck converter, and (c) Buck-Boost converter. Voltage V at the output isregulated by repeatedly turning ON/OFF the switch between input and output. Note that iload includes both the nominal loadcurrent, as well as ripple current. The converters are assumed to operate in continuous-conduction-mode (CCM).

(2). Buck converter results in the same dynamic modelas (2) with u = −V(t) + d(t)Vg and α = 1. Similarly,the buck-boost converter is modeled by (2) with u =V(t) + d(t)(Vg −V(t)) and α = −D′.

Remark: Note that the way the input variables u arechosen in these models is critical which results in lineardynamic model (2) even though the maps from originalcontrol input d(t) to inductor current and voltage arenon-linear. This structure enables linear control design,where u(t) is synthesized, and the corresponding duty-cycle be implemented is determined using the invertiblemap between u and d(t). Since the averaged modelsfor the boost, buck, and buck-boost converters are struc-turally identical, one can easily derive the control designof one from the other. For brevity and as a result ofthis equivalence, we present a control design method forboost-type converters.

III. CONTROL OBJECTIVES AND DESIGN

The proposed work simultaneously addresses the fol-lowing primary objectives (in the context of Figs. 1 and2) : (a) Effective regulation of the DC-link voltage V toa pre-specified setpoint value Vref in presence of time-varying loads (manifested through iload), uncertainties ininput voltage Vg, and parametric uncertainties in L and Cvalues, (b) Time-varying current (power) sharing amongmultiple sources that ensures that current (power) out-puts ik from the kth converter tracks a time-varying sig-nal irefk

, and (c) Managing 120 Hz ripple current trade-offbetween the total current, i = ∑ ik sourced by DC sourcesand the DC-link capacitor current iC. Note that in thisnetwork, each controller interfaced with a DC-DC con-verter has access to its own measurement of the DC-linkvoltage V and its inductor current. Furthermore, eachcontroller is provided with a reference voltage commandVref, common nominal reference current iref, and power-sharing proportion γk (see Fig. 4). Also the uncertainexogenous input at kth converter is iload−∑j 6=k ij, whichis equal to (1 − γk)iload, when all the controllers aresatisfying the power sharing requirements. In such acase, the knowledge of iload(t) is sufficient for voltageregulation and power sharing objectives. Therefore inthe centralized setting, it is assumed that a controllercan additionally measure or estimate the net load currentiload, and set iref = iload. In the decentralized case iload

is not known at each controller (iref is set at a nominalvalue). We first describe a control scheme for a singleconverter which forms a basis for the analysis and designof distributed control architecture for a system networkof multiple converters in parallel described in SectionIII-B.

A. Control Design for Single Converter

Fig. 3 depicts a block diagram representation of thethe proposed inner-outer control design. Note that acascade inner-current outer-voltage control architectureis preferred over a traditional single measurement con-troller for voltage tracking and load disturbance rejec-tion, primarily due to fast current dynamics over slowvoltage dynamics [19], [20]. In fact, it is shown in [21]that the cascaded inner-current outer-voltage structureis an optimal strategy in terms of voltage regulationand robustness, when both bus voltage V and inductorcurrent iL are measured. The inner controller is designedto achieve fast rejection to disturbance in current arisingdue to variations in the output load, while the primaryouter controller regulates the output voltage by gen-erating the required set-point for the inner loop. Thusthe inner current controller influences the outer voltageloop by affecting the primary process variable (voltagesignal) in a predictable and repeatable way. Here Kcrepresents the inner-loop controller which addresses theripple-current management objective, while [Kv, Kr] con-stitute the outer-loop controllers to address the DC-linkvoltage regulation and power sharing objectives. Therequirements on current sharing are imposed throughthe exogenous input iref (explained in Sec. III-B). iref isset to the measured (or communicated) value of loadcurrent iload when available, while in the absence of iloadmeasurement, iref is set to pre-specified nominal value.

1) Design of inner-loop controller: The primary objec-tives for designing the inner-loop controller Kc is toachieve the desired trade-off between the 120 Hz rippleon the capacitor current iC (or equivalently on the outputvoltage V) and the inductor current iL (see Fig. 2a), andensure robust tracking of the command u (in Fig. 3) bythe inductor current iL. The signal u is the reference com-mand generated by the outer-voltage controllers for theinner-controller that regulates iL. Here, Kc is designed


Fig. 3: Block diagram representation of the inner-outer controldesign. Exogenous signal Vref represents the desired outputvoltage. The quantities V, iload and iL represent the outputvoltage, load current and inductor current, respectively. Theregulated variables z1, z2, z3 and z4 correspond to weighted - (a)tracking error in DC-link voltage, (b) mismatch between irefand iload, (c) control effort u, and (d) output voltage tracking,respectively. Gv(s) , 1

sC represents the plant transfer functionfrom DC-link capacitor current to output voltage V.

such that the transfer function Gc (from u to iL) in Fig. 3is given by:

Gc(s) =(

ω

s + ω

)(s2 + 2ζ1ω0s + ω2

0s2 + 2ζ2ω0s + ω2

0

), (3)

where ω0 = 240π rad/s and ω, ζ1, ζ2 are design param-eters. Parameter ω > ω0 is chosen to implement a low-pass filter that attenuates undesirable frequency contentin iL beyond ω resulting from noisy measurements andswitching effects. Gc(s) also incorporates a notch at ω0 =120 Hz, where the “size” of the notch is determined bythe ratio ζ1/ζ2. Lower values of this ratio correspond toa larger notch magnitude, which in turn implies smaller120 Hz component in iL. Since iC = CV = D′iL − iload,the 120 Hz ripple in the load current is reflected as alarger ripple in V, when the proportion in iL is pushedlower. Thus the ratio ζ1/ζ2 regulates the trade-off be-tween 120 Hz ripple on inductor current iL and DC-linkvoltage V. The stabilizing second-order controller Kc thatyields the inner-closed loop plant Gc is given by:

Kc(s) = Lω(s2 + 2ζ1ω0s + ω2

0)

(s2 + 2ζ2ω0s + ω20 + 2(ζ2 − ζ1)ω0ω)

. (4)

The readers are encouraged to refer to Sec. III in [10]for further details on the inner-loop control design.

2) Design of outer-loop controller: For a specified innerclosed-loop plant Gc in (3), we now present a system-atic design for the outer controllers, [Kv Kr], shownin Fig. 3. The fundamental performance limitations ofthe proposed closed-loop design with inner closed-loop

plant Gc ,Kc

sL + Kcand outer controllers

[Kv Kr

]is

analyzed below by investigating the closed-loop dy-namical equation from reference voltage Vref, referencecurrent iref and load-current iload to DC-link voltage V.Furthermore, the closed-loop dynamics provides usefulinsights into the control methodology and explains howthe same architecture with identical controllers work forboth matched (iref = iload) and unmatched (iref 6= iload)conditions. Note that from Fig. 3, the DC-link voltage Vis given by,

V = Gv(−iload + D′Gc(Kve1 + Kre2)). (5)

Using e1 = Vref − V and e2 = iref + ηe1 − D′Gc(Kve1 +Kre2), the DC-link voltage in terms of exogenous signalsVref, iref and iload is given by:

V = TVrefVVref + GvTirefV (iref − iload)− GvSiload, (6)

where S = [1+ D′GcKr + D′GcGv(Kv + ηKr)]−1, TVrefV =[D′GcGv(Kv + ηKr)]S, and TirefV = D′GcKrS. Note thatS + TVrefV + TirefV = 1, where DC-gains of the aboveclosed-loop transfer functions are given by:

|TVrefV(j0)| = 1, |(GvTirefV)(j0)| = |Kr(j0)||Kv(j0) + ηKr(j0)|

and |(GvS)(j0)| = 1D′ (|Kv(j0) + ηKr(j0)|) . (7)

If the load current, iload, is measured and iref is set toiload, then it follows from (6) that in steady-state V ≈ Vref,provided the gain of sensitivity transfer function GvSat DC is made small. However in the absence of loadcurrent measurement, and assuming that at DC, thecontroller is synthesized to ensure GvS is small, thesteady-state DC-link voltage is given by:

V ≈ Vref +

(|Kr(j0)|

|Kv(j0) + ηKr(j0)|

)︸︷︷︸

κ(η)

(iref − iload) (8)

Thus in the unmatched case (iref 6= iload), the outputvoltage droops by an amount proportional to the mis-match (iref − iload) and the droop-gain.

The outer-controllers Kv and Kr are designed througha model-based multi-objective optimization problem. Informulating this problem, we first choose the outputvariables z1 ,W1e1, z2 ,W2e2, z3 ,W3u, and z4 ,W4V(see Fig. 3) that correspond to weighted (a) tracking errorof the DC-link voltage, (b) mismatch between iref andD′iL, (c) control effort u, and (d) output voltage tracking,respectively. The optimization problem of interest is tofind stabilizing outer-controllers [Kv Kr]T such that theH∞-norm of the closed-loop transfer function, Twz, fromw , [Vref iref iload]

T to z , [z1 z2 z3 z4]T is minimized.

The resulting optimization problem is:

argminKv ,Kr∈K

‖Twz‖∞, (9)

where K is a set of all proper-stabilizing controllers.Weights W1(jω) and W2(jω) are chosen to be large inthe frequency range [0, ωBW ] to ensure tracking errors,e1 = Vref−V, and e2 = iref + ηe1−D′iL, in this frequencyrange to be small. The design of weight function W3(jω)entails ensuring the control effort lies within saturationlimits. The weight function W4(jω) is designed as a high-pass filter to ensure that the transfer function from iloadto V is small at high frequencies, which mitigates effectsof measurement noise. The optimization problem (9) canbe solved efficiently using standard routines [22].

B. Extension to Multi-Converter SystemIn typical architectures, analysis and control synthesis

for a parallel network of DC-DC converters is complex,


Fig. 4: A multiple-converters system with shaped inner plantsGc. In the proposed implementation, we adopt the same outercontroller for different converters, that is, Kv1 = Kv2 = .. =

Kvm = 1m Kv and Kr1 = Kr2 = .. = Krm = Kr.

and optimal control design becomes untenable even fora moderate number of converters since the complexityscales with the number of converters. We propose amodular controller framework, where we impose struc-ture both within each module and across modules. Hereeach module comprises a power source along with itsDC-DC converter and the corresponding control system(see Fig. 4). This structure significantly simplifies theanalysis and synthesis problems for the DC microgrid;both these problems reduce to analyzing and designof an equivalent single converter problem described inSection III-A. This architecture makes optimal controldesign for multi-converter system tenable since it re-quires solving the optimization problem only for theequivalent system. We further show that this architectureis robust to perturbations in the assumed structure; forinstance if a new module is added that does not followthe structural constraints that we have assumed, thenetwork is still viable in terms of voltage regulation andpower sharing between the older sources.

The inter-modular structure is motivated from theobservation that the control design for voltage-regulationand reference-current tracking objectives are similaracross the modules; accordingly we impose that all theouter-controllers are identical, that is, Kvi = Kvj andKri = Krj for 1 ≤ i, j ≤ m (see Fig. 4). In orderto allow for controlled drooping of voltage, the signalγk(iref + η(Vref−V)) is fed to the kth outer controller Krk .The choice of γk dictates the power sharing requirementson the kth converter, and since it appears as a referencesignal input to the controller, it can be time-varying. Weshow in Theorem 1 that the proposed implementationdistributes the output power nearly in the proportionγ1 : γ2 : .. : γm.

The inner-controllers Kck are chosen such that theinner-shaped plants from uk to iLk are identical acrossk and are given by

Gc,nom(s) =(

ω

s + ω

)(s2 + 2ζ1,nomω0s + ω2

0s2 + 2ζ2,nomω0s + ω2

0

), (10)

where the ratio ζ1,nom/ζ2,nom determines the trade-off of120Hz ripple between the total output current D′iL =∑m

k=1 D′kiLk and the capacitor current iC. For given valuesof ζ1,nom, ζ2,nom and inductance Lk, explicit design of Kckexists and is given by (4). We further impose that outer-controllers Kvk = Kv/m and Krk = Kr for all k.

In particular, by our choice of inner and outer con-trollers, the transfer functions from external referencesVref, iref and iload to the desired output V are identicalfor all converters. Hence the entire network of parallelconverters can be analyzed in the context of an equiva-lent single converter system. Therefore,

Kvk

and

Krk

can be computed by solving H∞-optimization problem(as described in Sec. III-A2) similar to the single convertercase. These design specifications are made precise in thefollowing theorem.

The system representation in Fig. 3 is consideredequivalent to that in Fig. 4, when the transfer functionsfrom the reference voltage Vref, reference current iref,load current iload to the DC-link voltage V in Fig. 3 areidentical to the corresponding transfer functions in Fig. 4.

Theorem 1: Consider the single-converter system inFig. 3 with inner-shaped plant Gc,nom(s) given by (10),outer controllers Kv, Kr, droop-coefficient η, and ex-ternal references Vref, iload, iref; and the multi-convertersystem described in Fig. 4 with inner-shaped plantsGck = Gc,nom(s) and outer controllers

Kvk =

1m Kv

and

Krk = Kr

for all k = 1, . . . , m, droop-coefficient

η, and same external references Vref, iload and referencecurrent iref prescaled by time-varying scalars γk > 0for 1 ≤ k ≤ m. The following assertions hold:1. [System Equivalence]: If ∑m

k=1 γk = 1, then thesystem representation in Fig. 3 is equivalent to the systemrepresentation in Fig. 4.2. [Power Sharing]: For any two converters k and l,k, l ∈ 1, . . . , m in a multi-converter system shown inFig. 4, the difference in the corresponding steady-statescaled output currents is given by:∣∣∣∣D′k iLk

(j0)γk

− D′l iLl(j0)

γl

∣∣∣∣ ≤ (η|T1(j0)|+∣∣∣ 1

γk− 1

γl

∣∣∣ |T2(j0)|)|e1(j0)|,

(11)where, S1 := [(1 + D′Gc,nomKr)]−1, T1 := D′Gc,nomKrS1and T2 := D′Gc,nomKvS1/m. Furthermore, the steady-state tracking error e1 , Vref − V in DC-link voltagesatisfies in the centralized case, where, iref = iload,

|e1(j0)| ≤ 1D′(|Kv(j0) + ηKr(j0)|) |iref(j0)|, (12)

while in the decentralized case:

|e1(j0)| ≤ |Kr(j0)||iref(j0)|+ (D′|Kr(j0) + 1)|iload(j0)|D′(|Kv(j0) + ηKr(j0)|) . (13)

Proof: See Appendix for details.Remark 1: If the steady-state tracking error in DC-link voltage is zero, (that is, |e1(j0)| = 0) then from(11), we have perfect output power sharing given by|D′1iL1(j0)| : . . . : |D′miLm(j0)| = γ1 : . . . : γm. In practice


the tracking error e1 is not exactly zero, however, thetracking error is made practically insignificant throughan appropriate choice of controllers Kv, Kr with largegains at DC which result from the H∞ optimizationproblem in (9). Moreover, the design of the controllersis such that |Kv(j0)| < |Kr(j0)| resulting in |T1(j0)| ≤ 1and |T2(j0)| ≤ 1.Remark 2: From (11), it is evident that for near equalsharing, that is, γk ≈ γl , for all k, l ∈ 1, . . . , m, thesecond term on the RHS in (11) is ≈ 0, thereby resultingin a tighter bound on sharing performance.Remark 3: The architecture proposed in Fig. 4 also allowsfor proportional sharing of 120 Hz ripple current amongDC sources in a desired ratio. For instance, constraints onthe power sources may require that 120 Hz ripple com-ponent in the net output current ∑k ik must be sharedin some specified proportion β1 : · · · : βk. This can beaddressed by adjusting reference current iref commandto kth converter as irefk

= iref + (βk/γk)iref,120, whereiref,120 represents the desired 120 Hz ripple content intotal output current.Remark 4: The droop-like coefficient η controls the trade-off between voltage regulation and power sharing. Thisis evident from (11)-(13). A sufficiently large value ofη ensures small steady-state error in voltage regulation,however, at the expense of loose upper bound on powersharing performance reflected through (11).Remark 5: The proposed control design is also applicableto a mix of converter topologies connected in parallel.This is possible due to identical structure (described inSection II) of different converter models that can be ex-ploited to design identical inner closed-loop plant trans-fer function Gc(s), and therefore also identical outer-controllers.

IV. SIMULATION RESULTS

In this section, we demonstrate the effectiveness ofthe proposed approach through simulated case studies.All test cases are simulated in MATLAB/Simulink [22]using SimPower/SimElectronics library. Here, we con-sider the setup shown in Fig. 5. In order to illustratethe robustness of the proposed approach, the controldesign assumes nominal (or equivalent single converter)inductance, capacitance and steady-state complementaryduty-cycle given by L = 0.12mH, C = 500µF and D′ =Vg/Vref = 0.5, whereas the simulated system has non-identical inductances and steady-state complementaryduty-cycles. The mismatch (or uncertainty) in L and Cparameters is large (∼ 20%). The design parameters forthe inner-controller Kc are: damping factors ζ1 = 0.7,ζ2 = 2.2, and bandwidth ω = 2π300rad/s. The outercontrollers Kv and Kr are obtained by solving the stackedH∞ optimization problem (see Eq. (9)) [11] using appro-priate weighting functions.

Results: The controllers derived for the nominal singleconverter system are used to derive controller parame-ters for a parallel multi-converter system as described inSec. III-B (by setting for each converter Kvk = 1

m Kv and

Fig. 5: A parallel network comprising of a PV, a Li-ion batteryand two generic sources. It is desired to regulate the DC-link voltage to 250V. The PV module is operated using MPPTalgorithm. Its output current, iPV, is directly proportional tothe (time-varying) irradiance and is included in our proposedformulation by regarding iPV as part of the disturbance signal,with the net disturbance current modeled as iload − iPV. TheDC-link can additionally be used to power complex AC loadsvia a DC-AC inverter.

Krk = Kr for all k = 1, . . . , m). Fig. 6a and Fig. 6c showthe voltage regulation at the DC-link to the referenceVref = 250V for the centralized (iload measurementavailable) and decentralized implementations. The DC-link load changes by 4kW every second (3kW to 7kW,and 7kW to 3kW). The reference current is considered asiref = 5kW/250V = 20A. Fig. 6b and Fig. 6d present theresults for time-varying sharing.The sources are initiallyrequired to provide power in equal proportion, followedby a proportion of 5 : 2 : 3 from t = 2s onwards. Forease of illustration, the scaled output currents D′iL/γare plotted. Overlapping values of scaled currents depictexcellent sharing performance.

Fig. 6e and Fig. 6f show the results of adding complexAC loads through a DC-AC inverter. The convertersystem is required to operate in “DC-only” mode until0.4s. The three DC-sources are required to share theiroutput power in the ratio of 4 : 3 : 3. The DC-loadconsidered in this test case has a resistance of 20Ω.Subjected to these conditions, the DC-sources regulatethe DC-link voltage at 250V (see Fig. 6e), while ensuringdesired sharing performance (see Fig. 6f). At t = 0.4, theDC-load is dropped and the networked system is inter-faced with a complex AC-load (R,L) = (52.08Ω, 2mH)through a grid-tied DC-AC inverter. Despite this suddeninterconnection, the proposed control design facilitatesseamless integration to ensure that the average DC-linkvoltage is regulated at desired 250V, while ensuring thesame sharing capabilities. The transient response to gridinterconnection remains well within acceptable limits.

Comparison to conventional droop-control scheme: In orderto highlight the significance of the proposed approachfor excellence in voltage tracking and power sharing, we


Fig. 6: Simulation results representing centralized control implementation - (a) and (b); decentralized control implementation -(c) and (d); handling of complex AC loads - (e) and (f).

Fig. 7: Simulation results for droop-based control design representing centralized control implementation - (a) and (b);decentralized control implementation - (c) and (d); handling of complex AC loads - (e) and (f). Compared to the proposedimplementation, the droop-based design is sluggish and has considerably poor steady-state voltage tracking behavior in all thescenarios.

simulate the microgrid setup in Fig. 5 using conventionaldroop-based control scheme. In particular, we use theinner-outer control architecture with PI compensatorsfor both inner as well as outer loops and a droop-lawon the outer-voltage loop. The PI compensators anddroop gains are appropriately tuned to achieve desirablevoltage regulation and power sharing performance.

Fig. 7 shows the performance of droop-based designfor the the simulation setup shown in Fig. 8. While in thecentralized implementation (load current is known) inFigs. 7a and 7b the droop-based design results in similartracking and power sharing performance as indicatedin Figs. 6a and 6b where the control design proposedin this manuscript is implemented; however, results fordecentralized implementation of droop scheme in Figs.7c and 7d are quite unsatisfactory. Here, variations inoutput voltage are large due to periodic change in outputload at the DC-link where the difference between themaximum and minimum output voltages during thecourse of simulation is almost 60V. On the other hand,the control design proposed here results in excellentvoltage tracking performance even for the decentralizedimplementation (see Fig. 6c).

We further evaluate the performance of droop con-troller for scenarios that capture interfacing DC-side withcomplex AC loads (see Figs. 7e and 7f). Compared tovoltage tracking in Fig. 6e using the proposed approach,

the droop-based scheme is sluggish and result in poorsteady-state behavior. This is expected since as the pro-posed scheme incorporates the bandwidth requirementson voltage tracking through an optimization frameworkdescribed in (9), where high-bandwidth (faster response)is encoded through appropriate choice of weightingtransfer functions. Moreover, the sharing performancefor the droop-based scheme is unsatisfactory in Fig. 7fwhen compared to its counterpart in Fig. 6f. The resultsalso signify the necessity of an inner-outer control archi-tecture over a single-loop design. Through an appropri-ate choice of inner-loop controller in the proposed design(see (4)), the ripple in inductor currents are traded-offfor ripple in DC-link voltage in Fig. 6e. On the otherhand, while designing the droop-based controllers, werestrict ourselves to conventional PI controllers wheresuch trade-off are not easily handled. Thus a separateinner-outer control design allows for greater flexibilityand desirable decoupling behavior between voltage andcurrent tracking.

V. EXPERIMENTAL VALIDATION

To verify the effectiveness of the proposed approach,a test rig with three parallel operated DC sources and aparallel PV simulator PVS60085MR is built (see Fig. 8). Itis desired to regulate the DC-link voltage to Vref = 60V.


Fig. 8: Experimental setup with (1) custom-designedboost-converter boards, (2) controllers implemented onTMS320F28335 Delfino MCUs, (3) variable load - two resistors,each of value 50Ω, (4) DC-sources with maximum rated outputvoltage of 30V, (5) PV simulator subjected to simulated noisyramp profile with a peak power of 43W and controlled usingMPPT algorithm , and (6) relay for load.

System Performance: The controllers for a nominal single-converter system are designed using the multi-objectiverobust optimal control framework described in Sec.III-A and is extended to a three-converter system usingthe methodology described in Sec. III-B. The details ofweighting transfer functions and the resulting controllertransfer functions are provided in the Appendix. In orderto analyze robustness to modeling uncertainties, a 50%uncertainty in capacitance is considered. For brevity, casestudies pertaining only to more challenging decentral-ized scenario are reported; where total load current iloadis unknown and there is no communication among thecontrollers. Furthermore, PV is regarded as a currentsource and injects power directly at the DC-link, asdescribed in Sec. IV. Since, the load current is unknown,constant iref = 2A is used.

Case A: Power sharing when PV is off: Figures 9a and9c show that power from the DC sources get distributedrespectively in ratios 1 : 1 : 1 and 2 : 1 : 1, irrespectiveof the load at the DC-link; even when there are loadchanges as high as 100%. Figures 9b and 9d illustrateexcellent DC-link voltage regulation at Vref = 60V inabsence of communication between controllers aboutload. The regulation error is within 1V even when loadis changed by 100%.

Case B: Power sharing with PV on: We now evaluatethe performance of our control design under additionaluncertainty in power generation, that is, a PV source un-der simulated noisy ramp irradiance profile is connectedat the DC-link. The converter controllers to genericDC-sources are agnostic to PV output. The inclusionof PV also tests the robustness of the system to loaddisturbances since PV current can be viewed as timevarying uncertain load at the DC- link for the rest of thepower sources. Fig. 9e shows that DC sources adequatelycompensate for the PV disturbance, that is, they exhibitpower profile complementary to PV profile, even thoughthe loading conditions are not communicated to the

controllers; also DC-link voltage is well regulated (seeFig. 9f).

Case C: Resilient to unforeseen failure in power gener-ation in an agnostic setup: Robust performance of thenetworked system is now evaluated for the scenariowhen one of the generic DC sources is abruptly turnedOFF (mimicking a power source failure in a network).Furthermore, this information is not communicated tothe network. If this information were communicated, ourarchitecture in Sec III-B, will make the following changes- 1) The outer controllers Kvk = (1/m)Kv will be updatedto Kvk = Kv/(m − 1), and 2) ∑ γk will be readjustedto sum up to 1 for the active sources. However, evenwithout this communication and edits, Fig. 9g showsthat as the DC-source #2 is abruptly turned OFF, thenet power output from other DC sources auto-adjuststo loss in power generation from DC-source #2, andensures DC-link voltage regulation (Fig. 9h) and equalpower sharing (Fig. 9g). Furthermore, at t = 4.3s, loadR2 is shed, while DC-source #2 is still inactive. Despitethe generation and load uncertainties, DC-link voltage ismaintained within the viable limits and the load poweris shared equally by the active sources.

APPENDIX

A. Proof of System Equivalence

Proof: The system equivalence results directly fromchoice of the control architecture. For the single con-verter system in Fig. 3 with inner-shaped plant Gc(s) =Gc,nom(s), the mismatch e2 in the current signal (inputsignal to controller Kr) is given by

e2 = iref + (η − D′Gc,nom)e1 − D′Gc,nomKre2. (14)

For the networked system in Fig. 4, the error in the DC-link voltage regulation is given by e(k)1 = Vref − V , e1.If we denote the total mismatch in current signal by e2,

that is, e2 =m∑

k=1e(k)2 , then from Fig. 4,

m

∑k=1

e(k)2︸︷︷︸e2

=m

∑k=1

γk[iref + ηe1]− D′Gc,nom

(Kve1−Kr

m

∑k=1

e(k)2︸︷︷︸e2

). (15)

Since ∑k γk = 1, the above equation reduces to (14).Thus, the transfer function from exogenous signals tocurrent mismatch is identical for the two systems. Simi-larly, the tracking error in DC-link voltage regulation forthe two systems is given by Vref −V. Finally, the multi-converter system, the voltage at the DC-link is derived asV = Gv(−iload + D′Gc,nom(Kve1 + Kre2)), which is againidentical to (5) for single-converter system. Moreover,since the expressions for error signals e1 and e2 in termsof exogenous signals Vref, iref and iload are identical forthe two systems, the expressions for DC-link voltage Vhave identical forms for the two systems. This establishesthe required equivalence between the two systems.


Fig. 9: Experimental results demonstrating effectiveness of the proposed control design under perfectly decentralized imple-mentation for several test scenarios: 1:1:1 sharing (PV off) - (a) and (b); 2:1:1 sharing (PV off) - (c) and (d); 1:1:1 sharing (PV on)- (e) and (f); Equal sharing in presence of abrupt failure in power generation - (g) and (h). Colors blue, red, green and purpleindicate power outputs of DC sources 1, 2, 3 and PV emulator, respectively.

(a) (b)

Fig. 10: Magnitude and phase responses of (a) controller transfer functions Kv and Kr, (b) sensitivity and complementarysensitivity transfer functions.

B. Proof of Power SharingProof: Using (15), the mismatch in the current sig-

nal for kth converter is given by e(k)2 = γkS1iref +

(γkη − D′m Gc,nomKv)S1e1. From Fig. 4, the output current

ik = D′kiLk for the kth converter is given by ik =

D′Gc,nom

[1m Kve1 + Kre(k)2

]. Therefore,∣∣∣∣ ik(j0)

γk− il(j0)

γl

∣∣∣∣ ≤ (η|T1(j0)|+∣∣∣∣ 1γk− 1

γl

∣∣∣∣ |T2(j0)|)|e1(j0)|

The expressions for the bounds on the tracking error forthe two scenarios is directly obtained from (6) and thesystem equivalence described earlier.

C. Weighting Functions and Controller Parameters

The weighting transfer functions W1, W2, W3 and W4are chosen to reflect design and performance specifi-

cations. In our experiments, we have considered thefollowing weighting transfer functions:

W1 = 0.4167(s + 452.4)(s + 1.885)

, W2 = 0.4167(s + 1206)(s + 5.027)

,

W3 = 0.04, W4 = 37.037(s + 314.2)

(s + 3.142× 104).

Weight W1 is chosen to be large in the frequency range[0, 30]Hz so that the sensitivity transfer function corre-sponding to error in voltage tracking is small in that fre-quency. Note that from (5), the error in voltage trackingis given by:

e1 := Vref −V=(1− TVrefV

)︸︷︷︸SVrefV

Vref − GvTirefV (iref − iload) + GvSiload.


One of the objectives of the optimal control problem in(9) is to minimize the norm of weighted error sensitivitytransfer function W1SVrefV . Since W1 is shaped as a low-pass filter, which gives high weight at low frequen-cies and relatively low-weights at high frequencies, theoptimal solution is such that SVrefV is small at lowfrequencies. A small value of the sensitivity transferfunction SVrefV translates to a small error in voltagetracking from above equation. Similarly, W2 is chosento be large in the frequency range [0, 80]Hz so that thetransfer function from mismatch between the sourcedoutput current and the reference current to the regulationerror e1 is small. Note that the bandwidth of W2 ischosen to be larger than the bandwidth of W1, primarilyto allow for faster dynamics in the inner current loopsince change in capacitor voltage occurs at a relativelyslower timescale than a sudden change in the loadingconditions. By satisfying this condition, the referencevalue of the inner loop which is the output of the outercontroller can be considered relatively constant (see Fig.3). W3 is chosen to be constant and is designed to makethe control effort lie within the limits at all frequencies.Finally, W4 is designed as a high-pass filter to ensure thatthe transfer function from iload to V is small at high-frequencies, which mitigates effects of high-frequencymeasurement noise. The corresponding outer controllersKv and Kr are obtained by solving a multi-objective H∞-optimization problem in (9). The controller orders arethen reduced using balanced truncation [12] for efficientimplementation:

Kv = 0.69(s + 4.42e106)(s + 167)(s2 + 3930s + 1.75e107)

(s + 4891)(s + 719.2)(s2 + 7.21e104s + 2.51e109)

Kr = −0.12(s− 4.56× 105)(s + 1.12× 104)

(s + 4.64× 105)(s + 4.96)

× (s + 355.7)(s + 248.9)(s2 + 714.9s + 2.66× 105)

Fig. 10 shows the bode plots of the sensitivity andcomplementary sensitivity transfer functions describedin (6). The DC-gains for these transfer functions are:

|(GvS)(j0)| = 0.0182, |TVrefV(j0)| = 1, |TirefV(j0)| = 0.

As a consequence, we achieve the desired control ob-jectives of |TVrefV(j0)| = 1 and |(GvS)(j0)| ≈ 0. Theresulting droop-gain κ(η) is evaluated to be 0.7822.

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Mayank Baranwal Mayank Baranwal is a finalyear PhD student in the Department of Me-chanical Science and Engineering at the Uni-versity of Illinois at Urbana-Champaign (UIUC).He obtained his Bachelors in Mechanical Engi-neering in 2011 from Indian Institute of Tech-nology, Kanpur, and MS in Mechanical Scienceand Engineering in Summer 2014 and MS inMathematics in Spring 2015, both from UIUC.He works on topics related to control of powerelectronic systems and microgrids; and on anal-

ysis of metaheuristic clustering techniques with applications to somereal world problems, such as grid reduction, and pick-up and deliveryproblem with time-windows.

Alireza Askarian Alireza Askarian is a PhDstudent in the Department of Mechanical Sci-ence and Engineering at the University of Illi-nois, Urbana-Champaign. He obtained his B.Sc.degree in Mechanical Engineering from SharifUniversity of Technology in Tehran, Iran. Heis working on developing novel microgrid con-trol architecture to meet the challenges to gridsystem reliability, efficiency, and resiliency pre-sented by widespread distributed and stochasticrenewable power generation. His long-term goal

lies in adoption of key technologies developed by this research for gridsystem of future. He is a student member of the IEEE.

Srinivasa M. Salapaka Professor SrinivasaSalapaka received the B.Tech degree in me-chanical engineering from the Indian Institute ofTechnology, Chennai, in 1995 and the MS andPhD degrees in mechanical engineering fromthe University of California, Santa Barbara, in1997 and 2002, respectively. From 2002 to 2004,he was a postdoctoral associate in the Labora-tory for Information and Decision Systems, Mas-sachusetts Institute of Technology, Cambridge.Since 2004, he has been a faculty member

in the Mechanical Science and Engineering Department, Universityof Illinois, Urbana-Champaign. His areas of current research interestinclude controls for nanotechnology, combinatorial resource allocation,and numerical analysis. He received the National Science FoundationCAREER Award in 2005. He is a member of the IEEE.

Murti V. Salapaka Professor Murti Salapakaobtained his Bachelors degree in MechanicalEngineering from Indian Institute of Technol-ogy, Madras in 1991. He obtained his Mastersand PhD. degrees from University of California,Santa Barbara in the years 1993 and 1997respectively. He was at Electrical Engineeringdepartment at Iowa State University from 1997-2007. He is currently the Vincentine Hermes-Luh Chair professor in the Electrical and Com-puter Engineering Department at University of

Minnesota at Minneapolis. He is a recipient of the NSF CAREER Awardand the ISU - Young Engineering Faculty Research Award for the years1998 and 2001, respectively. He is a member of the IEEE.

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