Display IP Solution V1.3 Dec2015 shyam edits-1...Arasan Chip Systems Inc. 2010 North First Street, Suite #510, San Jose, CA 95131 Ph: 408-282-1600 Fax: 408-282-7800 Datasheet Total

ArasanChipSystemsInc.2010NorthFirstStreet,Suite#510,SanJose,CA95131Ph:408-282-1600Fax:408-282-7800www.arasan.com

Datasheet TotalMIPIDisplayIPSolution

DSIv1.3HostControllerDSIv1.3DeviceController

D-PHYv1.2PhysicalInterface

Datasheet

Copyright©2015,ArasanChipSystemsInc.

DisclaimerThisdocumentiswritteningoodfaithwiththeintenttoassistthereadersintheuseoftheproduct.CircuitdiagramsandotherinformationrelatingtoArasanChipSystems’productsareincludedasameansofillustratingtypicalapplications.Althoughtheinformationhasbeencheckedandisbelievedtobeaccurate,noresponsibilityisassumedforinaccuracies.Informationcontainedinthisdocumentissubjecttocontinuousimprovementanddevelopment.

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Datasheet


Contents

1 Introduction......................................................................................................11.1 AboutDSI.........................................................................................................................11.2 Arasan’sContributiontoMIPI.........................................................................................11.3 Arasan’sTotalIPSolution................................................................................................1

2 MIPIDSIHostIP.................................................................................................32.1 Overview..........................................................................................................................32.2 Features...........................................................................................................................32.3 Architecture.....................................................................................................................4

2.3.1 FunctionalDescription....................................................................................................42.3.2 FunctionalBlockDiagram...............................................................................................52.3.3 BlockDiagramDescription.............................................................................................5

2.4 PinDiagram.....................................................................................................................72.5 SOCLevelIntegration......................................................................................................8

2.5.1 IPDeliverables................................................................................................................82.5.2 VerificationEnvironment...............................................................................................8

3 MIPIDSIDeviceIP...........................................................................................103.1 Overview........................................................................................................................103.2 Features.........................................................................................................................103.3 Architecture...................................................................................................................11

3.3.1 FunctionalDescription..................................................................................................113.3.2 FunctionalBlockDiagram.............................................................................................123.3.3 BlockDescription..........................................................................................................12

3.4 PinDiagram...................................................................................................................143.5 SOCLevelIntegration....................................................................................................15

3.5.1 IPDeliverables..............................................................................................................153.5.2 VerificationEnvironment.............................................................................................16

4 D-PHYv1.2PhysicalInterface..........................................................................174.1 Overview........................................................................................................................174.2 Features.........................................................................................................................174.3 Architecture...................................................................................................................18

4.3.1 D-PHYBasedInterconnectArchitecture.......................................................................184.3.2 D-PHYLaneArchitecture..............................................................................................19

4.4 ArasanD-PHYArchitecture............................................................................................204.5 D-PHYPadTable............................................................................................................21

4.5.1 FunctionalDescriptionofD-PHYPadsforClockLane..................................................214.5.2 FunctionalDescriptionofD-PHYPadsforFirstDataLane............................................21

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4.5.3 FunctionalDescriptionofD-PHYPadsforSecondDataLane.......................................214.5.4 FunctionalDescriptionofD-PHYPadsforThirdDataLane..........................................214.5.5 FunctionalDescriptionofD-PHYPadsforFourthDataLane........................................224.5.6 PowerPads...................................................................................................................224.5.7 FunctionalDescriptionofTrimBits..............................................................................224.5.8 FunctionalDescriptionofClockandResetUnitInput..................................................234.5.9 FunctionalDescriptionofDataPPISignalsCommontoallDataLanes........................234.5.10 FunctionalDescriptionofClockPPI'sEscapeModeSignals.........................................234.5.11 FunctionalDescriptionofClockPPI'sControlSignals...................................................244.5.12 FunctionalDescriptionofClockPPI'sHighSpeedInterfaceSignals.............................254.5.13 FunctionalDescriptionofDataPPI’sEscapeModeSignals..........................................264.5.14 FunctionalDescriptionofDataPPI’sControlSignals....................................................274.5.15 FunctionalDescriptionofSideBandSignals.................................................................284.5.16 FunctionalDescriptionofDFTSignals..........................................................................284.5.17 D-PHYUIParameterCountSignals...............................................................................294.5.18 A-BISTRelatedSignals..................................................................................................29

4.6 HardMacroDeliverables...............................................................................................30

5 Services&Support..........................................................................................315.1 GlobalSupport...............................................................................................................315.2 ArasanSupportTeam....................................................................................................315.3 ProfessionalServices&Customization..........................................................................315.4 TheArasanPortingEngine............................................................................................315.5 Pricing&Licensing.........................................................................................................31

Tables Table1:FunctionalDescriptionofD-PHYPadsforClockLanes..........................................................21Table2:FunctionalDescriptionofD-PHYPadsforFirstDataLane.....................................................21Table3:FunctionalDescriptionofD-PHYPadsforSecondDataLane................................................21Table4:FunctionalDescriptionofD-PHYPadsforThirdDataLane...................................................21Table5:FunctionalDescriptionofD-PHYPadsforFourthDataLane.................................................22Table6:PowerPads............................................................................................................................22Table7:PortsforTrim_Bits.................................................................................................................22Table8:FunctionalDescriptionofClockandResetunitInputsignalsforclockanddataPPI............23Table9:FunctionalDescriptionofdataPPIsignalsthatarecommontoallDataLanes....................23Table10:FunctionalDescriptionofClockPPI’sHighSpeedInterfaceSignals...................................23Table11:FunctionalDescriptionofClockPPI’sControlSignals..........................................................24Table12:FunctionalDescriptionofDataPPI'sHighSpeedInterfacesignals......................................25Table13:FunctionalDescriptionofDataPPI'sEscapemodeSignals.................................................26Table14:FunctionalDescriptionofDataPPI’sControlSignals...........................................................27

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Table15:FunctionalDescriptionofSideBandSignals........................................................................28Table16:FunctionalDescriptionofDFTSignals.................................................................................28Table17:D-PHYUIParameterCountSignals......................................................................................29Table18:A-BISTPins...........................................................................................................................29

Figures Figure1:Arasan'sTotalIPSolution.......................................................................................................2Figure2:DSIHostPinout.......................................................................................................................7Figure3:DSIHostPinoutContinued.....................................................................................................8Figure4:VerificationEnvironmentofDSIHostIP.................................................................................9Figure5:DSIDevice(Rx)FunctionalBlockDiagram............................................................................12Figure6:DSIDevice(Rx)Pinout..........................................................................................................14Figure7:DSIDevice(Rx)PinoutContinued........................................................................................15Figure8:VerificationEnvironmentofDSIDeviceIP...........................................................................16Figure9:MIPILinkDiagramforFourDataLanes................................................................................18Figure10:D-PHYLaneArchitecture....................................................................................................19Figure11:AnalogandDigitalD-PHYBlockDiagram...........................................................................20

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Copyright©2015,ArasanChipSystemsInc. 1

1 Introduction1.1 AboutDSITheMIPI®AlliancetheDisplaySerialInterface(DSI)datesbackto2005.TheDisplaySerialInterfacespecificationdefinesprotocolsbetweenahostprocessorandperipheraldevicesusingaD-PHYphysicalinterface.TheDSIspecificationbuildsonexistingspecificationsbyadoptingpixelformatsandcommandsetdefinedinMIPIAllianceSpecificationsforDisplayPixelInterface2(DPI-2)andDisplayCommandSet(DCS).

Fromasystemorsoftwarepointofview,serializationanddeserializationoperationsshouldbetransparent.Themostvisible,andunavoidableconsequenceoftransformationtoserialdataandbacktoparallelisincreasedlatencyfortransactionsthatrequirearesponsefromtheperipheral.Forexample,readingapixelfromtheframebufferonadisplaymodulehasahigherlatencyusingDSIthanDBI.Anotherfundamentaldifferenceisthehostprocessor’sinabilityduringareadtransactiontothrottletherateorsizeofreturneddata.

1.2 Arasan’sContributiontoMIPIArasanhasbeenamemberofMIPIforovertenyears.Weareactiveparticipantsinanumberofworkinggroups.WeworkcloselywithothermembercustomerstoensurecompliantimplementationofstandardsbasedIP.

1.3 Arasan’sTotalIPSolutionArasanprovidesaTotalIPSolution,whichencompassesallaspectsofIPdevelopmentandintegration,includinganaloganddigitalIPcores,verificationIP,softwarestacks&drivers,andhardwarevalidationplatforms.BenefitsofTotalIPSolution:

• SeamlessintegrationfromPHYtoSoftware• Assuredcomplianceacrossallcomponents• Singlepointofsupport• Easiestacquisitionprocess(onelicensingsource)• Lowestoverallcostincludingcostofintegration• Lowestriskforfasttimetomarket

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Figure1:Arasan'sTotalIPSolution

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2 MIPIDSIHostIP2.1 OverviewArasanChipSystemsisaleadingSOCIPproviderofacompletesuiteofMIPIcompliantIPsolutions,whichconsistofIPcores,verificationIP,softwarestacksanddrivers,protocolanalyzers,hardwareplatformsforsoftwaredevelopmentandcompliancetesting,andoptionalcustomizationservices.TheMIPIcompliantIPcoresareinterfacebuildingblocksthatsimplifyinterconnectarchitecturesinmobileplatforms.Thisleadstosmallerfootprint,greaterinteroperabilitybetweenmobileIP,chipsanddevicesfromdiversesources,andlowerpowerandEMI.

ThisdocumentdescribestheArasanIPCorethatfunctionsasaMIPIDSIHostController,whichtypicallyresidesinamobileplatform’sapplicationprocessor,andcommunicatesoveraD-PHYseriallinktoaDSIDeviceinthedisplaypanel.

2.2 Features• CompliantwiththefollowingMIPIspecifications:

§ DisplaySerialInterface(DSI)version1.3§ DisplayPixelInterface(DPI-2)version2.00§ DisplayBusInterface(DBI)version2.00§ DisplayCommandSet(DCS)version1.02§ D-PHYversion1.2

NewFeaturesaddedinV1.2

§ Supportforcompressedimagepixeldataformat § PPS-pictureparameterset-packetfortransmittingcompressionparameters


§ Hi-Speedtransmitsupportupto2.5Gbpsperlane § Deskewsupport-initialandperiodic

• DSIHost-side(displaymodule)interfacesupports:§ ConnectivitytoD-PHYthroughPPIInterface§ 1to4datalane§ Hi-Speed(HS)transmitfrom80Mbpsto1.5Gbps2.5Gbpsperlane§ LowPower(LP)receive/transmitfrom/todeviceat10Mbps§ Continuousandstoppableclocksonclocklane§ Busturnaroundwithcontentionandfaultrecovery§ SwitchingtoandfromLowPower(LP)andUltra-lowPower(ULPS)modes§ EOTenable/disablemechanisms§ Multiplepacketspertransmissionwithinterleaveddatastream§ ProgrammableerrorinjectioninVerificationIPanderrordetectionindesignIP

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§ FlexibilityinsettingpolarityforDPIInterfacesignals

• ApplicationProcessorConnectivityandVideoCommandProcessing§ DPIorDBI,dependingonpanelordisplayunitarchitecture§ Genericcommandsupport

§ Genericparallelinterfaceforsendingandreceivingvendor-specificinformationtoandfromthedisplaydriverlogicinthedisplaymodule

§ Supportforallgenericread/writesoverDBI/Genericinterface

• VideoModesupports:§ Widerangeofdisplayresolutionandpixelformats§ Displayresolutions:QQVGA,QCIF,QVGA,CIF,VGA,WVGA,XGA,1080p,QXGA,QSXGA§ Burstmodeandnon-bursttransfersoverDPIinterface

• DBIsupports:§ 8/9/16-bitdatatransferinDBITypeBinterface§ AllDCScommands

• AHB/APBInterfaceforregisterconfigurationandmonitoringusingprogrammedIO

2.3 Architecture2.3.1 FunctionalDescriptionTheArasanDSIHostControllerIPisdesignedtoprovideMIPIDSI1.3complianthighspeedserialconnectivityformobileapplicationprocessorsusing1to4D-PHYsdependingonbandwidthneeds.Serialconnectivitytothedisplaymodule’sDSIdeviceisimplementedusing1to4D-PHY’s(alsoavailablefromArasan),dependingondisplaybandwidthneeds.ThisIPconnectstotheD-PHY’sthroughthePPIinterface.

Ontheapplicationprocessorside,Arasan’sDSIHostControllerprovidesthechoiceofDPIorDBIInterfacetoagraphicscontroller.ADBIinterfaceprovidesdownstreamsupportofTypes1to3displaymodules,andtheDPIInterfaceisneededforTypes2to4displays.

InitialconfigurationofthisIPcanbedonethroughprogrammedIOovertheAHBbus,however,otherbusinterfacescanbeprovideduponrequest.

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2.3.2 FunctionalBlockDiagram

Figure1:DSIDevice(Tx)FunctionalBlockDiagram

2.3.3 BlockDiagramDescription

2.3.3.1 LaneManager

ThisblockcommunicatesthroughaPPIinterfacewithonetofourD-PHYdatalanes,dependingonthebandwidthneedsofanapplication.TheLaneManagerblockdrivesthedifferentstatesintheD-PHY’slikeULPS(Ultra-LowPowerState),HS(HighSpeed)andLP(LowPower).ItreceivesthedatafromthePacketizermoduleanddistributesacrosstheD-PHYdatalanesbasedontheprogrammedlanecount.

Ithastimerslikehighspeedtransmittimeout,lowspeedreceptiontimers,andturnaroundtimeoutcounterstorecoveritselffromfaultmodeconditions,anddeviceresettimersforrecoveryfromcontentions.

InLPmode,thisblockisresponsibleforsendingandreceivingthetriggermessages,andreceivingthegeneric/DCSreadresponsedatainshortorlongpacketformats.ForincomingLPmodepackets,thisblockmanagesECCandCRCchecking.

2.3.3.2 Channelizer

TheChannelizerutilizestheBlankingandLowPower(BLLP)intervalduringDPItransmitstointerleaveDBI/Generictransfersduringthosetimes.ThisresultsinextremelyefficientDSIbandwidthutilization.

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2.3.3.3 Packetizer

DependingonthepacketinformationregisteredinthecontrolFIFOintheDBI/GenericBusInterface,shortpacketsorheadersoflongpacketsaregeneratedandtransmittedbythePacketizer.Forlongpackets,datafromtheDataFIFOisappended,thebytelengthofwhichisreferencedinthecontrolFIFO.

DependingonthesignallingintheDPIInterfaceandtheparametersprogrammedinitsregisters,eithershortorlongpacketsaregeneratedandtransmitted.ECCisgeneratedandaddedforshortpacketsandheadersoflongpackets.Forlongpackets,pixelsthataregatheredinaDPIDataFIFOareappendedaspayloadsoflongpackets,alongwithaCRCvaluecalculatedbythePacketizer.

2.3.3.4 DPIFIFOandPixelInterface

Apixel-to-byteconverterinthePixelInterfaceconvertstheincoming16,18or24-bitpixeldatatobyteformatandstoresitinDPIFIFO,andnotifiesthePacketizer.A2048x32-bitDPRAMisusedforlinebuffering.

2.3.3.5 DBI/GenericFIFOandBusInterface

TheseblocksparsesandclassifytheincomingDCS/genericcommandsasreadandwritecommandsundervariouscategories.ThereadcommandsarepassedontotheperipheralsandreadresponsesaresentbacktotheDBIinterface.CommandsthatinvolveahugedatawritedatatransferareconvertedintoDCS/genericlongwritecommandsandsentbythePacketizertotheLaneManageraspackets.

2.3.3.6 AHBSlaveInterface

ThisblockallowsaprocessortoconfiguretheIPthroughprogrammedIO,andprovidesfortheIPtoprovidestatusinformationtotheprocessorusinginterrupts.

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2.4 PinDiagram

Figure2:DSIHostPinout

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Figure3:DSIHostPinoutContinued

2.5 SOCLevelIntegration2.5.1 IPDeliverables• VerilogHDLoftheIPCore• Userguide• Gatecountestimatesavailableuponrequest• Synthesisscripts

2.5.2 VerificationEnvironment• ComprehensivesuiteofsimulationtestsforeaseofSOCintegration• Verificationcomponentsandtestfilesprovided• Verificationenvironmentandtestsuitewelldocumented

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Figure4:VerificationEnvironmentofDSIHostIP

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3 MIPIDSIDeviceIP3.1 OverviewArasanChipSystemsisaleadingSOCIPproviderofacompletesuiteofMIPIcompliantIPsolutions,whichconsistofIPcores,verificationIP,softwarestacksanddrivers,protocolanalyzers,hardwareplatformsforsoftwaredevelopmentandcompliancetesting,andoptionalcustomizationservices.TheMIPIcompliantIPcoresareinterfacebuildingblocksthatsimplifyinterconnectarchitecturesinmobileplatforms.Thisleadstosmallerfootprint,greaterinteroperabilitybetweenmobileIP,chipsanddevicesfromdiversesources,andlowerpowerandEMI.

ThisdocumentdescribestheArasanIPCorethatfunctionsasaMIPIDSIDeviceController,whichtypicallyresidesinamobileplatform’sdisplaypanel,andcommunicatesoveraD-PHYseriallinktoaDSIHostintheapplicationsprocessor.

3.2 Features• CompliantwiththefollowingMIPIspecifications

§ DisplaySerialInterface(DSI)version1.3§ DisplayPixelInterface(DPI-2)version2.00§ DisplayBusInterface(DBI)version2.00§ DisplayCommandSet(DCS)version1.02§ D-PHYversion1.2


§ Supportforcompressedimagepixeldataformat § PPS-pictureparameterset-packetfortransmittingcompressionparameters


§ Hi-speedreceivefrom80Mbpsto2.5Gbpsperlane § Deskewsupport-initialandperiodic

• DSIDevice-sideinterfacesupports:

§ ConnectivitytoD-PHYthroughPPIInterface§ 1to4datalane§ Hi-Speed(HS)receivefrom80Mbpsto2.5Gbpsperlane§ LowPower(LP)receive/transmitfrom/tohostat10Mbps§ Continuousandstoppableclocksonclocklane§ Busturnaroundwithcontentionandfaultrecovery§ SwitchingtoandfromLowPower(LP)andUltra-lowPower(ULPS)modes§ EOT,ECC,andCRCenable/disablemechanisms§ Multiplepacketspertransmissionwithinterleaveddatastream

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§ Acknowledgepacketsandtriggermessages§ ProgrammableerrorinjectioninVerificationIPanderrordetectionindesignIP

• DisplayPanelConnectivityandvideo/commandprocessingsupports:

§ DPIorDBI,dependingonpanelordisplayunitarchitecture§ Genericcommand§ Genericparallelinterfaceforsendingandreceivingvendor-specificinformationtoandfrom

thedisplaydriverlogicinthedisplaymodule§ Allgenericread/writesoverDBI/Genericinterface

• VideoModesupports:

§ Widerangeofdisplayresolutionandpixelformats§ Displayresolutions:QQVGA,QCIF,QVGA,CIF,VGA,WVGA,XGA,1080p,QXGA,QSXGA§ Burstmodeandnon-bursttransfersoverDPIinterface

• DBIsupports:§ 8/9/16-bitdatatransferinDBITypeBinterface§ AllDCScommands

• AHBInterfaceforregisterconfigurationandmonitoringusingprogrammedIO

3.3 Architecture3.3.1 FunctionalDescriptionTheArasanDSIDeviceControllerIPisdesignedtoprovideMIPIDSI1.3complianthighspeedserialconnectivityformobiledisplaymoduleswithType1to4architectures.Serialconnectivitytothemobileapplicationsprocessor’sDSIhostisimplementedusing1to4D-PHY’s(alsoavailablefromArasan),dependingondisplaybandwidthneeds.ThisIPconnectstotheD-PHY’sthroughthePPIinterface.

Displaymodulesconsistofdisplaydriverlogicdrivingdisplaysignalsontoadisplaydeviceorpanel.Onthedisplaydriverside,Arasan’sDSIDeviceControllerprovidestheDBIInterfaceforTypes1to3displaymodulesandtheDPIInterfaceforTypes2to4displays.

InitialconfigurationofthisIPcanbedonethroughprogrammedIOovertheAHBbus,however,otherbusinterfacescanbeprovideduponrequest.

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3.3.2 FunctionalBlockDiagram

Figure5:DSIDevice(Rx)FunctionalBlockDiagram

3.3.3 BlockDescription

3.3.3.1 LaneManager

ThisblockcommunicatesthroughaPPIinterfacewithonetofourD-PHYdatalanes,dependingonthebandwidthneedsofanapplication.TheLaneManagerblockdetectsthedifferentstatesoftheD-PHY’slikeULPS(Ultra-LowPowerState),HS(HighSpeed)andLP(LowPower).ItcollectsincomingbytesofdatafromtheD-PHYlanesateveryclockedgebasedonprogrammedlanecountandforwardsthemtotheDepacketizermodule.Itisalsoresponsibleforcontentionanderrordetectionandresponseforallincomingpackets.

InLPmode,thisblockisresponsibleforsendingtriggermessages,acknowledgmentpacketsandgeneric/DCSreadresponsedatainshortorlongpacketformats.ForoutgoingLPmodepackets,thisblockmanagesECCandCRCgeneration.

3.3.3.2 Depacketizer

FromtheDSIdatatypeintheDataIdentifieroftheincomingpacket,theDepacketizerdetermineswhethertheincomingpacketisshortorlong.Fromtheincominglongpackets,theDepacketizerseparatesouttheheader,footerandpayloadandforwardseachofthemtotheappropriateprotocollayerblocks.ThechecksumvalueforlongpacketpayloadsiscalculatedandcomparedwithreceivedCRCandenteredintheregistersetforfurtherprocessing.Shortpacketsandheadersforlongpacketsarecorrectedfor1-biterrors.

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3.3.3.3 DPIFIFOandPixelInterface

Thispathisselectedinvideomodeandisunidirectional.DisplaysynceventtiminginformationoriginatesasshortpacketsfromtheDSIhost.Uponreceivingthem,thePixelInterfaceconvertsthosetodisplay-relatedcontrolsignals,suchashorizontalandverticalsyncandblankingintervals.PayloadbytesextractedbytheDepacketizerfromlongpacketsreceivedinHSmodefromtheDSIhostaresentthroughtheDPIFIFOtothePixelInterfaceblock,whichconvertsthemtopixelsandsendstothedisplaypanelthroughtheDPIbus.

3.3.3.4 DBI/GenericFIFOandBusInterface

Thispathisselectedincommandmodeandisbidirectional.LongpacketsandshortpacketsreceivedfromtheDepacketizercontainthecommandsfortheoff-chipdisplaymodulethatimplementstheDisplayCommandSet.ForDCSorGenericReadcommands,thenumberofdatabytescollectedforDBIreadoperationsisbasedonthemaximumreturnpacketsizesettings,andforwardedtotheLaneManagertoencapsulatewithinapacketstructure,asdescribedabove.

3.3.3.5 AHBSlaveInterface

ThisblockallowsaprocessortoconfiguretheIPthroughprogrammedIO,andprovidesfortheIPtoprovidestatusinformationtotheprocessorusinginterrupts.

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3.4 PinDiagram

Figure6:DSIDevice(Rx)Pinout

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Figure7:DSIDevice(Rx)PinoutContinued

3.5 SOCLevelIntegration3.5.1 IPDeliverables• VerilogHDLoftheIPCore• Userguide• Gatecountestimatesavailableuponrequest• Synthesisscripts

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3.5.2 VerificationEnvironment• ComprehensivesuiteofsimulationtestsforeaseofSoCintegration• Verificationcomponentsandtestfilesprovided• Verificationenvironmentandtestsuitewelldocumented

Figure8:VerificationEnvironmentofDSIDeviceIP

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4 D-PHYv1.2PhysicalInterface4.1 OverviewToaddresstheexplosivegrowthinthemobileindustry,theMobileIndustryProcessorInterface(MIPI®)Alliancewascreatedtodefineandpromoteopenstandardsforinterfacestomobileapplicationprocessors.D-PHYisthephysicallayerspecifiedforseveralofthekeyprotocolswithintheMIPI®familyofspecifications.

TheArasanD-PHYIPcoreisfullycomplianttotheD-PHYspecificationversion1.2.ItsupportstheMIPI®CameraSerialInterface(CSI-2)andDisplaySerialInterface(DSI)protocols.ItisauniversalPHYthatcanbeconfiguredasatransmitter,receiverortransceiver.TheD-PHYconsistsofananalogfrontendtogenerateandreceivetheelectricallevelsignals,andadigitalbackendtocontroltheI/Ofunctions.

TheArasanD-PHYprovidesapointtopointconnectionbetweenmasterandslaveorhostanddevicethatcomplywitharelevantMIPI®standard.Atypicalconfigurationconsistsofaclocklaneand1-4datalanes.Themaster/hostisprimarilythesourceofdataandtheslave/deviceisusuallythesinkofdata.TheD-PHYlanescanbeconfiguredforunidirectionalorbidirectionallaneoperation,originatingatthemasterandterminatingattheslave.Itcanbeconfiguredtooperateasamasterorasaslave.TheD-PHYlinksupportsahighspeed(HS)modeforfastdatatrafficandalowpower(LP)modeforcontroltransactions.InHSmode,thelowswingdifferentialsignalisabletosupportdatatransfersfrom80Mbpsto2.5Gbps.InLPmodeallwiresoperateasasingleendedlinecapableofsupporting10Mbpsasynchronousdatacommunications.

TheArasanD-PHYIPcoreimplementsthePPIinterfacerecommendedbytheMIPI®workinggroupstoeasilyinterfacetotherequiredprotocols.

4.2 Features • ComplianttoMIPIAllianceStandardforD-PHYspecificationVersion1.2.Supports:• Synchronoustransferathighspeedmodewithabitrateof80-1500Mb/s• Asynchronoustransferatlowpowermodewithabitrateof10Mb/s• SpacedonehotencodingforLowPower[LP]data• Onebytebufferhousedinsidethecoreforbothdata-outanddata-inpaths.• Oneclocklaneanduptofourdatalanes• Errordetectionmechanismforsequenceerrorsandcontentions• Transferofdatainhighspeedmode• Ultralowpowermode,highspeedmodeandescapemode.• Contentiondetectionandturnarounds• Clockdividerunittogenerateclockforparalleldatareceptionandtransmissionfromandtothe

PPIunit.

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• Activationanddisconnectionofhighspeedterminatorsforreceptionandtransmission.• StandardPHYtransceivercomplianttoMIPISpecification• StandardPPIinterfacecomplianttoMIPISpecification.• Clocklaneunidirectionalcommunication• On-chipclockgenerationconfigurableforeithertransmitterorareceiver• TestabilityforTx,RxandPLL• ConfigurabilityofPHYasamasterorslave• Corestructuredtoincreasethenumberofdatalanes• HighspeedmodeinForwardcommunication

4.3 Architecture4.3.1 D-PHYBasedInterconnectArchitecturePhysicalconnectivitybetweenamasterandslavecomponentrequiresaclocklaneand,dependingonbandwidthneeds,onetofourdatalanes.Tosupportthis,aD-PHYhasaClockLaneModule,andonetofourDataLaneModules.EachoftheseD-PHYLaneModulescommunicatesviaadifferentialsignalpairtoacomplementarypartontheothersideoftheLaneInterconnect.

Figure9:MIPILinkDiagramforFourDataLanes

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4.3.2 D-PHYLaneArchitecture

Figure10:D-PHYLaneArchitecture

4.3.2.1 Lane

EachLaneModulehasacontrolandinterfacelogicunitandatransceiverportiontohandledifferentialHigh-Speedfunctionsutilizingbothinterconnectwiressimultaneously,single-endedLow-Powerfunctionsoperatingoneachoftheinterconnectwiresindividuallyandalowpowercontentiondetector.TheI/OfunctionsarecontrolledbyaLaneControlandInterfaceLogicblock.

4.3.2.2 Signaling

High-Speedsignalshavealowvoltageswingof200mV,whileLow-Powersignalshavealargeswingof1.2V.High-SpeedfunctionsareusedforHigh-SpeedDatatraffic.TheLow-Powerfunctionsaremainlyusedforcontrolandcanhavedatatransfersupport.

4.3.2.3 Link

EachlinkhasaMasterandaSlaveside.TheMasterprovidestheHigh-SpeedDDRClocksignaltoClockLaneandisthemaindatasource.TheSlavereceivestheclocksignalattheClockLaneandisthemaindatasink.ThismaindirectionofcommunicationisdenotedastheForwarddirection.CommunicationintheoppositedirectioniscalledReversetraffic.Onlybi-directionalDataLanessupportbothforwardandreversecommunications.

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4.3.2.4 LaneControlandInterfaceLogic

Itsendsanddetectsstartofpacketsignallingandendofpacketsignallingonthedatalanes.Ithasaserializerandde-serializerunittodialogwiththePPI/PHYadapterunit.AlsoithasclockdividerunittosourceandreceivedataduringparalleldatatransfersfromandtothePPI.

4.4 ArasanD-PHYArchitectureThetransceiverpinsoftheArasanD-PHYarecomplianttoMIPI'stransceivers.ThelanecontrolandinterfacelogicunitoperateswiththeclockprovidedbyPPIunitduringhighspeedaswellasinlowpowermodesofoperationinmastermodewhereas,aseparatelowpowerclockisusedinslavemodeforlowpoweroperationsandthereceivedhighspeedclockisusedforhighspeeddatatransfers.

InArasanD-PHYdigitalIP,bothMasterandslavemodeshavestatemachinestogeneratesequencesforswitchingtohighspeed,controlmodeandultralowpowermodes.Theyhavedeserializer/serializerunittoconvertparalleltoserialdataandvice-versa.

Slavedevicehassequenceobserverstatemachinestoknowthemodesofoperationofthelanes.Theyhavesequenceerrordetectorsalso.

Figure11:AnalogandDigitalD-PHYBlockDiagram

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4.5 D-PHYPadTable4.5.1 FunctionalDescriptionofD-PHYPadsforClockLane

Table1:FunctionalDescriptionofD-PHYPadsforClockLanes

Pin Direction Description

dpck Bidirectional Positivepolarityoflowvoltagedifferentialclocksignalfortransmitterandreceiver

dnck Bidirectional Negativepolarityoflowvoltagedifferentialclocksignalfortransmitterandreceiver

4.5.2 FunctionalDescriptionofD-PHYPadsforFirstDataLaneTable2:FunctionalDescriptionofD-PHYPadsforFirstDataLane


dp0 Bidirectional Positivepolarityoflowvoltagedifferentialdatasignalfortransmitterandreceiver

dn0 Bidirectional Negativepolarityoflowvoltagedifferentialdatasignalfortransmitterandreceiver

4.5.3 FunctionalDescriptionofD-PHYPadsforSecondDataLaneTable3:FunctionalDescriptionofD-PHYPadsforSecondDataLane




4.5.4 FunctionalDescriptionofD-PHYPadsforThirdDataLaneTable4:FunctionalDescriptionofD-PHYPadsforThirdDataLane




Datasheet


4.5.5 FunctionalDescriptionofD-PHYPadsforFourthDataLaneTable5:FunctionalDescriptionofD-PHYPadsforFourthDataLane




4.5.6 PowerPadsTable6:PowerPads

Pin Type Direction DescriptionVDD_clk Power InOut PowerpadforClocklane

VSS_clk Power InOut GroundpadforClocklaneVDD_d0d1 Power InOut PowerpadforDatalane0and

Datalane1VSS_d0d1 Power InOut GroundpadforDatalane0and

Datalane1VDD_d2d3

PowerInOut PowerpadforDatalane2and

Datalane3

VSS_d2d3Power

InOut GroundpadforDatalane2andDatalane3

VDDD Power InOut PowerpadforDFEVSSD Power InOut GroundpadforDFEVDDLP12 Power InOut PowerpadforLowpowerblocks

4.5.7 FunctionalDescriptionofTrimBitsTable7:PortsforTrim_Bits


trim_0[31:0] Input TrimbitsforDPHYtrim_1[31:0] Input TrimbitsforDPHYtrim_2[31:0] Input TrimbitsforDPHYtrim_3[31:0] Input TrimbitsforDPHY

Datasheet


4.5.8 FunctionalDescriptionofClockandResetUnitInputTable8:FunctionalDescriptionofClockandResetunitInputsignalsforclockanddataPPI


TxClkEsc Input EscapemodeTransmitClock.Thisclockisdirectlyusedtogenerateescapesequences.Theperiodofthisclockdeterminesthesymboltimeforlowpowersignals.ThisisalsotheinputreferenceclockforthePLL

enable[Reset] Input ActiveLowsystemresettothemodule.

4.5.9 FunctionalDescriptionofDataPPISignalsCommontoallDataLanes

Table 9: Funct ional Descr ipt ionof dataPPI s ignals that are commontoa l l DataLanes


dln_bd_ForceRxmode

Input ForceLaneModuleIntoReceivemode/WaitforStopstate.ThissignalforcesthestatemachineintoRXmode.

dln_ForceTxStopmode[3:0]

Input ForceLaneModuleIntoTransmitmode/GenerateStopstate.ThissignalforcesSTOPsignalonthetransmitlines.

4.5.10 FunctionalDescriptionofClockPPI'sEscapeModeSignalsTable10:FunctionalDescriptionofClockPPI’sHighSpeedInterfaceSignals


cln_TxRequestHS Input High-SpeedTransmitRequestandDataValidforclocklane.ForclockLanes,thisactivehighsignalcausesthelanemoduletobegintransmittingahigh-speedclock.

cln_RxActiveHS Output ReceiverClockActive.Thisasynchronous,activehighsignalindicatesthataclockLaneisreceivingaDDRclocksignal

TxByteClkHS Output High-SpeedTransmitByteClock.ThisisusedtosynchronizePPIsignalsintheHigh-Speedtransmitclockdomain.ItisrecommendedthatalltransmittingDataLaneModulesshareonetransmitter’sbyteclocksignal.Thefrequencyofbyteclockisexactly1/8theHigh-SpeedbitrateThisisthetxbyteclkhstowhichallPPIinterfaceissynchronousfortransmitter.

Datasheet


RxByteClkHS Output High-SpeedReceiveByteClock.ThisisusedtosynchronizesignalsintheHigh-Speedreceiveclockdomain.TherxbyteclkhsisgeneratedbydividingthereceivedHigh-SpeedDDRclockThisisthebyteclocktowhichallPPIinterfaceissynchronousforreceiver.

RxDDRClkHS_0 Output HighspeedDDRclockusedbythereceiver.cln_TxUlpsExit Input TransmitULPExitSequenceforclocklane.This

activehighsignalisassertedwhenULPstateisactiveandtheprotocolisreadytoleaveULPstate.ThePHYleavesULPstateandbeginsdrivingMark-1whentx_ulpsactivenot_clk_nbecomesdeasserted.txulpsexit_clkissynchronoustotxclkesc.ThissignalisignoredwhentheLaneisnotintheULPState

cln_TxUlpsClk Input ToforcetheclocklanetotransmitULPSsequencesintheclockline.

cln_RxUlpsClkNot Output ReceiveUltraLow-PowermodeonClockLane.ThisactivelowsignalisassertedtoindicatethattheClockLanemodulehasenteredtheUltraLow-Powermode.TheLanemoduleremainsinthismodewithRxUlpsClkNotasserteduntilaStopstateisdetectedontheLaneInterconnect

cln_tx_UlpsActiveNot

Output ULPState(not)Activeforclocklane.ThisactivelowsignalisassertedtoindicatethattheLaneisinULPstate.

cln_rx_UlpsActiveNot

Output ULPState(not)Activeforclocklane.ThisactivelowsignalisassertedtoindicatethattheLaneisinULPstate

4.5.11 FunctionalDescriptionofClockPPI'sControlSignalsTable11:FunctionalDescriptionofClockPPI’sControlSignals


cln_Rxstopstate Output LaneisinStopstateforclocklane.ThisactivehighsignalindicatesthatthelanemoduleiscurrentlyinStopstate.Thisisvalidforbothreceiversandtransmitters.NotethatthissignalisasynchronoustoanyclockinthePPIinterface

Datasheet


4.5.12 FunctionalDescriptionofClockPPI'sHighSpeedInterfaceSignals

Table12:FunctionalDescriptionofDataPPI'sHighSpeedInterfacesignals


dln_TxDataHS[31:0] Input High-SpeedTransmitDatafordatalane.High-speeddatatobetransmitted.Dataiscapturedonrisingedgesoftransmittedbyteclock.

dln_TxRequestHS[3:0]

Input High-SpeedTransmitRequestandDataValidfordatalane.Alow-to-hightransitionontxrequesthscausesthelanemoduletoinitiateaStart-of-Transmissionsequence.Ahigh-to-lowtransitionontxrequesthscausesthelanemoduletoinitiateanEnd-of-Transmissionsequence.ForDataLanes,thisactivehighsignalalsoindicatesthattheprotocolisdrivingvaliddataontxdatahs_0tobetransmitted.Thelanemoduleacceptsthedatawhenbothtxrequesthsandtxreadyhsareactiveonthesamerisingtxbyteclkhsclockedge.Theprotocolalwaysprovidesvalidtransmitdatawhentxdatahs_0isactive.Onceasserted,txdatahsremainshighuntilthedatahasbeenaccepted,asindicatedbytxreadyhs.txdatahsisonlyassertedwhiletxrequestesc_0islow

dln_TxReadyHS[3:0]

Output High-SpeedTransmitReadyfordatalane.Thisactivehighsignalindicatesthattxdatahs_0isacceptedbythelanemoduletobeseriallytransmitted.txreadyhs_0isvalidonrisingedgesoftransmittedbyteclock.

dln_RxDataHS[31:0] Output High-SpeedReceiveDatafordatalane.Thesignalconnectedtorxdatahs_0wasreceivedfirst.Dataistransferredonrisingedgesofreceiverbyteclock.

dln_RxValidHS[3:0] Output High-SpeedReceiveDataValidfordatalane.dln_RxActiveHS[3:0]

Output High-SpeedReceptionActivefordatalane.Thisactivehighsignalindicatesthatthelanemoduleisactivelyreceivingahigh-speedtransmissionfromthelaneinterconnect.

dln_RxSyncHS[3:0] Output ReceiverSynchronizationObservedfordatalane.ThisactivehighsignalindicatesthattheLanemodulehasseenanappropriatesynchronizationevent.Inatypicalhigh-speedtransmission,rxsynchs_0ishighforonecycleofreceivedbyteclockatthebeginningofahigh-speedtransmissionwhenrxactivehs_0isfirstasserted,andagainforonecycleofreceivedbyteclockattheendofahigh-speedtransmission,justbeforerxvalidhs_0returnslow.

Datasheet


4.5.13 FunctionalDescriptionofDataPPI’sEscapeModeSignalsTable13:FunctionalDescriptionofDataPPI'sEscapemodeSignals

Pin Direction Descriptiondln_TxRequestEsc[3:0]

Input EscapemodeTransmitRequestfordatalane.txrequestesc_0isonlyassertedbytheprotocolwhiletxrequesths_0islow.

dln_TxUlpsExit[3:0] Input TransmitULPExitSequencefordatalane0.ThisactivehighsignalisassertedwhenULPstateisactiveandtheprotocolisreadytoleaveULPstate.ThePHYleavesULPstateandbeginsdrivingMark-1whenulpsactivenot_0_nbecomesdeasserted.txulpsexit_0issynchronoustotxclkesc.ThissignalisignoredwhentheLaneisnotintheULPState.

dln_TxUlpsEsc[3:0] Input EscapemodeTransmitUltraLowPowerfordatalane0.Thisactivehighsignalisassertedwithtxrequestesctocausethelanemoduletoentertheultra-lowpowermode.Thelanemoduleremainsinthismodeuntiltxrequestesc_0isdeasserted.txlpdtesc_0andallbitsoftxtriggerescarelowwhentxulpsesc_0isasserted.

dln_bd_TxLpdtEsc Input Thissignalisusedtorequestalowpowerdatatransmissionentryinthereversedirection.

dln_bd_TxTriggerEsc[3:0]

Input A4bitsignalthattriggersatriggersequenceintheESCmodeinthereversedirection.

dln_bd_TxDataEsc[7:0]

Input Indatamode,the8-bitdatatobetransmittedinthereversedirection.

dln_bd_TxValidEsc Input Avalidsignalwhichqualifiesforthedatalines.

dln_bd_TurnDisable Input Toavoidtheturn-aroundrequestduringthelockupsituation.

dln_bd_Direction OutPut Toindicatethedirectionofthedatalane.Thissignalisusedtoindicatethecurrentdirectionofthelaneinterconnect.Whendirection_0=0,thelaneisintransmitmode(0=Output).Whendirection_0=1,thelaneisinreceivemode(1=Input).

dln_bd_TurnRequest Input Thissignalisusedtorequestaturn-aroundoperationforabidirectionallane.

dln_rx_RxClkEsc[3:0]

Output EscapemodeReceiveClockfordatalane0.Thissignalisusedtotransferreceiveddatatotheprotocolduringescapemode.This"clock"isgeneratedfromthetwoLow-PowersignalsintheLaneinterconnect.BecauseoftheasynchronousnatureofEscapemodedatatransmission,this"clock"maynotbeperiodic.

Datasheet


Pin Direction Descriptiondln_rx_RxUlpsEsc[3:0]

Output EscapeUltraLowPower(Receive)modefordatalane.Thisactivehighsignalisassertedtoindicatethatthelanemodulehasenteredtheultra-lowpowermode.ThelanemoduleremainsinthismodewithrxulpsescasserteduntilaStopstateisdetectedonthelaneinterconnect.

dln_rx_UlpsActiveNot[3:0]

Output ULPSsignalreceivedonthereceiverinthebi-directionallane

dln_bd_TxReadyEsc

Output Readysignalforthetransmitdatalinesinreversedirection.

dln_rx_RxDataEsc[7:0]

Output ThelowpowermodedataintheEscapemode.

dln_rx_RxValidEsc Output TheESCmodevaliddata.

dln_rx_RxTriggerEsc[3:0]

Output TheTriggermodereceiversignal.

dln_rx_RxLpdtEsc Output Thelowpowerdatatransferforthefirstlane

dln_rx_ErrEsc Output ErrorontheEscapesequenceduringreceiver

dln_rx_ErrSyncEsc Output Errorinsyncescinthereceivermode.

4.5.14 FunctionalDescriptionofDataPPI’sControlSignalsTable14:FunctionalDescriptionofDataPPI’sControlSignals


dln_RxStopState[3:0]

Output LaneisinStopstatefordatalane.ThisactivehighsignalindicatesthatthelanemoduleiscurrentlyinStopstate.NotethatthissignalisasynchronoustoanyclockinthePPIinterface.

dln_tx_UlpsActiveNot[3:0]

Output ULPState(not)Activefordatalane.ThisactivelowsignalisassertedtoindicatethattheLaneisinULPstate.

dln_ErrorSotHS[3:0] Output Start-of-Transmission(SoT)Errorfordatalane.Ifthehigh-speedSoTleadersequenceiscorrupted,butinsuchawaythatpropersynchronizationcanstillbeachieved,thiserrorsignalisassertedforonecycleofreceiver’sbyteclock.Thisisconsideredtobea"softerror"intheleadersequenceandconfidenceinthepayloaddataisreduced.

dln_ErrorSotSyncHS[3:0]

Output Start-of-TransmissionSynchronizationErrorfordatalane0.Ifthehigh-speedSoTleadersequenceiscorrupted

Datasheet



inawaythatpropersynchronizationcannotbeexpected,thiserrorsignalisassertedforonecycleofreceiver’sbyteclock.

dln_ErrContentionLP0

Output ThecontentionerrorsignalonLP0line.

dln_ErrContentionLP1

Output ThecontentionerrorsignalonLP1line.

dln_rx_ErrControl[3:0]

Output Errorcontrolinlane0duringreceiver

4.5.15 FunctionalDescriptionofSideBandSignalsTable15:FunctionalDescriptionofSideBandSignals


dln_def_dir Input Providesthedefaultdirectionofthebi-directionallane,1’b1-receive,1’b0-transmit.

dln_dpdnswap[3:0] Input Enabledpdnswapondatalanes0to3inHSTxmode.

cln_pll_locked Output PlllockedsignalfromtheDphy

4.5.16 FunctionalDescriptionofDFTSignalsTable16:FunctionalDescriptionofDFTSignals


SCAN_EN Input ScanmodeEnable.SCAN_CLK Input ScanclockSA_SCAN Input Stuck-Atscanmode.SCAN_IN Input ScaninputforAt-speedscan.SCAN_OUT Output ScanoutputforAt-speedscan.DFT_sdi_1to6 Input ScaninputforAt-speedscan.DFT_sdo_1to6 Output ScanoutputforAt-speedscan.

Datasheet


4.5.17 D-PHYUIParameterCountSignalsTable17:D-PHYUIParameterCountSignals

Pin Type Direction Descriptiondln_cnt_hs_prep[7:0] Register Input TheperiodforwhichHSpreparetime

shouldbeaccommodatedfordatalane[40ns]

dln_cnt_hs_zero[7:0] Register Input count[260ns]forTclockcount.dln_cnt_hs_trail[7:0] Register Input TheperiodforwhichHStrailingshould

bedrivenfordatalane[60ns].dln_cnt_hs_exit[7:0] Register Input TheperiodforwhichHSexitstate

shouldbemaintainedfordatalane[110ns].

dln_rx_cnt[7:0] Register Input CounterthatcontrolstheassertionofenableontheDPHYfordatalane

dln_sync_cnt[7:0] Register Input Atimeoutvalueusedforsyncerrordetectorlogicfordatalane.

dln_cnt_lpx[7:0] Register Input WaittimeinbytedatafortheLPXfordatalane.

cln_cnt_hs_trail[7:0] Register Input Waittimeinbyteclockforthetrailingbitsforclocklane[60ns].

cln_cnt_hs_exit[7:0] Register Input waittimeinbyteclockfortheexitstateforclocklane[110ns]

cln_cnt_lpx[7:0] Register Input waittimeinbyteclockfortheLPXforclocklane.

cln_cnt_prep[7:0] Register Input waittimeinbyteclockforthepreparetimeforclocklane[40ns]

cln_cnt_zero[7:0] Register Input waittimeinbyteclockforthezerostateforclocklane[260ns].

cln_cnt_pll[15:0] Register Input ThecountvaluewhichisusedforthePLLlocktime.

dln_cnt_lpx[7:0] Register Input TheperiodforwhichtheLPstateshouldbedriven.

4.5.18 A-BISTRelatedSignalsTable18:A-BISTPins


dln_loop_back Input EnableA-BIST(loopbackBIST)bist_seed[7:0] Input BISTPRBSintiationseedbist_force_error Input SignalisusedtointroduceerrorsintheBISTrun.

Datasheet



bist_en_esc_lp,bist_en_esc_hs

Input Bistmodeselectionpins00->Reserved01->HSMode10->LPMode11->RxClkEscGeneration

bist_err_rx_hs Output ErrorinHSreceptionbist_err_rx_hs_sync Output ErrorinRXHSsyncbist_err_rx_esc Output ErrorinLPreceptionbist_err_rx_esc_sync

Output ErrorinLPrxsync

bist_done Output EndofBISTcomparison

4.6 HardMacroDeliverables• GDS-II• CDLnetlistforLVS• LVSreports• DRCandAntennareports• LIBfiles• User-guideandintegrationguides• LEF• Scan-insertednetlistforDFT• VerificationEnvironmentwithbehavioralmodels

Datasheet


5 Services&Support5.1 GlobalSupportArasanChipSystemsprovideglobalsupporttoitsIPcustomers.Thetechnicalsupportisnotgeographicallyboundtoanyspecificsiteorlocation,andthereforeourcustomerscaneasilygetsupportfordesignteamsthataredistributedinseverallocationsatnoextracost.

5.2 ArasanSupportTeamOurtechnicalsupportisprovidedbytheengineerswhohavedesignedtheIP.Thatisahugebenefitforourcustomers,whocancommunicatedirectlywiththeengineerswhohavethedeepestknowledgeanddomainexpertiseoftheIP,andthestandardtowhichitcomplies.

5.3 ProfessionalServices&CustomizationAtArasanChipSystemsweunderstandthatnotwoApplicationProcessorsarethesame.Werealizethatoftenthestandarditselfneedssometweaksandoptimizationstofityourdesignbetter.Sometimes,theinterfacebetweentheIPblocksandyourdesignneedsomecustomization.Therefore,weprovideprofessionalservicesandcustomizationtoourIPcustomers.WedonotsellourIPblocksas“blackbox”thatcannotbetouched.Pleasecontactusformoredetailsonourcustomizationservices.

5.4 TheArasanPortingEngineAnalogIPblocks,suchaseMMC5.1HS400PHY,aredesignedforaspecificFabandprocesstechnology.Arasan’sanalogdesignteam,utilizingitsdeepdomainexpertiseandvastexperience,iscapableofportingthePHYsintoanyspecificprocesstechnologyrequiredbythecustomer.Thatis“TheArasanPortingEngine”.

5.5 Pricing&LicensingArasanchargesaone-timelicensingfee,withnoadditionalroyalties.ThelicensingfeegivestherighttouseourIPfor1project.Licensingfeeforadditionalprojects,usingthesameIP,isdiscounted.Wealsoofferunlimited-uselicense.Foranyadditionalinformationregardingpricingandlicensing–pleasecontactoursalesat:[email protected].

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