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Direct Conversion Receivers. Qui Luu Dec 2, 2009. Agenda. Wireless communication architectures Dual IF Superheterodyne, Low IF Sampling Single IF Superheterodyne, High IF Sampling Direct (Zero-IF) Conversion Homodyne receiver challenges DC offset Quadrature errors Even order distortions - PowerPoint PPT Presentation
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The World Leader in High Performance Signal Processing Solutions
Direct Conversion Receivers
Qui Luu
Dec 2, 2009
Agenda
Wireless communication architecturesDual IF Superheterodyne, Low IF SamplingSingle IF Superheterodyne, High IF SamplingDirect (Zero-IF) Conversion
Homodyne receiver challengesDC offsetQuadrature errorsEven order distortions
Origins of DC offsetLO feed throughCommon mode mismatch
Theory behind quadrature errorsAmplitude and phase mismatch
Consequences of DC and Quadrature errorEVMOccupy available bandwidth
Implementation of DC and quadrature correction Results Summary
2
Receive Architectures Dual IF Superheterodyne, Low IF Sampling
3
ωIF
DesiredChannel
Image
Cos(ωLO-ωIF)Cos(ωLO)=Cos(2ωLO-ωIF)+Cos(ωIF)
Cos(ωLO+ωIF)Cos(ωLO)=Cos(2ωLO+ωIF)+Cos(ωIF)
ImageRejectFilter
ωLOωIF ωIF
ωLOωIF ωIF
DesiredChannel
Image
Antenna
Receive Band
DesiredChannel
Out-of-band Interferers
In-band Interferers
Receive Band
Band SelectFilter
ωIF
0
Gain Control
0
LPF ADC
Anti-aliasFilter
DDC
Clock Distribution
DSP
DSP
DSP Cluster
Network Interface
BPF
Channel Select Filter
BPF
Low Noise Amplifier
Band SelectFilter
TuningControl
BPF
Image Reject Filter
Tuning Control
BPF
Channel Select Filter
Anti-aliasfilter
fADC/20
RF front-end harmonics
ADC Input
fADC/20ADC Output
Wideband Fundamental
HD2HD3 +
aliased HD3
0
ChannelSelectFilter
ωIF
ChannelSelectFilter
Receive Architectures Dual IF Superheterodyne, Low IF Sampling
Large RF/IF content RF front end
Fixed final LO frequency and mixer, reconfigurable first LO frequency and maybe mixer Final IF amplifier HD2/HD3 may require sharper anti-alias filter Distributed RF gain eases per block noise/gain/IP trade-off
Typically used for multi-band single carrier designs IF ranges to 15MHz
4
AntennaBPF BPF
Band SelectFilter
Channel Select Filter
Tuning Control
BPF
Image Reject Filter
BPF
Gain Control
Channel Select Filter
LPF ADC
Anti-aliasFilter
DDC
Clock Distribution
DSP
DSP
DSP Cluster
Network Interface
5
Receive Architectures Single IF Superheterodyne, High IF
Sampling
ωIF
DesiredChannel
Image
Cos(ωLO-ωIF)Cos(ωLO)=Cos(2ωLO-ωIF)+Cos(ωIF)
Cos(ωLO+ωIF)Cos(ωLO)=Cos(2ωLO+ωIF)+Cos(ωIF)
ImageRejectFilter
ωLOωIF ωIF
ωLOωIF ωIF
DesiredChannel
Image
Antenna
Receive Band
DesiredChannel
Out-of-band Interferers
In-band Interferers
Receive Band
Band SelectFilter
ωIF
BPF
Channel Select Filter
BPF
Low Noise Amplifier
Band SelectFilter
TuningControl
BPF
Image Reject Filter
ωIF
ChannelSelectFilter
ωIF Anti-aliasfilter
fADCfADC/20ADC Input
3*fADC/2 2*fADC 5*fADC/2
RF front-end HD2
Relaxed transition
band
fADCfADC/20ADC Output
3*fADC/2 2*fADC 5*fADC/2
Undersample in-phasefrom 3rd nyquist zone
GainControl
BPF ADC
Anti-aliasFilter
DDC
Clock Distribution
DSP
DSP
DSP Cluster
Network Interface
Receive Architectures Single IF Superheterodyne, High IF Sampling
Cuts out one mixer stage Puts the final mixer requirements on the ADC Last IF mix done in digital domain (digital complex down mix)
RF front end Band reconfigurable first LO frequency and maybe mixer Final IF amplifier HD2 usually of no concern Reduced RF gain distribution requires higher performing RF/IF
ADC needs good IF performance (nyquist or under-sample) IF ranges from 100-300MHz
6
AntennaBPF BPF BPF ADC
Band SelectFilter
Channel Select Filter
GainControl
TuningControl
Anti-aliasFilter
DDC
Clock Distribution
DSP
DSP
DSP Cluster
Network Interface
BPF
Image Reject Filter
7
Receive ArchitecturesDirect (Zero-IF) Conversion
BPF
Low Noise Amplifier
Band SelectFilter
TuningControl
ωRF
0
*Conceptually
BPF
Image Reject Filter
TuningControl
ωRF
Cos(ωRF) Cos(ωRF)=1+Sin2(ωRF)Cos(ωSIG) Cos(ωSIG)=1+Sin2(ωSIG)
BPF
Band SelectFilter
TuningControl
ωRF
α1x(t)+α2x2(t)
Antenna
Receive Band
Band SelectFilter
ωRF
ω2
ω1
0
ω2-
ω1 ω
2
ω1
Feedthrough
0
ω2-
ω1
LNA(t)=α1x(t)+α2x2(t)input(t)=A1Cos(ω1t)+A2Cos(ω2t)
feedthrough(t)=α2A1A2Cos(ω2-ω1)t
0 +ωRF-ωRF
0
GainControl
900
TuningControl
Ph
ase
and
Gai
n E
rro
rP
has
e an
dG
ain
Err
or
900
TuningControl
LPF ADC
Anti-alias/Channel SelectFilter
DDC
Clock Distribution
DSP
DSP
DSP Cluster
LPF ADC
Co
mpl
ex
fADC/20-fADC/2ADC Output
Anti-aliasfilter
LO feedthrough
Unsupressed Quadrature
Image
Homodyne Receiver Advantages and Challenges
Advantages:Low component count leads to lower system costNo image reject filter neededFiltering requirements more relaxed at basebandGain stages at baseband provide power savings
Challenges:DC offset appearing at baseband
Self mixingOffset voltages
Images appearing symmetrically about zero frequency I/Q mismatches in phase and amplitude
Even order nonlinearitiesTwo high frequency interferers close to the channel of interest can result in
even order non-linearities that fall within the band of interest.
8
9
The Imperfect I/Q Demodulator
I/Q DEMODULATOR
LOIN
RFIN0
89.5
G1
G4
G3
G2
fVo s1
V fo s2
I IN
QIN
Imbalance
In Phase
Splitter
Gain
Imbalance
(G1,G2,G3,G4)
Offset
Voltages
Imperfections in the I/Q Signal Path
ControlTuning90
0
R +/- 5%
R +/- 5%
LPF
LPF
Voffset1
Voffset2
Voffset3
Voffset4
ADC
ADC
10
Offsets within the
dual channel ADC
PCB and Layout
mismatches
Component mismatches
Back to Basics : Euler’s Formulas
Sin 0t is 90 out of phase with respect to cos 0t
With perfect amplitude and phase matching the signal content at - 0 cancels
11
Amplitude and Phase Mismatch
Amplitude Mismatch Phase Mismatch
12 0
- 0
A+B2
A-B2
Desired Signal
Image
Effects of Gain, Offset, and Phase Errors
14
-1.5 -1 -0.5 0 0.5 1 1.5-1.5
-1
-0.5
0
0.5
1
1.5
-1.5 -1 -0.5 0 0.5 1 1.5-1.5
-1
-0.5
0
0.5
1
1.5
-1.5 -1 -0.5 0 0.5 1 1.5-1.5
-1
-0.5
0
0.5
1
1.5
fLO
+10% Quadrature Gain Error
fLO
1o Quadrature Phase Error
fLO
+1% Quadrature Offset Error
15
What is causing the poor quality of this demodulated Constellation?
Very poor LO Quadrature Phase Split (in DMOD) DC Offset of the complete constellation (probably LO to RF Leakage) Noise has enlarged the footprint of the constellation points (poor Receiver Noise Figure)
SymbolDecision
ThresholdIf the symbol lands
on the edge or outsideof the box, bit errors
will occur
Effects of I/Q Mismatch
16
f1f0 f2-f0-f1-f2 0
Desired Signal
IdealGain ErrorGain Error IdealPhase ErrorPhase Error
** EVM Degradation **** EVM Degradation **
** Images Occupy BW **** Images Occupy BW ** ** Interfere with Desired Signal **** Interfere with Desired Signal **
DC Offset and Quadrature Error Correction
DC offset and quadrature error correction implemented digitally at the end of the receive chainMost efficient approach in order to compensate for all potential
mismatches or errors in the signal pathDC Correction
If DC free coding is used, a notch filter can be applied Quadrature Error Correction
Gain CorrectionCalculate I^2 – Q^2 to determine the power difference between I and Q.The power difference should be driven to zero.
Phase CorrectionPerform a cross-multiply between I and Q.Can be viewed as a Mixer. The DC term is proportional to the phase
difference between I and Q.By definition this should be zero if they are perfectly orthogonal.
17
18
AD9262: Direct Conversion RX Signal Chain
Discrete signal chain targeting Multi-Carrier base stations.WCDMA, CDMA2000, TDSCDMA, WiMax, LTE
ADL5523: 400 MHz to 4 GHz Low Noise Amplifier ADL5382: 700 MHz to 4 GHz Quadrature Demodulator AD9262: 16-bit Dual Continuous Time Sigma-delta ADC
Integrated DC and Quadrature Error Correction
BANDSELECT
ADL5523
LNA1
ADL5523BPF
LNA2
ADC
ADC
AD9262
50W 1000W
ADL5382
19
AD9269: Direct Conversion RX Signal Chain
Discrete signal chain targeting Multi-Carrier base stations.WCDMA, CDMA2000, TDSCDMA, WiMax, LTE
ADL5523: 400 MHz to 4 GHz Low Noise Amplifier ADL5382: 700 MHz to 4 GHz Quadrature Demodulator AD9269: 16-bit Dual Pipeline ADC
Integrated DC and Quadrature Error Correction
BANDSELECT
ADL5523
LNA1 LNA2
ADL5382
ADC
ADC
AD9269
BPF
AAF
AAF
LO
ADL5523ADL8366
CW Single Tone
QEC DisabledDC Power: -46.4 dBImage Rejection: 58.5 dB
QEC EnabledDC Power: -100 dBImage Rejection: 112 dB
WCDMA Carrier with GSM Blocker
QEC DisabledDC Power: -46.8 dBImage Rejection: 60.8 dB
QEC EnabledDC Power: Image Rejection: 99.2 dB
GSM blocker 10 MHz away from WCDMA carrier At the antenna, blocker power: -25 dBm and WCDMA carrier: -50 dBm
WCDMA Carrier with Modulated Blocker
QEC DisabledDC Power: -46.9 dBImage Rejection: 56.7 dB
QEC EnabledDC Power: -105 dB Image Rejection: 63.2 dB
Blocker 10 MHz away from WCDMA carrier At the antenna, blocker power: -40 dBm and WCDMA carrier: -60 dBm
Summary
Direct conversion or homodyne receivers have there own merits and challenges.
Gain, phase, and offset errors are a few of the challenges that can be addressed with quadrature error correction algorithms
Gain, phase, and offset errors cause degradations in receiver EVM and sensitivity
Quadrature error correction will improve EVM and sensitivityDirect conversion offers advantages in power, cost and
performance over IF sampling architecturesQuadrature error correction enables realizable direct
conversion solutions for macro level basestationsAnalog Devices’ first generation of QEC is available
integrated into the following productsAD9262 – dual 16b continuous time sigma delta ADCAD9269 – dual 16b pipeline ADC
23
AD9262 16-Bit, 2.5/5/10MHz, 30-160MSPSDual Continuous Time Sigma Delta ADC
Temp Package
-40°C – +85°C 9 x 9 mm LFCSP
Pb-Free
Sampling Final Release
Now January 2010
KEY FEATURESKEY FEATURES SNR: 84.5 dBFS to 10 MHz input SFDR: 87 dBc to 10 MHz input
Noise Figure: 15dB Power: 675 mW
Sample rate converter: 30-160 MSPS Selectable bandwidth:
5/10/20MHz complex Passive input network No ADC driver amplifier
Alias immune No Anti-Alias Filter
Integrated Funtions: Decimation filter and Sample Rate Conv.
Quadrature Error and DC offset correction PLL clock multiplier
Low drift voltage reference Serial Control Interface
1.8 V Analog supply
CT Σ-ΔM O DU L A T O R
L O W -P A S SDE C IM A T IO N
F IL T E R
V IN +A
V IN –A
V IN +B
V IN –B
V R E F
AG N D
S A M P L ERA T E
C O N V E R T E R
C M O SBU F F E R
CT Σ-ΔM O DU L A T O R
L O W -P A S SDE C IM A T IO N
F IL T E R
S A M P L ERA T E
C O N V E R T E R
C M O SBU F F E R
D G N D
A V D D
A D 9262
DR V D D
D 15A
O R A
D 0A
D 15B
D 0B
P HA S E-L O CK E D
L O O P
C L K +
C L K –
DC O
O R B
C F IL T
S D IO S C L K
S E R IA LIN T E R F AC E
C S B
QUADRATUREERROR
ESTIMATE
GAIN ADJ
PHASE ADJ
DC
CORRECT
DC
CORRECT
25
AD9269 : 16-Bit, 20/40/65/80 MSPS 1.8V DUAL ADC
Key Benefit Lower Power per channel Small Footprint Outstanding dynamic performance
Temp Package
-40°C – +85°C64-pin LFCSP (9x9mm)
Pb-Free
Sampling Production Qtys
Now Oct09
KEY BENEFITSKEY BENEFITS
Total Power Dissipation = 125 mW / ch @80Msps
Outstanding PerformanceSNR = 77 dBFs @ fIN = 40 MHz @ 80 MSPSENOB of 12.4 @ fIN = 40 MHz @ 80 MSPS
SFDR = 88 dBFs @ fIN = 40 MHz @ 80 MSPS Excellent Linearity
DNL = ±0.7 LSB (Typical)INL = ±5.5 LSB (Typical)
1.8V or 3.3V CMOS outputs 650 MHz Full Power Analog Bandwidth
1Vp-p to 2Vp-p Input Voltage Range Data Clock Output Provided
User Controls via Serial port interfaceOutput Data Format and Mux’d Options
Clock Duty Cycle StabilizerOutput Test patterns
Analog input range adjustmentPower down modes
Quadrature Error Correction 16-bit and 14-bit Pin Compatible family
AD9268-125 (16-bit), AD9258-125 (14-bit)AD9251 (14-bit), AD9231 (12-Bit), AD9204 (10-bit)
REF SELECT
ADC
ADC
VREF
VIN-A
VIN-B
SENSE
VIN+A
VIN+B
GNDAVDD
DUTY CYCLE STABILIZER
CM
OS
OU
TP
UT
BU
FF
ER
CM
OS
OU
TP
UT
BU
FF
ER
D0A
D15B
D0B
CLK+ CLK-
D15A
DRVDD
DIVIDE 1 TO 8
SYNC
PROGRAMMING DATA
DCOA
SDIO SCLK CSB
VCM
RBIAS
MODE CONTROLS
PDWN
SPI
AD9269
DCS DFS
ORA
ORB
OEB
DCOB