Diode in Digital Logic Design

Section 3.1-3.3

Schedule# Date Day Topic Section1 1/14 Tuesday Diagnostic Test  L 1/14 Tuesday Lab protocol, cleaning procedure,

Linus/Cadence intro 

2 1/16 Thursday Fundamental concepts from Electric Circuits

 

3 1/21 Tuesday Basic device physics 2.1L 1/21 Tuesday I-V characteristics of a diode

(Simulation) 

4 1/23 Thursday Drift/Diffusion current

5 1/28 Tuesday Physics of PN junction diode 2.2-2.3L 1/28 Tuesday I-V Curve of a diode 2.36 1/30 Thursday Diode models, application of diodes

in digital logic,review3.1-3.3 (Highlights)

7 2/4 Tuesday Test #1  L 2/4 Tuesday Diode Logic  8 2/6 Thursday Class Canceled!

Outline

• Review• Diode Model• Applications of Diodes in Digital Logic

– OR2– AND2

Different ways of Crossing PN Junction

np=ni2

DiffusionDiffusion

Majority carriers cross the pn junction via diffusion (because you have the gradient)Minority carriers cross the pn junction via drift( because you have the E, not the gradient)

Drift Drift

Reverse Biased DiodeReverse: Connect the + terminal to then side.

Depletion region widens.Therefore, stronger E.

Minority carrier to cross the PN junction easilythrough drift.

Current is composed mostly of drift current contributedby minority carriers.

np to the left and pn to the right.

Current from n side to p side,the current is negative.

E

Forward Biased Diode

Depletion region shrinks due to charges from the battery.The electric field is weaker.Majority carrier can cross via diffusion;Greater diffusion current.Current flows from P side to N side

IS=Reverse Saturation=leakage current

Diode Models

(Exponential model)(Ideal model)

(Constant voltage model)

Choosing a Diode Model

Use the ideal model to develop a quick, rough understanding of a circuit.

If the ideal model is not adequate, uses the constant voltage model, which issufficient for most cases.

Occasionally, we will use the exponential model

Ideal Model of a Diode

(exponential model)(ideal model)

An ideal diode will turn on even for the slightest forward bias voltage.(VD≥0)An ideal diode will turn off even for the slightest reverse bias voltage.(VD<0)

Behavior of Ideal Diode

Ideal diode:Vanode>Vcathode: Diode is onVanode<Vcathode: Diode is offAn ideal current experieincing Vanode=Vcathode, carries no current

I/V Characteristics

An Open—can’t get a current to flow.

A short--can’t get aV to develop across a diode. A diode

Vanode>Vcathode: Diode is onVanode<Vcathode: Diode is offAn ideal current experieincing Vanode=Vcathode, carries no currentIn practice, consider a slightly positive or negative voltage to determine the response of a diode.

Example 1: An OR Gate Realized By Diodes

Assume that “1”=3 V“0”=0 V

Assume “ideal” diode

“0”=0 V

“0”=0 V

Exercise 1: An OR Gate Realized By Diodes

Assume that “1”=3 V“0”=0 V

Assume “ideal” diode

“1”=3V

“0”=3 V

What is Vout?

Exercise 2: An OR Gate Realized By Diodes

Assume that “1”=3 V“0”=0 V

Assume “ideal” diode

“1”=3V

“1”=3 V

What is Vout?

Analysis of an OR Gate

Observations:1.If D1 is on, VA=VOUT and VOUT=“1”2.If D2 is on, VB=VOUT and VOUT=“1”.3.VOUT is 0 if and only if D1 and D2 are “0”

This is an OR gate.

Logic 1=3 VLogic 0=0V

Cadence Simulation of an OR Gate

VA=3 VVB=3 VVOUT=2.459 V≈3V

Cadence Simulation of an OR Gate

VA=3 VVB=0 VVOUT=2.424 V≈3V

Cadence Simulation of an OR Gate

VA=0 VVB=0 VVOUT=0 V

If VD is less than VD, On, the diode behaves like an open circuit.The diode will behave like an open circuit for VD=VD,on

Constant Voltage Model

Cadence Simulation of an OR Gate

VA=3 VVB=0 VVOUT=2.424 VConstant voltage model: 3V-0.6V=2.4 V

If we assume a turn on voltageof 0.6 V, we are not off by too much.

Grid Control

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In Class Exercise

What kind of gate is this?Please assume ideal diode model.

Cadence Simulation of an AND Gate

VA=3 VVB=3 VVOUT=3 V

In Class Exercise

Assume that VA=“1”=3V, VB=“0”=0VPlease assume constant voltage model.What is the output voltage?

Cadence Simulation of an AND Gate

VA=3 VVB=0 VVOUT=0.575 V