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Abstract—A digitally tunable Transconductance-Capacitor Low-pass Notch Filter (LPNF) for Electroencephalography (EEG) application is presented in this research report. Since EEG signals fall into four basic frequency bands, δ (1-4Hz), θ (4-8Hz), α (8-13Hz), and β (13-40Hz), but the power line interference at 60Hz, created by electrode cable and circuitry, has much higher power than the brain signals, the power line interference negatively affects the accuracy of the EEG system. Therefore, a combination of a notch filter and a high-order low-pass filter is employed in this work. With the development of microcontrollers, digital control methods are becoming more frequent in integrated circuit (IC) implementations. Hence, a digital tuning method for this LPNF is in high demand. Due to the digital tuning approach, an automatic calibration of this Gm-C LPNF through a microcontroller can be realized in the future.

Keywords—Digital Tuning Method; Binary Way; Lowpass-Notch Filter; Operational Transconductance Amplifier.

I. INTRODUCTION Electroencephalography systems monitor activities in the brain by recording electrical signals from cerebral nerve cells along the scalp. As the only non-invasive method for measuring brain activities from human scalps, it plays an important role in effectively diagnosing patients with severe neuron muscular disorders, and therefore, it is widely used in research of brain nerves and clinical applications [1]. EEG signals can be categorized into four basic bands, δ (1-4Hz), θ (4-8Hz), α (8-13Hz), and β (13-40Hz) [2]. Since brain signals are very weak, ranging from 2 to 200µV, compared to the Signal to Noise Ratio (SNR) from the power line, the strongest noise source, it is beneficial to include a LPNF in the analog front-end (AFE) of EEG measurement devices [3]. However, fabrications and environmental variations may cause the actual notch frequency to deviate from the nominal value, so there must be a reliable tuning method for the LPNF architecture in order that the notch frequency can be easily calibrated. As a microcontroller has advantages of small size, programmable input and output peripherals, all-in-one design (containing the processor, RAM, and I/O), and low cost, it can

be used to test preliminary designs prior to integrating analog signal processing and digital calibration circuits on the same chip, for which the work described in this report is preparing. The LPNF used in this work is mainly referenced by a single-ended Gm-C filter structure first proposed by Qian et al. and a fully-differential CMOS LPNF designed by Kainan Wang from the Analog and Mixed-Signal Integrated Circuit Research Laboratory at Northeastern University [2], [3]. In Section II, a digitally tunable notch filter is elaborated upon. Then, a comprehensive simulation assessment with Cadence software tools and actual measurements is presented in Section III and Section IV. The focus in Section V is on the future improvements of this digitally tunable LPNF. Conclusions are given in Section VI.

II. TUNABLE FILTER DESIGN

A. Fifth Order Elliptic Low-pass Notch Filter The Transconductance-C (OTA-C) filter in Fig. 1 realizes a fifth-order elliptic filter with a low pass transfer function that contains a notch in Fig. 2. The null frequencies play an important role in determining the notch frequency and stopband ripple in the low-pass filter. Because the brain signals of interest only fall into low frequencies ranging up to 40Hz, the signals out of this range will be treated as noise. In order to remove these noises, it is necessary to have a low-pass filter with extremely narrow transition band. Not only does this kind of elliptic filter act as a low-pass filter, but also it is used as a notch filter. Since the strong power line interference of the EEG system is around 60Hz, it is required to have sufficient attenuation at the notch frequency. In this fifth-order elliptic filter, the null frequencies are very close to the cut-off frequency of the transfer function, which is why the notch is just at the outside of the passband range. Hence, this fifth-order elliptic filter can combine the advantages of both notch filters and low-pass filters. The schematic of the active LPNF is shown in Fig. 1. Since this LPNF is mainly designed for on-chip circuits, the size (chip area) of the filter is one of the main concerns. As OTAs in integrated circuits are much smaller than that of the on-chip inductors, the OTA-C filter is a better design choice for implementation on chips. Additionally, it allows designing the passband gain of the active filters by using Gm-C structures. In this design, all six OTAs have the same transconductance Gm, so the pass band gain is 0dB. Moreover, in order to have deeper

Digitally Tunable Lowpass-Notch Filter Design for Analog Front-Ends in Brain Signal

Measurement Applications Kaidi Du, Student, Marvin Onabajo, Professor

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notch, two null frequencies of the OTA-C filters are combined to a single notch in this fifth-order elliptic filter. According to the schematic in Fig. 1, these two null frequencies can be expressed as:

𝑓" =12𝜋

𝐺()*+𝐶-"𝐶.

(1)

𝑓. =12𝜋

𝐺()*+𝐶-.𝐶2

(2)

𝑓" = 𝑓. (3)

Because these two notches overlap each other, the final notch in this design is deeper compared to the standard elliptic filter design. As tuning for GmOTA may affect the ripples in the pass-band specification, it is better to fix the value of Gm during the tuning process. Therefore, the only way to tune the notch frequency is changing the values of CL1 and CL2 or C2 and C4 by using variable capacitors or by adding extra capacitors with switches. Usually, the switch is easier to operate when one of its two terminals is grounded. Fig. 1 shows that one terminal of CL1 and CL2 is grounded but C2 and C4 are floating between two nodes, so adding extra capacitors with switches to CL1 and CL2 is a better way to tune the notch frequency than using C2 and C4.

B. Digital Notch Frequency Tuning Since microcontrollers can read, implement, and generate digital signals at I/O interfaces, which are chip-operable, inexpensive, and programmable devices with low power consumptions and supported programming environments across multiple standard platforms; they are widely used in the electronics field [5]. The LPNF in this paper is intended for an on-chip application, and therefore, a tuning method involving digital controlling by microcontrollers or on-chip digital circuits will help to compensate for manufacturing process variations. According to the equation (1) and (2), tuning the grounded capacitors, which are CL1 and CL2 shown in Fig. 1, will lead to changes in the notch frequency. Hence, if the value of the grounded capacitors can be controlled by digital signals, digitally tuning the notch frequency will be put into practice. In other words, the notch frequency of the LPNF can be digitally

controlled by connecting digital switches in series with extra capacitors that are parallel with the fixed-value grounded capacitors (CL1 and CL2). The detailed schematic is presented in Fig A-1. In the circuit, all switches are implemented with discrete N-type metal-oxide-semiconductor (NMOS) transistors. Each NMOS switch controls the connection of one extra-grounded capacitor. The drain of the NMOS connects to one lead of an extra-grounded capacitor and its source terminal connects to the ground. In the future, the gate voltage of the NMOS can be controlled by a programmable microcontroller. Currently, the on and off state of the NMOS switch is manually controlled by connecting the gate either to the low voltage power line (3-4V) or to ground, which imitated the digital output signal of the microcontroller. If the voltage at the gate is higher than the threshold voltage of the NMOS, which is equal to voltage value of the low voltage power line, the extra capacitor will be connected in parallel with the fixed value grounded capacitors so that the total value of the grounded capacitors increases and the notch frequency decreases. Digital tuning of the notch frequency is possible by controlling the on and off states of the NMOS switches.

C. Binary Digital Tuning Approach For the purpose of tuning the notch frequency of the LPNF with the largest tuning range and the smallest increment, it is effective and economic to use a binary-weighted method for changing the total values of grounded capacitors. There are 8 bits available in the LPNF design of this work. The value of capacitor at each bit is calculated based on the binary arithmetic rules:

𝐶4 ≅ 𝐶6×24 (4)

Where 𝐶4 is the capacitor value at 𝑛:;bit, and 𝐶6is the capacitor value at LSB.The calculated capacitor value for each code is shown in Table 1. In order to actually build this filter, the component selections also depend on the availability of standard values offered by

Fig. 1. Schematic of the fifth-order single-ended low-pass notch filter [2].

Fig. 2. Typical fifth-order elliptic filter with a low pass transfer function [3]

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component distributors. To make calculations simple, all GmOTA values of OTAs are set to be 9.6mS; C1, C3, and C5 are equal to 30µF; C2 and C4 are equal to 20 µF (Fig. A-1). Cancelling out the power interference at 60Hz is the main goal of this LPNF, so the notch frequency is set to 60Hz. If all values are substituted into equations (1)-(3), the desired notch frequency would be achieved:

𝑓< = 60 =12𝜋

9.6×10AB

𝐶CDEF4G_:E:IJ_<×20×10AK 5

Where 𝑓<, 𝑓", 𝑎𝑛𝑑𝑓. are all equal to the notch frequency and

𝐶CDEF4GPQPRST = 𝐶-< + 𝐶𝑙𝑖X44

(6)

Where 𝑖 = 1,2, 𝑛 = 0,1,2,3,4,5,6,7 . Rearranging equation (4) results in

𝐶CDEF4GPQPRST ≅ 32.42 µμ𝐹 = 𝐶-< + 𝐶𝑙𝑖X44

(7)

To determine the acceptable range of CLi, the worst case must be considered. According to the data sheets [6]-[9], all capacitors have the same 20% tolerance and the range of the GmOTA is from 6.7×10AB𝑆 to 13×10AB𝑆. Therefore, there are two extreme cases: a. If GmOTA is at the lower bound (i.e., GmOTA=6.7×10AB𝑆)

and all capacitors are at the upper bound (i.e., 𝐶×(1 +20%), when only 𝐶-<is used), the notch frequency, which is at the upper bound of the notch frequency range, must be greater than 60Hz. The mathematical inequality expression is

60 < "

.aK.b×"6cd

efT_gQhTgRS×("i.6%)×.6∗("i.6%)×"6ck 8

which implies

𝐶-<_4E(<4IJ < 10.96µμ𝐹 (9)

b. If GmOTA is at the lower bound (i.e. GmOTA=13.0×10AB𝑆), and all capacitors are at the upper bound (i.e. 𝐶×(1 −20%) , when all extra capacitors are used), the notch frequency, which is at the lower bound of the notch frequency range, must be less than 60Hz. The mathematical inequality expression is

60 > ".a

"B.6×"6cd

(efTieopqh)×("A.6%)×.6∗("A.6%)×"6ck 10

where the sum of the nominal value of all extra capacitors is CX_Sum, implying that:

𝐶-< + 𝐶r_sF( > 92.90µμ𝐹 (11) The larger 𝐶-< is, the smaller 𝐶r_sF( is. Because it is better to design with a small increment, 𝐶r_sF( should be small. In this

prototype, the largest 𝐶-< value is 10 µμ𝐹, requiring that 𝐶r_sF( must be greater than 82.92 µμ𝐹. Hence, the capacitor value at the LSB must be

𝐶-st >82.92µμ𝐹2u − 1

≅ 0.325µμ𝐹 (12) The closest available capacitor value of 0.33 µμ𝐹 is selected. The closest available capacitors at other bits are summarized in Table 2. The expected results for the typical and two worst cases are listed in Table 3.

nth Binary Code Capacitor Value at Each Code

0 (LSB) 0.33 µμ𝐹 1 0.66 µμ𝐹 2 1.32 µμ𝐹 3 2.64 µμ𝐹 4 5.28 µμ𝐹 5 10.56 µμ𝐹 6 21.12 µμ𝐹

7 (MSB) 42.24 µμ𝐹 The sum of all extra

capacitors 84.15 µμ𝐹

nth Binary Code

Typical Value

Anticipated minimum value with variation

Anticipated maximum value with variation

0 (LSB) 0.33 µμ𝐹 0.26 µμ𝐹 0.40 µμ𝐹 1 0.68 µμ𝐹 0.54 µμ𝐹 0.82 µμ𝐹 2 1.2 µμ𝐹 0.96 µμ𝐹 1.44 µμ𝐹 3 2.7 µμ𝐹 2.16 µμ𝐹 3.24 µμ𝐹 4 5.6 µμ𝐹 4.48 µμ𝐹 6.72 µμ𝐹 5 12 µμ𝐹 9.60 µμ𝐹 14.40 µμ𝐹 6 22 µμ𝐹 17.60 µμ𝐹 26.40 µμ𝐹

7 (MSB) 47 µμ𝐹 37.60 µμ𝐹 56.40 µμ𝐹

The sum of all extra

capacitors (CX_Sum)

91.51 µμ𝐹 73.21 µμ𝐹 109.81 µμ𝐹

TABLE I CALCULATED EXTRA-GROUNDED CAPACITOR VALUES AT EACH CODE

TABLE II AVAILABLE EXTRA-GROUNDED CAPACITOR VALUES AT EACH CODE

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III. SIMULATION RESULTS All circuits were designed and simulated with ideal components in Cadence. The schematics in Fig. A-2 and Fig. A-3 show the macro model of the LPNF in Cadence. The OTA is modeled as shown in Fig. 3. Table 4 summarizes the simulated specifications of the standalone LPNF. The results are indicated in Table 5. The outputs of the Cadence simulations are shown in Fig. 4, Fig. 5, and Fig. 6. Fig. 4 represents the simulation result when all capacitors and OTAs are at the nominal values. When the ideal switch codes are 11111111 (all NMOS switches are on), the simulated notch frequency is at 34.51Hz; when ideal switches codes are 01000110, the notch frequency is at 60.20Hz; when ideal switches codes are 00000000 (all NMOS switches are off), the notch frequency is at 111.68Hz. Table 5 shows the simulation results in other two extreme cases (the largest gm with smallest capacitors and the smallest gm with largest capacitors, which corresponds to Fig. 5 and Fig. 6).

According to the simulation results in Table 5, it is clear that if Gm is fixed, the notch frequency is inversely correlated to the value of the grounded capacitors (CL1 and CL2). On the other hand, if the value of the grounded capacitors is fixed, the notch frequency increases with the value of Gm. This simulation results agree with the calculated results based on the equations (1) and (2).

Parameters in Cadence Simulation

Typical GminCmax GmaxCmin Code when

Notch @60Hz 01000110 00000110 11101101

Voltage to Open the Switch < 999.9mV < 999.9mV < 999.9mV

Voltage to Close

the Switch > 1V > 1V > 1V

R_OpenSwitch 192KΩ 192KΩ 192KΩ

R_ClosedSwitch 365.2mΩ 365.2mΩ 365.2mΩ

CL_1 10µF 12µF 8µF CL_2 10µF 12µF 8µF

cl2_D7 47µF 56.4µF 37.6µF cl2_D6 22µF 26.4µF 17.6µF cl2_D5 12µF 14.4µF 9.6µF cl2_D4 5.6µF 6.72µF 4.48µF cl2_D3 2.7µF 3.24µF 2.16µF cl2_D2 1.2µF 1.44µF 0.96µF cl2_D1 0.68µF 0.82µF 0.54µF cl2_D0 0.33µF 0.4µF 0.26µF

D27 0 0 1 D26 1 0 1 D25 0 0 1 D24 0 0 0 D23 0 0 1 D22 1 1 1 D21 1 1 0 D20 0 0 1

cl1_D7 47µF 56.4µF 37.6µF cl1_D6 22µF 26.4µF 17.6µF cl1_D5 12µF 14.4µF 9.6µF cl1_D4 5.6µF 6.72µF 4.48µF cl1_D3 2.7µF 3.24µF 2.16µF cl1_D2 1.2µF 1.44µF 0.96µF cl1_D1 0.68µF 0.82µF 0.54µF cl1_D0 0.33µF 0.4µF 0.26µF

D17 0 0 1 D16 1 0 1 D15 0 0 1 D14 0 0 0 D13 0 0 1 D12 1 1 1

Case gm fmin fmax Typical

Case 9600 µμ𝑆 33.90954426 Hz

108.0379579 Hz

Worst Case 1

(G_min, C_max)

6700 µμ𝑆 19.72169675 Hz

62.83457623 Hz

Worst Case 2

(G_max, C_min)

13000 µμ𝑆 57.39896815 Hz

182.8767517 Hz

TABLE III EXPECTED NOTCH FREQUENCY RESULTS IN DIFFERENT SIMULATIONS

Fig. 3. OTA macro model.

TABLE IV PARAMETERS FOR SIMULATIONS IN CADENCE

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Typical GminCmax GmaxCmin D11 1 1 0 D10 0 0 1 c1 30µF 36µF 24µF c2 20µF 24µF 16µF c3 30µF 36µF 24µF c4 20µF 24µF 16µF c5 30µF 36µF 24µF

Gm 9600µS 6700µS 13000µS Rin 26KΩ 26KΩ 26KΩ

Rout 1MΩ 1MΩ 1MΩ Vsin 1mV 1mV 1mV

Fig. 4. Simulated results with typical values of Gm and for capacitors.

Fig. 5. Simulated results with minimum Gm and maximum capacitor values.

Fig. 6. Simulated results with maximum Gm and minimum capacitor values.

IV. MEASUREMENTS The proposed filter was assembled on a breadboard with components ordered from Mouser Electronics. Table 6 lists the

values of key components parameters shown in Fig. A-1. The photo of the circuit is displayed in Fig. 7. All OTAs are biased identically and operate with the same supply voltages of ±18V. There are some differences between Table 6 and Table 4. All ideal switches in Fig. A-1 are replaced by NMOS switches with the same threshold voltage. The values of CL_1 and CL_2 in measurements are larger than those in simulations. The reason is that manufacturing variations were higher than the expected. After adding extra capacitors to CL_1 and CL_2, the total value of the fixed grounded capacitors was 40µF to place the notch frequency at 60Hz. More specifically, 30µF capacitors were added to the original CL_1 (10µF) and CL_1 (10µF), which are marked as four 15µF capacitors in Fig. 7. As a result, the smallest frequency which the notch can reach is about 58Hz.

G_typ and

C_typ G_min and

C_max G_max and

C_min The closest

frequency to 60Hz 59.98 Hz 59.70 Hz 60.25 Hz

fmin 34.51 Hz 20.14 Hz 58.34 Hz

fmax 111.17 Hz 65.16 Hz 187.93 Hz

Gain @60 Hz -61.64 dB -58.78 dB -66.79 dB

Gain @fmin(11111111) -64.77 dB -62.64 dB -66.83 dB

Gain

@fmax(00000000) -60.83 dB -59.28 dB -62.55 dB

Switch Code to place the notch at 60HZ

(MSB→LSB) 01000110 00000110 11101101

TABLE IV (CONT.) PARAMETERS FOR SIMULATIONS IN CADENCE

TABLE V SUMMARY OF SIMULATION RESULTS

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Measurement Notch

Frequency (Hz)

60 Hz (Typical) 58 Hz 120 Hz

Code 11111100 11111111 00000000 D27 1 1 0 D26 1 1 0 D25 1 1 0 D24 1 1 0 D23 1 1 0 D22 1 1 0 D21 0 1 0 D20 0 1 0 D17 1 1 0 D16 1 1 0 D15 1 1 0 D14 1 1 0 D13 1 1 0 D12 1 1 0 D11 0 1 0 D10 0 1 0

NMOS Threshold 1V 1V 1V

VDC 3.75V 3.75V 3.75V R_buffer1 10KΩ 10KΩ 10KΩ R_buffer2 62KΩ 62KΩ 62KΩ C_buffer 0.001µF 0.001µF 0.001µF

CL_1 40µF 40µF 40µF CL_2 40µF 40µF 40µF

cl2_D7 47µF 47µF 47µF cl2_D6 22µF 22µF 22µF cl2_D5 12µF 12µF 12µF cl2_D4 5.6µF 5.6µF 5.6µF cl2_D3 2.7µF 2.7µF 2.7µF cl2_D2 1.2µF 1.2µF 1.2µF cl2_D1 0.68µF 0.68µF 0.68µF cl2_D0 0.33µF 0.33µF 0.33µF cl1_D7 47µF 47µF 47µF cl1_D6 22µF 22µF 22µF cl1_D5 12µF 12µF 12µF cl1_D4 5.6µF 5.6µF 5.6µF cl1_D3 2.7µF 2.7µF 2.7µF cl1_D2 1.2µF 1.2µF 1.2µF cl1_D1 0.68µF 0.68µF 0.68µF cl1_D0 0.33µF 0.33µF 0.33µF

c1 30µF 30µF 30µF c2 20µF 20µF 20µF c3 30µF 30µF 30µF c4 20µF 20µF 20µF c5 30µF 30µF 30µF

vsin 1mV 1mV 1mV Fig. 8 shows the measured transfer function of the LPNF in Fig. 7. This transfer function is based on the collected data from measuring output voltage and input voltage at different frequencies with a Tektronix DPO2024B oscilloscope. It shows that the range of notch frequency in the measurements is from 58Hz to 120Hz depending on the digital code setting. The captured signals at points 1, 2 and 3 in Fig. 8 are shown in Figurers 9-14 (point 1, 2, and 3 are all for the transfer function with the code for a notch at 60Hz). In Figures 9-14, the unit of the vertical axis is dBV(RMS) and the unit of the horizontal axis is Hz. Fig. 9 and Fig. 10 show that when the input signal is at point 1 (5Hz) in Fig. 8, the output signal has

Fig. 8. Transfer function of the LPNF circuit.

Fig. 7. Photograph of the LPNF.

TABLE VI PARAMETERS DURING MEASUREMENT BASED ON SCHEMATIC IN FIG. A-1

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approximately the same amplitude as the input signal. In other words, the gain at 5Hz is almost 0dB as expected. Fig. 11 and Fig. 12 show that the gain at point 2 (55 Hz) in Fig. 8, where stop-band attenuation occurs, is about -70.3-(-30.3)=-40dB. Fig. 13 and Fig. 14 show that when the input signal is at point 3 (60Hz) in Fig. 8, where the notch frequency is located, the gain is -98.1-(-28.8)=-69.7dB. The flat line in Fig. 14 indicates that the output signal is below the noise level, which agrees with expectations.

Fig. 9. Input signal waveform and FFT at point 1.

Fig. 10. Output signal waveform and FFT at point 1.

Fig. 11. Input signal waveform and FFT at point 2.

Fig. 12. Output signal waveform and FFT at point 2.

Fig. 13. Input signal waveform and FFT at point 3.

Fig. 14. Output signal waveform and FFT at point 3.

V. FUTURE WORK — AUTOMATIC DIGITALLY-ASSISTED CALIBRATION

In the future, microcontrollers can be added to control this LPNF design. The microcontrollers will not only control on and off states of NMOS switches, but also automatically determine which switches are on. In other words, microcontrollers will realize the automatic calibration of the LPNF. In order to achieve this goal, there must be a feedback circuit returning the information at the output of the LPNF to the microcontroller. In this case, the Beagle Bone Black microcontroller board will be used as an example. The LPNF design in this paper needs sixteen digital output pins for controlling on and off states of the NMOS switches and two input pins for connecting the feedback circuit. The Beagle Bone Black microcontroller board has sixty five available digital I/Os [10]. The output “high” voltage of each digital output is 3.3V, which is higher than the threshold voltage (1-2V) of the NMOS used in this measurement.

The major part of the feedback circuit design is the Amplitude Detector. In each cycle of the calibration, the output of the LPNF will be monitored by the Amplitude Detector and then send the result to the microcontroller. The logic structure of the envisioned amplitude detection scheme is shown in Fig. 15. There are two outputs in this Amplitude Detector—the Amplitude Detector Output and the On Detector Output. These two outputs will connect with the input pins of the microcontroller. When the calibration of the LPNF starts, a 60Hz test signal will enter the filter, and then the output signal of the LPNF will be compared with the reference voltages (VREF_TYP and VREF_ON) in the Amplitude Detector. VREF_TYP is the threshold voltage for detecting that the signal at 60Hz is cancelled out. If the amplitude of the output signal from LPNF is smaller than VREF_TYP but larger than VREF_ON, it means that the signal at 60Hz is filtered.

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Similarly, VREF_ON is the threshold voltage for detecting that the LPNF is on. When the amplitude of the output signal from LPNF is smaller than VREF_ON, the LPNF is off. For instance, in Fig. 15, there are three sample output waveforms from the LPNF: Waveform 1 occurs when the LPNF is powered off, so there will be the signal which is smaller than VREF_ON coming into the Amplitude Detector; Waveform 2 happens when the notch frequency of the LPNF is at 60Hz, the amplitude of the output signal from the LPNF will be smaller than the unfiltered typical signal amplitude VREF_TYP, which means that most of the output signals of LPNF at 60Hz are canceled out; Waveform 3 happens when the notch frequency of the LPNF is not at 60Hz so the amplitude of the output signal from the LPNF is larger than VREF_TYP. To sum up, the Amplitude Detector’s output results of each waveform are listed in Table 7.

Fig. 15. Amplitude detection scheme in the feedback circuit for the LPNF [12].

The microcontroller will start calibrations with switch codes from 00000000 to 11111111, which means that the notch frequency begins at the maximum value and gradually decreases to the minimum value. To realize this function, the microcontroller will increase one LSB of the switches code each time; i.e., sequentially closing switches to increase the total grounded capacitors value with an increment of 0.33µF. When the feedback signal from the amplitude detector is “11,” the notch frequency of the LPNF is at 60Hz and the microcontroller will stop increasing the switches code; i.e., closing NMOS switches. Consequently, the automatically digitally-assisted calibration through microcontrollers will be realized with the feedback circuit in the future.

Waveform

Amplitude Detector Output

On Detector Output Meaning

1 0 0 LPNF is Power Off

2 1 1 Notch

Frequency Calibrated

3 0 1 Notch

Frequency is not at 60Hz

VI. CONCLUSION A digitally tunable fifth order Transconductance-Capacitor (Gm-C) Low-pass Notch Filter for EEG applications has been presented. The main goal of this design is to realize digitally tuning of the notch frequency to be at 60Hz so that it can filter out the power line interference signal of the EEG front-end system. In the simulations, this LPNF achieves a 61.64dB deep notch at 60 Hz with typical values for each component (using macro models). The notch frequency can be tuned from 34.51 Hz to 111.17Hz. Comparatively, in the real measurement, the LPNF achieves a 69.7dB deep notch at 60Hz. The notch frequency of the real LPNF can be tuned from 58Hz to 120Hz through changing the total value of the grounded capacitors. Because the transconductance of the OTA may vary due to manufacturing process variations or changes of its temperature, a difference between simulations and actual measurements is normal. In the actual LPNF, the total value of the grounded capacitors can be controlled by the on and off state of the NMOS switches, which connect with extra grounded capacitors (cl1_D1~7 and cl2_D1~7 shown in Table 6) in series. By changing the gate voltage of each NMOS switch, the connection of the extra grounded capacitors can be easily added to the fixed grounded capacitors (CL_1 and CL_2). As the values of the extra grounded capacitors are distributed in a binary way, changing the switches code; i.e., changing the gate voltage, will lead to the movements of the notch frequency. The gate voltage of each NMOS switch can be controlled by a microcontroller, such as the Beagle Bone Black microcontroller board, and the feedback circuit will help the microcontroller to calibrate the notch frequency to be at 60Hz. In the future, a microcontroller and a feedback circuit can be added to this LPNF design.

TABLE VII OUTPUT CODE FOR DIFFERENT WAVEFORMS

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APPENDIX

Fig. A-1. Actual LPNF circuit connection.

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Fig. A-2. Macro Model layout design of LPNF in Cadence.

Fig. A-3. Zoomed-in macro model for OTA.

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ACKNOWLEDGMENT This work was supported by Analog & Mixed-Signal Integrated Circuit (AMSIC) Research Laboratory at Northeastern University. The authors thank to Kainan Wang, Li Xu, and Alireza Zahrai for valuable discussions. Kaidi Du received a B.S. degree (summa cum laude) in Electrical Engineering from Northeastern University in 2016. She conducted this independent study project and got the college honors distinction in Electrical Engineering at Northeastern University. She will continue her graduate study in Electrical Engineering at UC Berkeley in Fall 2016. Marvin Onabajo is an Assistant Professor in the Electrical and Computer Engineering Department at Northeastern University. He received a B.S. degree (summa cum laude) in Electrical Engineering from The University of Texas at Arlington in 2003 as well as the M.S. and Ph.D. degrees in Electrical Engineering from Texas A&M University in 2007 and 2011, respectively. During his final year at UT-Arlington he worked in the Analog and Mixed-Signal IC group in affiliation with the National Science Foundation’s Research Experiences for Undergraduates program. From 2004 to 2005, he was Electrical Test/Product Engineer at Intel Corp. in Hillsboro, Oregon. He joined the Analog and Mixed-Signal Center at Texas A&M University in 2005, where he was engaged in research projects involving analog built-in testing, data converters, and on-chip temperature sensors for thermal monitoring. In the Spring 2011 semester, he worked as a Design Engineering Intern in the Broadband RF/Tuner Development group at Broadcom Corp. in Irvine, California. Marvin Onabajo has been at Northeastern University since the Fall 2011 semester. His current research areas are analog/RF integrated circuit design, on-chip built-in testing and calibration, mixed-signal integrated circuits for medical applications, data converters, and on-chip sensors for thermal monitoring. He received the 2015 CAREER Award from the National Science Foundation.

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