Digital to Analog Converters (DAC)

2

©Paul GodinCreated March 2008

Building a DAC

◊ DACs require an output circuit in the form of an amplifier.

◊ The DACs in the following models are op-amps.

◊ Op Amps typically require a positive (VDD) and negative (VEE) supply, and a ground reference (VSS).

DAC 2.2

Operational Amplifier

◊ This Operational Amplifier configuration operates in this general manner:◊ Gain equals the input voltage times the ratio of the

feedback resistor Rf to the input resistor.

VDD

VEE

Rf

Rin

DAC 2.3

Binary-Weighted Resistor DAC

◊ The summing Op-Amp output will be the sum of the input voltages times the ratio of Rf over each Rin(Rf/Rin).

VDD

VEE

Rf

Rin1

Rin2

Rin3

Rin4

DAC 2.4

Binary-Weighted Resistor DAC

◊ The first resistor has no attenuation therefore the voltage is passed. The second R has a ½ ratio so will attenuate by 50%. The 3rd R attenuates by ¼, and the last by 1/8.

◊ This is an inverting amplifier (output voltage is negative)

VDD

VEE

1 kΩ

1 kΩ

2 kΩ

4 kΩ

8 kΩ

DAC 2.5

◊ A 4-bit binary input is applied to the input resistors, with the 1 kΩ resistor considered the MSB.

◊ The resistor ratio for the MSB is 1:1...if the input voltage is 5V, the value for the MSB is 5V.

Binary-Weighted Resistor DAC

VDD

VEE

1 kΩ

1 kΩ

2 kΩ

4 kΩ

8 kΩ

MSB

LSB

DAC 2.6

Binary-Weighted R DAC - Table

◊ Based on an input of 5V for the MSB, the resolution can be calculated:◊ 10002 = 810, therefore each step =

5V/8 = 0.625V per step

◊ Note the amplifier inverts, therefore the output voltage is negative

D C B A VOUT

0 0 0 0 -0.000

0 0 0 1 -0.625

0 0 1 0 -1.250

0 0 1 1 -1.875

0 1 0 0 -2.500

0 1 0 1 -3.125

0 1 1 0 -3.750

0 1 1 1 -4.375

1 0 0 0 -5.000

1 0 0 1 -5.625

1 0 1 0 -6.250

1 0 1 1 -6.875

1 1 0 0 -7.500

1 1 0 1 -8.125

1 1 1 0 -8.750

1 1 1 1 -9.375

DAC 2.7

Exercise

◊ Design a Binary-Weighted Resistor DAC for a 4-bit binary input. Use a 3.30 kΩ resistor for Rf and a 2.20 kΩ resistor for the MSB.

◊ Use EWB to analyse the circuit◊ Complete the table

D C B A VOUT

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

DAC 2.8

Limitations

◊ The Binary-Weighted DAC can be difficult to implement:◊ The resistors must be precise, otherwise the scale steps

will be uneven.◊ The output of logic devices such as gates or flip-flops are

not always at 5 volts and will therefore affect the scale.◊ If switches are used, pull-up resistors will affect the

operation of the device.◊ Larger binary values require progressively larger resistors

for the LSB. For our example:◊ 5 bit = 16kΩ◊ 8 bit = 128kΩ◊ 12 bit = 2.048MΩ

DAC 2.9

Conclusion

◊ There are other configurations for DACs.

◊ Next presentation will look at the R/2R method.

DAC 2.10

©Paul R. Godinprgodin°@ gmail.com

END DAC 2

DAC 2.11