DIGITAL SIGNAL PROCESSOR - TDL

IMPLEMENTATION AND COMPARISON OF COSINE

MODULATED FILTER BANKS ON A FIXED POINT

DIGITAL SIGNAL PROCESSOR

by

KbDAR RAVINDRA BHATE, BE.

\ THESIS

IN

ELECTRICAL ENGINEERING

Submitted to the Graduate Faculty

of Texas Tech University in Partial Fulfillment of the Requirements for

the Degree of

MASTER OF SCIENCE

IN

ELECTRICAL ENGINEERING

Approved

Chairperson of the Committee

Accepted

Dean of the Graduate School

May, 2004

ACKNOWLEDGEMENTS

A lot of people have been involved in making this thesis come tme. I would like

to take this opportunity to express my deepest gratitude for the following people.

I thank my advisor. Dr. Brian Nutter, for showing a great interest in my project

right from the selection of topic to writing the thesis. Our many insightful technical

conversations and his helpfial comments and constmctive crfticism have greatly improved

this work.

I thank Dr. Tanja Karp for the paper that inspired this thesis. Her guidance and

knowledge in this area helped me when things did not seem to go in the right direction.

I would also like to thank the Department of Electrical and Computer Engineering

for providing unlimited access and outstanding facilities in the computer lab as well as

the necessary financial support.

My parents, Ravindra Bhate and Sunanda Bhate and my elder brother, Mandar

have been source of inspiration throughout my life. They have always supported my

dreams and aspirations. I owe a special thanks to them, for their encouragement and

especially remarkable interest in my career.

11

TABLE OF CONTENTS

ACKNOWLEDGEMENTS ii

ABSTRACT vi

LIST OF TABLES vii

LIST OF FIGURES viii

I. INTRODUCTION 1

1.1 Background and Previous Work 1

1.2 Motivation 2

1.3 Outiine of the Report 3

II. COSINE MODULATED FILTER BANKS 4

2.1 Filter Banks 4

2.2 Cosine Modulated Filter Banks (CMFB) 5

2.3 Filter Bank Realization Using Polyphase Filters and Cosine Modulation . . . 6

2.4 Efficient Realization of Polyphase Filter Banks 7

2.5 Decomposition of the Filter Matrices and the Perfect Reconstmction Property 9

III. FIXED-POINT VERSUS FLOATING-POINT HARDWARE 12

3.1 Introduction 12

3.2 Floating-Point and Fixed-Point Representation 12

3.3 Comparison between the Fixed-Point and Floating-Point Hardware for an Audio Application 14

3.4 Choice of the Hardware 15

111

3.5 The Right Tool for the Right Application 16

IV. IMPLEMENTATION OF THE FILTER BANK ON TMS320C6211 FIXED-POINT DIGITAL SIGNAL PROCESSOR 17

4.1 The Development Process 17

4.2 Matlab/Simulink Models for the Cosine Modulated Filter Banks 18

4.2.1 Implementation of the Analysis and Synthesis Filters 18

4.2.2 Implementation of the Modulation Matrices 20

4.3 TMS320C6211 DSK and Code Composer Studio 22

4.4 Overall Stmcture of the Application 23

4.5 Cosine Modulated Filter Bank Implementation in C 25

4.6 Hardware Configuration 26

4.6.1 Chip Select Library (CSL) 26

4.6.2 Multichannel Buffered Serial Port (McBSP) Configuration 27

4.6.3 CODEC Initialization 32

4.6.4 Enhanced Direct Memory Access (EDMA) Controller Configuration 34

4.7 Intermpt Service Routine (ISR) 37

4.8 Creating and Running the Application 38

4.9 Hardware and Software Limitations 42

V. EFFECT OF DIFFERENT PARAMETERS ON THE PERFECT RECONSTRUCTION PROPERTY OF THE FILTER BANK 43

5.1 Effect of including Modulation Matrices 44

5.2 Effect of Filter Length 46

5.3 Effect of Overall System Delay 48

IV

5.4 Nature of the Error 50

5.5 Effect of Number of Channels and Overflow Error 51

5.6 Input Signal Amplitude and SNR 53

VI. CONCLUSION AND FUTURE WORK 55

6.1 Conclusion 55

6.2 Future Work 55

REFERENCES 56

ABSTRACT

Cosine Modulated Filter Banks have an efficient stmcture with respect to the

number of multiplication and delay elements required. They also provide another

desirable feature, perfect reconstmction (PR). However, their ability to provide PR can be

affected due to various parameters, such as fixed-point constraints, imperfect modulation

matrix, etc. In this thesis, effects of these parameters on the ability of the filter bank to

provide PR are studied. To demonstrate the use of the filter bank in a real- time

application, it is implemented using a TMS320C6211 Fixed-point Digital Signal

Processor (DSP). The implementation uses the TLC320AD535 audio Encoder/Decoder

(CODEC), the Multichannel Buffered Serial Port (McBSP) and the Enhanced Direct

Memory Access (EDMA) controller on the DSK6211 board to continuously process and

reconstmct digitized audio data.

VI

LIST OF TABLES

4.1 CSL Modules and Include Files [13] 27

4.2 EDMA Channel Parameter Entries for Each EDMA Event [16] 36

4.3 Different Sections in the SECTIONS Directive [15] 39

vi i

LIST OF FIGURES

2.1 Example of an M-channel Filter Bank [2] 4

2.2 Filter Bank with Polyphase Filters and Cosine Transform 7

2.3 New Realization of the Analysis and Synthesis Filter Bank [2] 9

3.1 Typical Floating-Point Representation [17] 12

3.2 Typical Fixed-Point Representation [20] 13

4.1 Simulink Model for the Filter Bank without Modulation Matrices 18

4.2 Maximum Delay Matrix (Left) and Inverse Maximum Delay Matrix (Right).. 19

4.3 Zero Delay Matrix (Top) and Inverse Zero Delay Matrix (Bottom) 19

4.4 Initialization Matrix (Top) and Inverse Initialization Matrix (Bottom) 20

4.5 Stmcture for Implementing the Modulation Matrices 21

4.6 Filter Bank with the Modulation Matrices 21

4.7 TMS320C6211 DSK [12] 23

4.8 Stmcture for the Audio Application 25

4.9 Multicharmel Buffered Serial Port block diagram [5] 28

4.10 Serial Port Control Register (SPCR) [5] 29

4.11 Receive Control Register (top) and Transmit Confrol Register (bottom) [5] . . . 32

4.12 Voice Channel CODEC Logic Diagram [14] 32

4.13 Data Format for Secondary Communication between CODEC and McBSP Register Read Operation (top), Register Write Operation (bottom) 33

4.14 Enhanced Direct Memory Access (EDMA) Controller [16] 35

4.15 The Linker Command File (*.cmd) 39

Vlll

4.16 Build Options Window in Code Composer Studio 41

4.17 Command Window with Confidence Test Results 41

5.1 Storing Memory Content of DSP to the File 43

5.2 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank without Modulation Matrices (M = 8, D = 15, N = 32) 45

5.3 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices (M = 8, D = 15, N = 32) 45






5.9 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices ( M - 8 , D = 31,N = 32) 49

5.10 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank without Modulation Matrices and White Noise as an Input (M = 8, D = 15, N = 32) 50

IX

5.11 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices and White Noise as an Input (M = 8, D = 15, N = 32) 51

5.12 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank without Modulation Matrices ( M - 1 6 , D = 31,N = 32) 52

5.13 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) and the Filter Bank with Modulation Matrices (M = 16, D = 31, N = 32) 52

5.14 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices (M = 8, D = 15, N = 32) and reduced input signal amplitude 53

5.15 Plots of the Original Signal (Top), Reconstmcted Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices (M = 8, D = 15, N = 32) and increased input signal amplitude 54

CHAPTER I

INTRODUCTION

1.1 Background and Previous Work

The theory of modulated filter banks and methods for their application have been

developed and studied extensively. Still, further advancements continue to be reported in

many areas related to them. Modulated filter banks are implemented based on a prototype

filter and a fast transform. Different modulation schemes for modulated filter banks using

the Discrete Fourier Transform, Discrete Cosine Transform, and Wavelet Transforms are

available. Each modulation scheme has its own advantages and disadvantages. However,

this thesis will focus on the filter banks with cosine transform as the modulation scheme.

During the last decade, the literature and research on the subject of cosine

modulated filter banks were focused mostly on the development of the stmcture that

gives inherent perfect reconstmction, low implementation cost and low overall system

delay [1, 2]. In recent years, research work has continuously developed applications for

the filter banks. The thmst of the research related to cosine modulated filter banks has

been changed to implementation on DSPs for different applications and complexities

associated with that. Some authors have already presented an evaluation of the

performance of filter banks when implemented in the fixed-point format [7, 8, and 10].

The results of these evaluations have showoi interesting promise for filter banks when

used in real-time applications. They also suggest that some newer techniques may

provide much better filter bank performance.

1.2 Motivation

Perfect Reconstmction (PR) of the signal is a desirable property in many signal

processing applications. Cosine modulated filter banks (CMFBs) achieve the PR

property, efficiently using the symmetry property of the modulation matrices. The

stmcture presented in [2] claims to be robust to coefficient quantization, rounding and

overflow in terms of the PR property of the filter banks. This is validated in the most

recent research done in [9]. However, modulation matrices were assumed to be perfect,

although cosine fianctions cannot be perfectly represented using conventional numeric

representations. Preserving the PR property of the CMFB including the modulation

matrices is a good research problem.

Usually filter banks are implemented on a fixed-point DSP when used in different

real-time applications. Fixed-point processors have various advantages over their

floating-point covmterparts such as lower cost, higher speed, less power consumption, etc.

However, the dynamic range of the fixed-point values is much less than floating-point

values with equivalent word sizes. Therefore, in order to avoid overflow or unreasonable

quantization errors, fixed-point values must be optimized by scaling.

The objective of the work presented in this thesis is twofold. The first objective is

to implement the filter bank on the fixed-point DSP and test it for real-time application.

The second objective is to consider the effect of change in filter length, number of

channels, overall system delay, input data format, and inclusion of the modulation

matrices on the PR property of the fifter bank.

1.3 Outline of the Report

Chapter II discusses the basic theory of CMFBs. Chapter III provides background

on the fixed and floating-point arithmetic and hardware. It also discusses why particular

hardware was chosen for implementation. Chapter IV discusses DSP implementation of

the CMFB and issues related to it. Chapter V presents the effects of different parameters

on the PR property of the filter bank. Finally, Chapter VI concludes this work with a

summary of results and a discussion of fiiture work.

CHAPTER II

COSINE MODULATED FILTER BANKS

2.1 Filter Banks

A filter bank is a collection of filters that are divided in two groups, the analysis

side filters and the synthesis side filters. Analysis side filters divide the incoming signal

into sub-bands, while the synthesis side filters merge the sub-bands in one signal. When

the signal is divided into sub-bands, it is possible to process each sub-band separately.

The analysis side also includes dovm-sampling while the synthesis side includes up-

sampling. In the simplest form, the dovm-sampler reduces the input sample rate by an

integer factor, M, by retaining only every M* sample. On the other hand, the up-sampler

increases the input sample rate by an integer factor, M, by inserting M-1 zeros between

consecutive samples. Figure 2.1 shows a typical stmcture of an M charmel Filter bank.

Analysis Side Synthesis Side

Down-sampler Up-sampler

X(i) >

ut

1 > H„(4

—> m^

— > HM

' *Hw)(=^

IM

iu

iM

ttM

^

Sign

al P

roce

ssin

g ^

— > •

— y

— — » •

t M

tM

tM

tM

- +

-*

—>

Fo<.z)

r,(z)

^^)

FMI<»

^

»

^

o *• Y(z)

Output

M-Charaid Filter Bank

Figure 2.1 Example of an M-channel Filter Bank [2]

A simple example of an analysis filter bank is a Hi-Fi audio system, ft separates

the sound signal into bass and treble, and outputs are obtained for two different

loudspeakers. Thus the signal is divided into sub-bands and each sub-band is treated

separately. Each speaker is designed to handle its respective frequency band.

2.2 Cosine Modulated Filter Banks (CMFBs)

CMFBs include down-sampler, up-sampler, filters, and a discrete cosine

fransform for the modulation scheme. The impulse responses and z-transforms of the

analysis side filters are denoted by hk(n) and Hk(z) respectively, where k = 0, ..., M-1, n

= 0, ..., Nh - 1, M = Number of sub-bands of the filter bank, and Nh = Length of the

analysis filters.

Similarly, the impulse responses and z-transforms of the synthesis side filters with

length Nf are denoted by fk(n) and Fk(z) respectively, where k = 0, ..., M-1, and n = 0, ...,

Nf-1 .

The impulse responses of the analysis filters hk[n] and synthesis filters fk[n] are

cosine modulated versions of the prototype filters h[n] and f[n], respectively. They are

given by

hk[n] = 2 X h[n] x cos [H/M x (k + 0.5) x (n - D/2) + 0k ], (2.1)

withn = 0, 1, . . . ,Nh- l,and

fk[n] = 2 X f[n] X cos [UM x (k + 0.5) x (n - D/2) - Gk ], (2.2)

with n = 0, 1, ..., Nf- I, where 6k = (-1)'' ^ n/4, D = Delay of the overaU system in

samples, and M = Number of chatmels.

The overall system delay is calculated by using the following expression:

D = (2 X s X M) + d. (2.3)

In equation (2.3), M represents number of charmels while s and d are integer delay

parameters. The parameter s is given in the design of the prototype filter and it is

calculated using the following equation.

s = ( 2 x M ) - l . (2.4)

2.3 Filter Bank Realization Using Polyphase Filters and Cosine Modulation

From [1, 18, 19], the analysis and synthesis prototype filters are expressed by the

polyphase components GL(Z) and KL(Z), respectively, as

2'M-l , .

H{z) = Y.^-'' X G, (z '^) , where (2.5)

gi^(m) = h{2xmxM -\- L).

VM-\ , . F{z) = X ^ - ^ X K^ (z^^), where (2.6)

z.=o

it̂ (ffj) = / ( 2 x m x M + Z,).

The modulation matrices Ci and C2 are given by

[C,],i =2xcos[;r/Mx(A:-HO.5)x(Z-D/2)-h0j,], (2.7)

where 0 < k < M , 0 < L < 2M, and

[ Q i k i =2xcos[ ; r /Mx(A:-HO.5)x(2M-Z-D/2)-0j , ] , (2.8)

where 0 < 1< 2M, 0 < L < 2M.The polyphase stmcture of the filters is useful for the sub-

band processing, which separates an incoming signal into several sub-band components.

The lengths of the polyphase filters GL(Z) and KL(Z) are determined by the prototype

filter lengths Nh and Nf, respectively. Realization of the polyphase CMFB is shown in

Figure 2.2.

Figure 2.2 Filter Bank with Polyphase Filters and Cosine Transform [2]

From Figure 2.2, it can be seen that the input signal is divided into M sub-bands

on the analysis side. These individual components are passed through the polyphase

filters and the output from the filter is modulated. On the synthesis side, the reverse steps

are performed.

2.4 Efficient Realization of Polyphase Filter Banks

The implementation cost is reduced for the stmcture of the polyphase filter banks

presented in Figure 2.2 using following properties.

The size of the modulation matrices represented by equations 2.7 and 2.8 is

reduced from M x 2M to M x M, using the following equations:

[Cl]k, d-M-L = (-1) [Cl]k, L , [C2]k,M-l-L ^ [C2]k,2M-l-d+L (2-9)

[Ci]k,L+M=(-l) [Cl]k,d-L, [C2]k.3M-l-d+L=^ [C2]k,2M-l-L- (2.10)

From Figure 2.2, it can be seen that on the analysis side, polyphase components

GL (-Z^) and GL+M (-z^) are fed from the same input, allowing two polyphase filters to be

considered jointly. The same holds tme for the synthesis side filters. The analysis filter

mafrix GL(Z) and synthesis filter matrix KL(Z) £ire given by

G,iz) =

K,{z)

G,{-z') {-\rG,_,_^{-z')

{-\yz-'G,^^{-z') z-'G,_,(-z^)

z-'K,_,{-z') {-\y-'K,_,_^{-z')

(-\rz-'K,^^{-z') K,(-z')

, and (2.11)

(2.12)

G^(-z^)

X

(-1)'

- \ k 'J

fi

> w

")

g .a Ul

ran

H V5 O o s ^

IWxM

CO

S T

rans

fom

i

(-1)\

bl 1 1

*lz-' 1 /

/ ( - I ) - '

K,(-z2)

^

^

Figure 2.3 New Realization of the Analysis and Synthesis Filter Bank [2]

The above steps drastically reduce the computations and result in a more efficient

stmcture for the filter bank. Figure 2.3 shows the new realization for the filter bank.

2.5 Decomposition of the Filter Matrices and the Perfect Reconstmction Property

The 2 x 2 filter matrices Gi(z) and Ki(z) represented by equations (2.11) and

(2.12) can be further decomposed into a product of initialization, maximum delay and

zero delay matrices. Mathematically, it is expressed in equation (2.13):

h

G,(z) = 2D,j(z)ZBu(^)><G,,Jz),K,iz) = K,,„Xz)Y,Bll{z)Y^^^^ J=\ i=\ '='0 » o '

The initialization, zero delay and maximum delay matrices in equation (2.13) are

given by equations (2.14) to (2.16), respectively.

Initialization matrices:

G,,„X^) = , and

K,jA^) = (-1)^ /2M(g,,og,_3 -gi.^gLa) SL.3Z -g,^,

-SL,2^~' gro

(2.14)

Zero delay matrices:

B,A^) =

Bti^ =

0 I

1 b,y-' and

-K.,^''- 1 (2.15)

Maximum delay matrices:

D,j{z) =

-"î.,-! 7-.-I

- 1

z"''^ 0

z-"--£)- ' (z) = -5 i.y

,and

Z - ' •

(2.16)

In equations (2.14), (2.15) and (2.16), the variables dy, bL,i, gL,i, gL,2, gL,3, gM,

represent the coefficients of the filters and pL,i, 5LJ have non-negative integer values. The

decomposition of the filter matrices into the product of maximum delay, zero delay, and

initialization matrices is beyond the scope of this thesis. More information about it can be

obtained from [2].

It can be seen from equation (2.15) that the zero delay matrices can increase the

length of the filter bank without affecting the overall system delay. The maximum delay

matrices increase not only the filter length but also the overall system delay.

10

It is also verified in [2] that the filter bank will give PR if

KL(Z) X GL(Z) = (-1)^ z-'̂ -V2M X I, (2.17)

where 0 < L < d -M, L ^ d - M/2, and I is the identity matrix. Equation (2.17) is not the

only condition for PR. Discussion of other conditions for PR is beyond the scope of this

thesis. The details and proof for all the above properties can be obtained from [1,2].

11

CHAPTER III

FIXED-POINT VERSUS FLOATING-POINT HARDWARE

3.1 Introduction

Digital Signal Processors (DSPs) have become the primary means with which

signal processing filters are implemented. Within DSPs, numbers are represented as

either fixed-point or floating-point data types. One of the most important decisions to be

made while implementing the filter bank on a DSP is whether to treat the data and filter

coefficient values as fixed-point or floating-point values. In this Chapter, fixed-point and

floating-point data formats and hardware are compared, and finally a choice is made

between the two.

3.2 Floating Point and Fixed Point Data Representation

Numerical representations in the floating-point and fixed-point formats are shown

in Figures 3.1 and 3.2, respectively.

B<p on «jt field=E Mamiwa field=F

S E; E^ Eg E4 E-j E^ £( E(| F;, F ]̂ F;

InÛcit binary point

Figure 3.1 Typical Floating Point Representation [17]

12

EH •4 8 1 6

1 5 b i t s

D e c i m a l n u m b e r e c j u i v a l e n t D e c i m a l pra in l S i g n fc>jt

Figure 3.2 Typical Fixed Point Representation [20]

From Figure 3.1, it can be seen that the floating-point number is represented by

three fields: a sign bit, an exponent and a mantissa. IEEE 754 standard for floating-point

representation uses 1 sign bft, 8 exponent bfts and 23 mantissa bits. Thus, a number X

represented in IEEE 754 floating point format can be calculated by using equation 3.1.

X = (-l^)(l.F)2^^-'^^> (3.1)

Thus, the decimal equivalent of the binary number 0:10000011:1000 .' .' .'

00000b in the floating point format can be calculated using equation 3.1. The decimal

equivalent of the above binary number is 1.5 x 2^.

In fixed-point format, fractional numbers are represented using a fixed point 2's

complement form, called the Qn format. The typical fixed-point representation of the

number is shown in Figure 3.2. In Qn format, the n signifies the number of bits to the

right of the binary point. Thus, a 16-bit word has one sign bit, (15 - n) integer bits, and n

fractional bits. The binary number 1101000000000000b, for example, in different Q

formats can be interpreted as follows:

Q14: 11.01000000000000b = -2' + 2° + 2"̂ = -0.75

Q15: 1.101000000000000b = -2°+ 2"*+2'^ =-0.375

13

From the above discussion, it can be seen that floating-point numbers have more

dynamic range than fixed-point representation with same number of bits. Greater

dynamic range significantiy simplifies real time implementation. However, floating-point

hardware is more complicated to implement than fixed-point hardware. That means we

need fewer transistors for fixed-point hardware. This, in turn, reduces overall cost and

power consumption of the system. It also means that speed of the fixed-point hardware

will be higher than the floating-point hardware. These advantages make the fixed-point

hardware popular for high volume and low power applications.

3.3 Comparison between the Fixed-Point and Floating-Point Hardware for an Audio Application

CMFBs can be used in variety of signal processing applications. However, audio

is the intended application for this thesis work. We will compare the fixed-point and

floating-point hardware based on two things: dynamic range and programmer's

flexibility.

The first thing to consider is the dynamic range of the peripheral devices such as

analog to digital or digital to analog converters. Their dynamic range may be limited

compared to that of the floating-point processor. Thus even if the floating-point processor

has greater dynamic range, the overall dynamic range of the system will be limited.

The second thing to consider is the programmer's flexibility. The quality of the

audio depends upon the skills of the programmers. They should develop accurate and

efficient algorithms. If the programmers have proper understanding of the mathematics.

14

then they will develop better algorithms which will give better results. Fixed-point

processing puts a lot of responsibility on the programmer's shoulders. But it also gives a

greater degree of flexibility. This is not so with floating-point designs.

3.4 Choice of the Hardware

From sections 3.2 and 3.3, tradftional advantages of the fixed point representation

such as higher speed, lower cost, size and power consumption are apparent, and the

disadvantages such as lesser dynamic range, etc. can be overcome due to greater

programmer flexibility. Therefore, the CMFB was implemented on the fixed-point DSP.

Texas Instruments (TI) offers the most comprehensive development toolset

available for DSP applications. It includes not only software and hardware support but

also an extensive collection of technical documentation. The TMS320C6XXX platform

includes the latest and high performance DSPs, which can be used in variety of

applications. Specifically, TI's TMS320C6211 Digital Signal Processing Starters Kit

(DSK) was used in this thesis work for implementing the filter banks. For targeting the

TMS320C6211 DSP and other peripherals on the DSK, Code Composer Studio (CCS)

software development platform was used. Detailed information about different DSPs and

their applications can be obtained from the TI's web site [12].

15

3.5 The Right Tool for the Right Application

It must be remembered that tmly objective comparison between fixed-point and

floating-point DSP architectures may not be possible. However, it is the application that

dictates the solution, and the quality of the solution depends upon the skill of the software

programmer implementing the application. DSP applications vary widely. Thus there

will be applications where floating-point processors are a better choice than fixed-point

counterparts. Comparison between the fixed-point and floating-point processors is the

separate research topic in itself, and more information regarding this topic can be

obtained from [11].

16

CHAPTER IV

IMPLEMENTATION OF THE FILTER BANK ON TMS320C6211

FIXED-POINT DIGITAL SIGNAL PROCESSOR

4.1 The Development Process

The Simulink models for the CMFB were developed in [9] with different values

for number of channels, overall system delay and filter length. Different built-in blocks in

the fixed-point block set of Matlab were used in these models. However, modulation

matrices were assumed to be perfect. In this thesis work, blocks implementing the

modulation matrices were added to the existing models developed in [9].

These models were used as a reference for creating the C code. Initially, the C

code was developed for the filter bank with 8 charmels, filter length of 32, and overall

system delay of 15. The filter bank was implemented on the fixed-point DSP and tested

for an audio application using compiled C code. Finally, the C code was expanded and

generalized to analyze the effect of various parameters, such as the number of charmels,

overall system delay, filter length and modulation matrices, on the perfect reconstmction

property of the filter bank.

17

4.2 Matlab/Simulink models for the Cosine Modulated Filter Banks

4.2.1 Implementation of the Analysis and Synthesis Filters

In [9], Simulink models for the filter banks were realized by using various built-in

blocks in the fixed-point blockset of Matlab. Figure 4.1 shows the stmcture of the filter

bank implemented in Simulink in [9] without modulation matrices.

Intialization CaHs n>3x2en>_init

FixPI GUI

Signal Tor

l/P Signals

[g

>B 0-

I z I ' - r douun2

*0 E rh

| z j do

0-douun4

4 e I zJ do

& douvnQ

4 •0-& [)el3y1

Analysis Side

Filteis

XJ YJ

X>| .M Y Ul

XJ YJ

X_d-I-M Y_M-I

XJ YJ

X.d'I'M Y_M-I

XJ YJ

X>l-M Y_l*l

Synthesis Side

Filters

XJ YJ

x_dl-u Y_MJ

X d-l-M Y M-1

XJ YJ

X d-l-M Y_MI

X_d-I-M Y_M-I

Signjl Tor Woikspacet L

DeljyS

Figure 4.1 Simulink Model for the Filter Bank without Modulation Matrices

The initialization, the zero delay and the maximum delay matrices described in

Chapter II were realized in Simulink using the fixed-point block set. Their stmcture is

shown in Figures 4.2,4.3, and 4.4.

18

(J> x1

(jy

•1

FixPt

Integer D«l3y1

FIxPt

Oaln

• 1

Z Fl

FixPt

Sum

FIxPt

Integer Deljy

•XT) y2 (jy

x1

y1

x2

• 1

Z Fl

FixPt

Integer Delayl

FixPt

Cain •1

ZFf

FixPt

Integer Delay

FixPt

Sum

y2

y1

Figure 4.2 Maximum Delay Matrix (Left) and Inverse Maximum Delay Matrix (Right)

Q3-X1

X2

FixPi Oaln

-1 z FT

FixPt lr^teg«r D«ljy FixPt

Sum

y1

-KZD y2

x-1

x2

Fi3<Pt <7din

-1 Z Fl FixP-t

Irttegei Delay FixPt Sum

• K Z J y2

Figure 4.3 Zero Delay Matrix (Top) and Inverse Zero Delay Matrix (Bottom)

19

FixPt FixPt Sum2 Integer Delay2

Oul2

FixPt ° " ' 2 Sum2

Figure 4.4 Initialization Matrix (Top) and Inverse Initialization Matrix (Bottom)

The zero delay, initialization and zero delay matrices were cascaded in the proper

order to realize the filters on both the analysis and synthesis sides. These matrices were

masked under the Gf,iter and Kf,iter filter blocks shown in Figure 4.1.

4.2.2 Implementation of the Modulation Matrices

The size of the modulation matrices is MxM for an M channel filter bank, while

the input has the dimensions of I xM. Implementing the modulation matrices essentially

means multiplication of two matrices of size IxM and MxM. Obviously, the output from

the modulation matrices has the dimension of 1 xM. Figure 4.5 shows the stmcture that

performs IxM and Mxl multiplication. M such stmctures were arranged in parallel to

perform the entire multiplication. They were masked imder the multiplication with the

20

analysis and synthesis modulation matrix blocks shown in Figure 4.6. The stmcture of the

filter bank including modulation matrices is shown in Figure 4.6.

r~̂ ~̂ )-

r ° >-ina

<—7—>- -CB>

Figure 4.5 Stmcture for Implementing the Modulation Matrices

r-HM*B

a * , FixPt Scop«2 domi\7

Integer [>elay8

Multipliy miith

jndlysis

modulation

matrix

f-0-I ' H i f l z R I downt I

t-uayim FixPtr-^-TxPtpV] * 1 1 J Integer D 4 M v | [ Z - £ l i y 7 l z _ E do<nin2

XJ Y J

X d + M Y_MJ

,rD«l y4 I 1 l|itftgerD«l y4

downs

-4 • &

XJ Y J

X d-l-M Y_|i*l H

Inti j i ization Cals maxzero Jnil

FbcR

OUI

- > M 1

Multipliy with

synthesis

modulation

matrix

Figure 4.6 Filter Bank with the Modulation Matrices

21

Matlab allows us to explore various issues related to fixed point computations,

such as overflow error, quantization noise, rounding mode, etc. Various built-in blocks in

the fixed-point blockset of Matlab give us the ability to develop the models for various

DSP systems. It is a great tool to begin the fixed point implementation. However, the

Simulink models were used only as a reference for this thesis work, and further analysis

of the filter banks was carried out by mrming the C code on the DSP.

4.3 TMS320C6211 DSK and Code Composer Studio

Figure 4.7 shows a picture of the TMS320C6211 DSK. The DSK includes all the

necessary hardware to run the application developed for this thesis. The DSK can be

cormected to the PC through the parallel port. The DSK provides 4MB additional

Synchronous Dynamic Random Access Memory (SDRAM) and 128Kb external flash

memory. The DSK includes a TLC320AD535 voice/data encoder/decoder (CODEC).

The maximum possible sample rate for either of the CODEC charmels is 11.025 KHz.

The CODEC includes 16-bit Analog to Digftal (ADC) and 15-bft Digital to Analog

converters (DAC). The DSK provides a 16-bit serial port interface for the CODEC and

the host processor. Code Composer Studio (CCS) from TI provides the necessary

development environment to the user. That allows the user to create, run and debug the C

or assembly language code. It also provides various tools to analyze and simulate the

application code.

The DSK combined with CCS provide the easy-to-use, cost-effective

development environment that expedites the whole design process, ft gives designers a

22

great capability to run and test their applications. More information about CCS can be

obtained from [12].

f - n 3.3 V PowBr Supply 2M X tSbil SDRAM (2) EVM Compmiblc

' Dsiiahler Can] t/F

U*erlEO1.U02.UO3

JTAG Header

, TLC320A053S 16-bit

"— Una LsveJ I/O MicrephofM ^ Lin* L«v«l 1/0 Sp«jik«fs

Figure 4.7 TMS320C6211 DSK [12]

4.4 Overall Stmcture of the Application

The C code for the filter bank with 8 charmels, overall system delay of 15, and

filter length of 32 was developed, optimized and tested on the TMS320C6211 DSK. The

code uses different peripheral devices such as Multicharmel Buffered Serial Port

(McBSP), AD535 (CODEC) and Enhanced Direct Memory Access (EDMA) controller.

An analog audio signal is the input for the program. Either a CD player or an audio player

can be used as the input source. The audio data is converted to digitized form by the ADC

in the CODEC. The digitized data is received at the serial port. The data is ttansferred to

memory from the serial port receive buffer using the EDMA controller. The digitized

23

data is tiien filtered by the CMFB implemented on the DSP. Again by using the EDMA

controller, the processed data is transferred to the serial port transmit buffer. Finally, the

data is converted back to analog format by the DAC. The analog audio output can be

heard using the speakers. The overall stmcture for the application is shown in Figure 4.8.

The application is designed to process continuous audio signals. Thus, it is

important that input and output buffers are continuously filled, emptied and processed

simultaneously. This is ensured in the application by using a Ping-Pong buffering

scheme. Ping-Pong buffering uses two sets of data buffers for all incoming and outgoing

data streams. When EDMA is transferring the data in to and out of Ping buffers, the DSP

processes the data in Pong buffers and vice versa. This scheme ensures that the focus of

the DSP remains data processing, while the EDMA takes care of managing the incoming

and outgoing data transfers. To achieve this, the EDMA channels have two parameter

sets instead of one. One parameter set configures the EDMA charmel to transfer the data

to and from the Ping buffers, while the other configures the EDMA charmel to transfer

the data to and from the Pong buffers. More details about the Ping-Pong buffering

scheme can be obtained from [16].

24

Audio

Input From CD Player

Audio Output From the Speaker

^

1

CC )DEC

^

4

Serial Port

—P'

^ •

EDMA Controller

V

PING-PONG receive

•

buffers

Digital Signal

Processor

• ^ '

PING-PONG transmit buffers

Figure 4.8 Stmcture for the Audio Application

The DSP implementation work of the Filter bank was divided in two main

sections. One section implements CMFB. The other section configures and controls

different peripheral devices.

4.5 Cosine Modulated Filter Bank Implementation in C

The code for the filter bank was developed based on a Simulink model. It includes

implementation of the analysis side filters, analysis modulation matrix, synthesis

modulation matrix and synthesis side filters. The filter coefficients as well as the

modulation matrix coefficients use short data format. Some filter coefficients have value

greater than 1, hence, Q14 fixed-point format was used for them. Q15 fixed-point format

was used for the modulation matrices coefficients. It must be remembered that the

optimal fixed-point format for the filter and modulation matrices coefficients will depend

upon coefficient values. The input, as well as all the data that passes through the channel,

25

is in short data format. This reduces the memory requirements and increases the speed of

DSP operations. Memory intensive functions such as printf() and malloc() are totally

avoided in the program

4.6 Hardware Configuration

For the proper functioning of the application, different on-chip and peripheral

devices must be configured and controlled correctly. The following sections describe how

different on-chip and peripheral devices were configured.

4.6.1 Chip Select Library (CSL)

The application uses C language for implementation. We need to have C language

functions that will allow us to configure and control different peripherals. This is where

the C compiler of the CCS is different from most other C compilers and extremely

powerful. The CCS compiler includes a Chip Select Library (CSL). This library provides

the designer various C language callable functions configuring and controlling the

peripherals. CSL includes different modules that are built and stored into a library file.

These library files must be linked with the program so that different functions can be

used in the program. The programmer also needs to initialize the CSL library before any

of the functions included in the library are used. Table 5.1 gives the list of different CSL

modules and their associated include files. More information about the CSL can be

obtained from [13].

26

Table 4.1 CSL Modules and Include Files [13]

Pefiptteral Module (PER)

CACHE

CHIP

CSL

DAT

CMA

EDMA

EMIF

EMIFA

EMIFB

QPIO

1#>I

I2C

IRQ

McASP

McBSP

PCI

PWR

TCP

TIMER

UTOP

VCP

XBUS

OescriptKHi

C a c ^ module

Chi(>«pecjiic module

Top-level module

Device independent data copy/f9t module

Direct memory access modtie

EiAanced direct memory access module

External memory interface modiie

Ext^nsl mermry interface A module

External memory interface B module

Ge?)eral-Purpoee infiutfoutput module

Host port interface mcxMe

Intef-lnte^Bted drci i t modiJe

Interrupt controller module

Mulbctiannel atsito serial port module

Multictian^wl buffered serial port modiie

Pe<riptwrBl component interconnect internee module

Power-dcNm modiie

Tubo decodet ooprooessor modute

Timer mociijle

Utofia interface module

Vitert>i decoder coprocessor modiile

Expanaon bus modide

litctude File

C8l_cacti8.h

C8(_ch»p.h

cal h

csl_dat.h

crt_(Sna.h

cal_e<frna.h

cal_er™f.h

cal_em«fa.ti

eal_emrflc)h

cal_gp(0-h

cal_hpi,ti

cal_i2c.h

cal_irq.h

cSI_nKaep.h

cSl_mciiBp.h

cal_pci.h

cal_pwrh

caJ_tcph

cal_tiiner.h

cal_utoph

cal_¥cp,h

c^_iti)us.ti

Module Support Symbolt

CACHE_SUPPORT

CHIP_SUPPORT

NA

DAT_Sl«>PORT

DMA_SUPPOfiT

EC»UIA_ajPPORT

E I *F_SUI 'PORT

EMIFA_SUPPORT

EM1FB_SUPP0RT

QPIO_SLff»PORT

HP1_SUPPORT

l2C_SUPPORT

IRQ_SUPPORT

MCASP_SUW>ORT

MCBSP_SUPPORT

P a _ S U P P O R T

PVWR_SUPPORT

TCP_»JPPORT

TI IVeR_9UPPORT

UTOP_8UPPORT

VCP_Sl«>PORT

XBUS_SUPPORT

4.6.2 Multichannel Buffered Serial Port (McBSP) Configuration

Two serial ports are available with TMS320C6211 DSP. The programmer can

conFigure and use any one of these ports. For this application, serial port zero (McBSP 0)

was used. Figure 4.9 shows a typical block diagram for the serial port. The working of

the serial port is simple and straight-forward. Either the DSP or the EDMA controller

reads the data fi-om the Data Receive Register (DRR) and writes the data to be

transmitted to the Data Transmft Register (DXR). Data written to DXR is shifted out to

27

the data transmft (DX) pin via the transmit shift register (XSR). Similarly the data

received on the Data Receive (DR) pin is shifted in to the receive shift register (RSR) and

copied into the receive buffer register (RBR). The data in the RBR is then ttansferred to

Data Receive Register (DRR). The data in the DRR can be read by either the DSP or the

EDMA controller.

OF* K l •

CLKX K l * « CLKR BgH 1

FSX FSR E H •

CLKS

McSSf>

" T - H PRFil *

Clock and frame ay rtc g«n«riatiron and cotrtfrol

Muntcdwnnal aeleciDon

Far<T XI NT

REVT XEVT

SZ-iM p«fTpî«ral

Incerrupls to CPU

Syndlrontzallon avBfila to QMA

Figure 4.9 Multichannel Buffered Serial Port (McBSP) Block Diagram [5]

As shown in Figure 4.10, the McBSP has eight configurable control registers that

control its operation. Out of these eight registers, the Multicharmel Control Register

(MCR), the Receive Channel Enable Register (RCER) and the Transmit Channel Enable

Register (XCER) are required for the multichannel operations. This application does not

need multichannel operations, so they will not be discussed any further in this thesis.

28

The Serial Port Control Register (SPCR) contains various status bits related to the

serial port operation. Figure 4.10 shows the SPCR.

31 26 26 24

Reserved FREE* SOFT*

R^) R/W-0 R/W-0

23 22 21 20 FRST

19 18 17 16 QRST XINTM

R/W-0 R/W-0

15 14

XSYIMCERR XEMPTY XRDY XRST

R/W.0 R/W-O R-0 n-0 R/W-0

13 12 11 10 DUB RJUST CLXSTP Reserved

R/W-0 R/W4 RyW-0 R-0

7

DXENA*

6

Reserved

6

1 RINTtH

4 3

RSYNCERR

2

RFULL

1

RRDY

0

RRST

nw-Q R-0 RW-0 RAV-0

' Availatjle only on CBaix^XTIx DSP and C64x DSP. Legend: R = Read orrfy; RW = React'Wriie: ^ = value sifter reset

R-0 R-0 R/W-0

Figure 4.10 Serial Port Control Register (SPCR) [5]

The FREE and SOFT fields of SPCR were set to 0. This means that the serial port

clock will stop immediately after the simulation is stopped. If these bits are set to 1, then

the serial port clock either continues to run after simulation halt or stops after completion

of current transmission. The GRST and FRST fields of SPCR were set to 0 to reset the

sample rate generator and frame synchronization generator. XRDY and RRDY are read

only fields of the SPCR. When the XRDY field is 1, the transmitter is ready for new data.

Similarly when the RRDY field is 1, the receiver is ready to transmit the data to the

EDMA or the DSP. The XRDY and RRDY fields were used to send transmft (XINTM)

and receive (RINTM) interrupt signals to the CPU. Transmit frame (XSYNCERR) and

29

receive frame (RSYNCERR) synchronization error fields were set to 0. These fields are

set to 1 if unexpected frame synchronization errors occur. The XEMPTY field of SPCR

is 1 if XSR is not empty, while the RFULL field of the SPCR is 1 if RBR and RSR are

full. The XRST and RRST fields of the serial port were set to 1. They enable the serial

port ttansmitter and receiver, respectively. The DLB field of the SPCR was set to 0. ft is

mainly used for testing. The RJUST field of the SPCR selects the justification for the

received data. It was set to 0. It fills the Most Significant Bits (MSBs) for the received

data with zeros. The CLKSTP field of the SPCR was set to 0. ft should be used if clock

stop mode configuration is required. The DXENA field of the SPCR was set to 0. ft's

used only in multichannel operations.

The Receive Control Register (RCR) and Transmit Control Register (XCR)

configure that parameter of the serial port for receive and transmit operations. They are

shown in Figure 4.11. The RPHASE and XPHASE fields of RCR and XCR registers

respectively were set to 1. This indicates that for both transmit and receive operation, a

fi-ame has a single phase. The RFRLEN2 and XFRLEN2 fields of the RCR and XCR are

irrelevant, since they specify receive and transmit frame lengths for the second phase.

Similarly, fields RWDLEN2 and XWDLEN2 which specify word length for phase 2 are

irrelevant. The RCOMPAND and XCOMPAND fields of the RCR and XCR specify,

whether the data should be expanded or compressed. For this application, the incoming as

well as the outgoing data use 16-bit format. These fields were set to 0. That means there

will be no compression or expansion of the incoming as well as the outgoing data. The

RFIG and XFIG fields for the RCR and XCR were set to 1. That means the reception and

30

the transmission will continue ignoring spurious frame sync signals. The fields

RDATDLY and XDATDLY of RCR and XCR specify the delay for reception and

transmission of the data. They were set to 1. That means there will be delay of 1 bit. This

is necessary since in case of zero delay, the data must be ready at the positive edge of the

clock and that may not always be the case. The RFRLENl and RWDLENl fields of the

RCR were set to 0 and 2, respectively. That means every frame received by the serial port

has one element and the length of the word is 16. Similarly, XFRLENl and XWDLENl

of tiie XCR were set to 0 and 2, respectively. The fields RWDREVES and XDREVES of

the RCR and XCR were set to 0. They will be set to 1 only if the data transfer starts from

the LSB instead of the MSB.

For Sample Rate Generator Register (SRGR) and Pin Control Register (PCR), the

default values were used.

To configure the serial port registers, the MCBSP_configArgs() function was

used. This function is defined in the "cslmcbsp.h" header file. To specify the values in

different fields of the registers, RMK macros were used. The RMK macros specify the

values for the register fields from MSB to LSB, and the programmer can specify only

writable fields. Different constants related with the McBSP configuration are defined in

the "cslmcbsphal.h" header file. The program used these constants.

31

31 3 0

R P H A S e I 19 18 17

I RWDLE^42 I l=ICOMPArMO | R F I G | RDATDLY |

R/W.O R/W-0 R/W-O

Raa«rv9d I R F R L E N l

(VW-O

I R W D L E N l I R W D R E V R 3 ' | ResBfvad |

3 1

X P H A S E XFRLEIM2 R/W-O

15

2 4 2 3 2 1 2 0 19 18 17 18 I XWDLEKja I X C O t ^ P A N O | X F I O | XOATOLY ]

R/W-O R/W-O

X F R L E N l X W D L E N l I X W D R S V R S t Rasarvad R - O

Figure 4.11 Receive Control Register (Top) and Transmit Control Register (Bottom) [5]

4.6.3 AD535 CODEC Initialization

Six configurable registers control the operation of the CODEC. Figure 4.12 shows

the logic diagram for the voice channel CODEC. Out of the six registers, the first two

registers are not required when the signal is audio.

Z.B V^.BV

HSTX. XMVnM

X . S V I U V Ltn^jOWtrOA

LI HHfHfval Otut Bti«r*r OtfBoraAfM

Figure 4.12 Voice Channel CODEC Logic Diagram [14]

32

There are two types of communications between the CODEC and the serial port:

primary communication and secondary communication. The primary communication

involves data or voice signal transfer between the serial port and the CODEC, while the

secondary communication is dedicated to set or read the 16-bit values of the control

registers. Thus, to configure the control registers, secondary communication is required.

The least significant bit of the 16-bit data determines whether it is a primary or secondary

commvmication. The secondary communication can be requested by setting this bit to

one. Figure 4.13 shows the data format for the secondary communication.

D15 D14 D13 D12 Dl l DIO D9 D8 D7-D0

0 0 R/W 0 0 Register address Don't care

Register Read Operation

D15 D14 D13 D12 Dl l DIO D9 D8 D7-D0

0 0 R/W 0 0 Register address Register Control Information

Register Write Operation

Figure 4.13 Data Format for Secondary Communication between CODEC and McBSP Register Read Operation (top). Register Write Operation (bottom)

33

From Figure 4.13, it can be seen that to write to the control register, the D13 field

should be zero. The fields D10-D8 specify the register address in which data is to be

written, while fields D7 to DO contain the control information.

Control register 3 was written to enable software reset, power down mode, and no

loopback between ADC to DAC. Software reset clears all the counters except the register

contents. The power down obviously helps with saving the power. Loopback mode is

used only when output of the DAC is given back to the ADC. Control register 4 controls

tiie voice ADC gain, which was set to zero Odb. Control register 5 controls the voice

DAC gain which was set to Odb. Control register 6 controls handset gain which was again

set to Odb.

More information about the configuring and working of the CODEC can be

obtained from [14].

4.6.4 Enhanced Direct Memory Access (EDMA) Controller Configuration

The block diagram for the EDMA controller is shown in Figure 4.14. The EDMA

controller includes event interrupt processing registers, event encoder, parameter RAM

and address generation hardware. The event registers capture various EDMA events. The

event encoder decides the priority if more than one EDMA event occurs simultaneously.

Parameter RAM stores various transfer parameters related to the response to these events,

while the address generation hardware provides the necessary addresses for the EDMA

operations.

34

EDMA parameter RAM

Address gensrslion - » to EMIF/perlphoralB

nlmemoi /InteinBfmemory

Ctiannel 0 pmnmeters

Channel 1 parameters

Channel N parameters

Reload channel 0 parameters

Reload channel 1 parametefs

Reload channel N parameters

Unused (scratdh area)

FSM

Event encoder

2, a:!

Figure 4.14 Enhanced Direct Memory Access (EDMA) Controller [15]

Sixteen different EDMA channels are available. Each charmel is tied to a specific

synchronization event. The channel will request a data transfer only if the event assigned

to it occurs. In this application, McBSP 0 was used. EDMA channels 12 and 13

correspond to the events of this serial port. Therefore, these two EDMA channels were

used and configured. To configure these two channels, the EDMA_configArgs() function

was used. This function is defined in the "csledma.h" header file. To configure the

EDMA channels using the above command we need handles. The handles for these

charmels were obtained using the EDMA_open() ftmction. Different entries such as

source address, destination address, etc, which configure the EDMA channels, are stored

in a memory called Parameter RAM (PaRAM). Table 4.2 shows EDMA channel

parameter entries for each EDMA event [16].

35

Table 4.2 EDMA Channel Parameter Entries for Each EDMA Event [16]

WonlO

Wewdl

Word 2

Words

Word 4

WoidS

3 1 0

E D M A Channat Oprtkms Parameter (OFT)

E D M A CharwiBl Source Address ( S R Q

Array/frame count ( F R M C N T ) Element count <ELECNT)

E D M A Chanr>Bl Destination Address (DST)

A r r a y A a m e Index (FRMIDX)

Element count reload (ELERLD)

Element Index (EL£IDX)

Link aitdress (LINK)

EDMA parameter

OPT

SRC

CNT

DST

lOX

RLD

Channel 12 was used to transfer the data from DSP memory to the McBSP. The

source address for the data transfer is a memory location of the DSP, while the

destination address is the address of DXR. Similarly, channel 13 was used for

transferring the data from the McBSP to DSP memory. The source address in this case

for the data transfer is the address of the DRR, while the destination address is a memory

location in the DSP. The number of elements received or transferred per frame by the

EDMA charmels was set to 80. The size of the element in the data transfer was set to 16,

and single dimensional data transfers were used for both the channels. The transfer

complete interrupt bits (TCINT) for both the channels were set to 1. This enables the

transfer complete indication which sets the corresponding bit in the Channel Interrupt

Pending Register (CIPR). This bit in the CIPR is then used to notify the DSP that data

fransfer for a particular channel is finished. More information about the EDMA channel

configuration can be obtained from [15].

Merely configuring the channels is not sufficient. The channels need to be

enabled as well. The charmels were enabled using the EDMA_enableChannel() ftanction.

36

4.7 Interrupt Service Routine (ISR)

This application uses a Ping-Pong buffering scheme. As already explained, when

the EDMA is transferring the data to and from the Ping buffers, the DSP processes the

data in the Pong receive buffer and puts the processed data in the Pong transmit buffer.

When the EDMA and the DSP finish their activities, they switch. Thus, it is necessary to

check four conditions in the application. These conditions include determining when Ping

and Pong receive buffers are completely filled and when Ping and Pong transmit buffers

are completely empty. The interrupt service routine (ISR) determines when these

conditions occur. In section 4.7, it is seen that when the EDMA data transfer is finished,

appropriate CIPR bits are set. The ISR continuously checks the contents of the CIPR to

determine whether any of the four conditions have occurred or not.

The ISR can be created using the Interrupt keyword. An ISR is just like any other

C sub routine, with two restrictions: No parameters can be passed to the ISR, and nothing

can be returned from the ISR. Once the ISR is created, it is important that the address for

the ISR is loaded appropriately in the memory. An assembly language (*.asm) file was

used to store the address for the interrupts. A section assembler directive (.sect) was used

to store the address table for the interrupts. The memory section was named "vectors".

The name of this section (vectors) was used to link the interrupt address table to an

appropriate location in the memory map of the TMS320C6211 DSP. This was done in the

linked command file (*.cmd). In the MEMORY section of the linker command file,

memory locations for the interrupt address table were specified. This section was defined

37

as "vectors". Then the linker command files SECTIONS area was used to place this

named section, "vectors" at the required address.

The interrupt sources in this application are the EDMA channels. In

TMS320C6211 DSP, Interrupt 8 (INT 8) is used to handle the events related to EDMA

channels. Hence, the EDMA event was mapped to Interrupt 8 using the IRQ_map()

function, and using the IRQ_enable() function. Interrupt 8 was enabled. Functions

IRQmapO and IRQ_enable() are defined in the "cslirq.h" header file, while different

macros related to interrupts are defined in the "cslirqhal.h" header file.

4.8 Creating and Running the Application

A new project in Code Composer Studio (CCS) can be created by selecting the

"Project-New" option. Different source files are added to the project choosing the

"Project-Add Files to Project" option in CCS. In addition to the source files, we need the

linker command file (*.cmd) and assembly language (*.asm) file. The linker command

file used in the program is shown in Figure 4.15. From Figure 4.15, ft can be seen that

linker command file includes the MEMORY and the SECTIONS directives. The

MEMORY directive specifies the starting memory address and size allocated for

different sections of the code. The compiler divides the program in different sections such

as global variables, local variables, etc. The SECTIONS directive specifies the memory

location for each of these divisions of the program. Table 4.3 shows different sections in

the SECTIONS directive. This application uses only Internal RAM. If possible, the

program should run from the Internal Random Access Memory (IRAM). This ensures

38

that we get maximum speed for the DSP operations. However, for some applications

external memory will be required.

Table 4.3 Different Sections in the SECTIONS Directive [15]

SiHl it III X . n u e

. t i ' X I

. s w i i t l i

. c o n ^ t

.ciuit

. l 1 S ^

.f;ir

.--ilack

.^y.sniciu

.<-i<)

r)(>< riptitiij

Ciulr

Tiihlcs fur switrli ill^tnlcrioll^

Gl()l);il uiid Si;itic struiu; litoral^

Initi.il v;llll<•^ [or ii;]ubiil, static vars

(TJohal and italic- variaMcs

Clobal and slatich dc* lar<'il far

Stack (hnal v;inal)los)

M(Mnorv for aialloc fiii^ (heap)

BuHVrs for btdio functions

HEHOKV

< VECS: IRAH:

}

SECTIOITS

< v e c t o r s . c in i^ .t;ex* . sâck -bss . cons^ .da«A . f a z -swit icK . sysjnejrt . c i o

o = o =

> > > > > > > > > > >

000000001 000002001

UECS IRAH IRAK IRAH IRAH IRAH IRAH IRAH IRAH IRAH IRAH

1 = OOOOITOOh

Figure 4.15 The Linker Command File (*.cmd)

39

The application also requires different library files. Different functions used in the

program are defined in these library files. The library files can be added to the program

by choosing the "Project-Add Files to the project" in the CCS menu and then selecting

Library files (*.lib) in the Files type box. This application requires the following library

files: "csl621 l.lib", and "rts6201.1ib".

The next step is to select "Project-Build Options" in the menu. By selecting the

compiler tab the following paths shown in equations (4.1), (4.2) and (4.3) must be added:

-i"C:\ti\c6000\dsplib\include", (4.1)

-i"C:\ti\c6000\bios\include", and (4.2)

-d"CHIP_6211". (4.3)

Figure 4.16 shows the build options window in CCS. The folders specified by

these paths include various header files used in the program. The next step is to select the

"Rebuild-AH" option from Project menu. This generates an executable file (*.out) for the

application. To load the program on the DSP, an executable file must be selected in the

"Load-Program" option of the File menu of the CCS.

Before we run an application, ft is always a good practice to run the confidence

test on the TMS320C6211 DSK. This is a built-in program from TI which can be run

from a command window, ft loads the necessary program on the DSP to test different

peripherals. The peripherals have to pass this test, or applications will not work. Figure

4.17 shows the command window in which confidence test was run.

40

Build Options for myaudiotryZ.pil:

General Compiler | Linker | Link Order |

•g -q •^r"DAkib\mvaudiotiv2\Debug" •i"c:\ti\c6000\dsplib\include" •i"cAti\cGOOO\biosMnclude" |-d"_D E B U G "-d''CHI P_G211 "•mvG210

Category:

.Advanced Feedback Files Assembly Parser Preprocessor Diagnostics

^

- B asic —

Target Version:

Geneiate Debug Info;

Opt Speed vs Size:

Opt Level:

Ptogram Level Opt.:

1621X _£j

|FUII Symbolic Debug (-g)

[Speed Most Critical (no ms

[None -^\

[None

d )d

d

OK Cancel Help

Figure 4.16 Build Options Window in Code Composer Studio

C:\WINNT\sYstem32\c !ff!ff!WffrW!ff[l

C : s T I \ C 6 0 e 0 \ D S K 6 X l l s C O N F I E S T > d s k 6 x t ;

T M S 3 2 0 C 6 2 1 1 / 6 7 1 : t DSK C o n f i d e C o p y r i a h t ; <c> 2BB1 b y Te> f i l l r i g h t s r e s e r u e d .

l e s t Run T i m e : 0 7 : 2 6 : 1 9 PM

USER_SU3=0 USEB_SW2=a USER_SWl=a

Connand = ISRftrl Corimand=SDRftli Coini!iand=t1CBSP Conmand 'TIMER ComiTiand=gDMfi C o n n a n d = L E D S . . -fii-e Tl iey F l a s h i n g ? Command =CODEC. . I s T o n e / ' M u s i c P l a y i n g

1 T e c t , Uej-sion 2 - 0 1 , May 2081 Ins t ruments I n c o r p o r a t e d .

B2, 2BB3

. . . R e s u l t = > PASSED?

. . . R e s u l t = > PASSED!

. . . R e s u l t = > PflSSEDt

. . . R e s u l t = > PfiSSED?

. . . R e s u l t = > PfiSSED!



r M S 3 2 B C 6 2 1 1 / 6 7 1 1 DSK C o n f i d e n c e T e s t PASSED? _ , . No t e s t f a i l u r e s f o u n d ?

C l o s i n g Log F i l e : d s k G x t s t . l o g

« » T l i S 3 2 B C 6 2 1 i / 6 V l l DSK C o n f i d e n c e T e s t C o m p l e t e !

C:STI ' sCf .0BBNDSK6XllsCONFTESI>

Figure 4.17 Command Window with Confidence Test Resufts

41

To run the program, one needs an audio or CD player and powered speakers

connected to the DSK. The program can be run by choosing the "Run" option in the

"Debug" menu of CCS. The resufts can be heard from the speakers.

4.9 Hardware and Software Limitations

In addition to the fixed point constraints, the hardware induces other constraints

on the program.

The ADC of the CODEC gives 16-bft resolution. But the DAC gives only 15-bft

resolution. This is because the least significant bit of the 16-bit communication word

between the serial port and CODEC is used to request secondary communication between

the two. The secondary communication is used for control information exchange. It

reduces the cost, since control as well data information is passed through the same bus,

but it does mean that a program using the TMS320C6211 DSK is never going to give

perfect reconstruction of the signal when the input and output are taken through the

CODEC.

The maximum sampling rate through the CODDEC is 11 KHz. Thus for

applications requiring higher sampling rate, the TMS320C6211 DSK can not be used

without modification.

The local variables in the program can not be viewed in the watch window of

CCS. This adds a major limitation on debugging the code.

42

CHAPTER V

EFFECT OF DIFFERENT PARAMETERS ON THE PERFECT

RECONSTRUCTION PROPERTY OF THE FILTER BANK

In the following discussion, the programs for the filter banks were developed and

tested on the DSP with different values of parameters such as channel numbers, overall

system delay, etc. These take the input from a file, and the reconstructed signal is stored

in the DSP memory. The reconstructed signal can be stored in a data (*.dat) file from the

DSP memory. The data file can be selected by choosing the "Data-Save" option in the

"File" menu of CCS. The data format in the data file can also be selected. When the file

name and the data options are selected, the window shown in Figure 5.1 pops up. In this

v^ndow, the address of the data and the length of the data are specified.

Istoring Memory into File « - | ^ ^ B |

Address: |0x00004CBC

L e n ^ : |1000

OK j Cancel j Help |

Figure 5.1 Storing Memory Content of DSP to the File

The data stored in the data file is tiien loaded into Matlab. The comparison

between the input signal, reconstructed signal and error between the two is made in

Matlab. ft must be noted that the file input is used only for analysis and to avoid any

43

errors that may get introduced due to the data converters. In a real-time application, input

from file should be avoided. Also, when we change the filter length, channel numbers or

overall system delay, the values of the modulation mafrix coefficients or filter

coefficients are changed. Thus, it is the programmer's responsibility to choose an

appropriate Q format values for the coefficients and the data signals. In this discussion, M

will represent number of channels, D will represent overall system delay, and N will

represent the filter length.

5.1 Effect of including Modulation Matrices

The plots shown in Figure 5.2 do not include the modulation matrices. Figure 5.3

shows the plots including the modulation matrices. It can be seen that when the

modulation matrices are included, very small amount of quantization error is introduced.

The signal to Noise Ratio (SNR) was calculated using the following formula:

SNR = 20 X logjo [mean(abs{signal)) I mean{abs(noise))].

The SNR is 80.62 db when the modulation matrices are included and obviously it

is 00 when the modulation matrices are not includes since the error is zero.

44

->

a

2

- 2

10

s

o

-s

10

It l O *

- . _ 3

X 1 0 *

: - > —

o

i .-̂ '̂

-- -y^^---

1QO

Jir^

10O

2 0 0

^ ^ J ^ ' ~"

2fXl

i 30Q

i 3 0 0

o i c to 2cra

\

^r:4,^r 4 0 0

i-

4 0 0

^ ' ".^^

5 0 0

^ \

soo

3 0 0 4 o a

\

6CK)

"̂ :

700

1 ^"x^ j

6 0 0

Ix

7O0

^:^^ 8 0 0

- - - - i -

„4-rr ffi30

1

9 0 0

L-^"^

1300

siaD BCKD 7 0 0 SOD

f - * -^ '—-_

1CKDO

^ • - ^ • ^ ^

1 0 0 0

a x i 1CX30

Figure 5.2 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank without Modulation Matrices (M = 8, D = 15, N = 32)

10

s -

D

-5

-10

^piw^^wi^^

Figure 5.3 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices (M = 8, D = 15, N = 32)

45

5.2 Effect of Filter Length

Figures 5.4 and 5.5 show the plots with N = 64 and N = 96, respectively, without

modulation matrices. We continue to get perfect reconstruction, however inclusion of the

modulation matrices induces an error in the reconstructed signal.

Figures 5.6 and 5.7 show the plots for the filter ban including the modulation

matrices. The SNR with inclusion of modulation matrices for N equal to 64 and 96 is

64.47db and 80.12 db.

Figure 5.4 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank without Modulation Matrices (M = 8, D = 15, N - 64)

46

-a'cBU-H

Figvu-e 5.5 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank without Modulation Matrices (M = 8, D = 15, N = 96)

1000


47

lacioti.

Figiure 5.7 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices (M = 8, D = 15, N = 96)

5.3 Effect of Overall System Delay

The plots shown in Figures 5.8 and 5.9 are obtained for filter banks with delay of

31 samples between the input and the output, ft can be seen that even though the overall

system delay is changed, we continue to get perfect reconstruction when modulation

matrices are not included. However, when the modulation matrices are included, the error

magnitude has increased. This is due to inexact filter coefficient values. The SNR with

inclusion of modulation matrices is 46.72 db.

48

! ! ! ! !

i /-^""^"^^k \ \X^^^ ^.^_^J^ ] i^--lL^~-^

1 1 i i i

! ' ! ' ' ' !

"̂ ""̂ i p^^^---^̂J-̂^̂

1 i i

Figure 5.8 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for Filter Bank without Modulation Matrices (M = 8, D = 31, N = 32)


49

5.4 Nature of the Error

We have seen that including the modulation matrices induces an error in the

reconstructed signal. It was important to study the nature of the error. Therefore, the filter

bank was tested with white noise. It can be seen from Figure 5.10 that we continue to get

perfect reconstruction when the modulation matrix is not included. However, when the

modulation matrices are included, we induce an error in the reconstructed signal. The

nature of the error depends upon the input. The SNR in this case is 66.56db.

Figure 5.10 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank without Modulation Matrices and White Noise as an Input (M = 8 ,D=15 ,N = 32)

50

wwiWi m 9 0 0 1000

1C» 200 30O

^^f%|^f(||lll^|^^

10O 2 0 0 3 0 0

Figure 5.11 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices and White Noise as an Input (M = 8 , D = I 5 , N = 32)

5.5 Effect of Number of Channels

So far in the discussion, we have considered only 8-chaimel filter banks.

However, results for the filter banks with 16 channels are shown in Figures 5.12, 5.13.

From Figure 5.12 ft can be seen that when modulation matrices are not included, we

continue to get perfect reconstruction. Figure 5.13 shows the results when the modulation

matrices are included. The SNR with inclusion of modulation matrices is 78.93db.

51

—

-^.^

1

^'^

1

--V

4

"

^ v -

1 1

-'y^.

i

1

4--i

1

\

- v = - , ^

y\

i

-_^^

—

Figure 5.12 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) and the Filter Bank without Modulation Matrices (M = 16, D = 31, N = 32)

Figure 5.13 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) and the Filter Bank with Modulation Matrices (M = 16, D = 31, N = 32)

52

5.6 Input Signal Amplitude and SNR

Figure 5.3 shows the plots for the filter bank with M = 8, D = 15, and N = 32

including modulation matrices. The plots in Figures 5.14 and 5.15 are also obtained for

the filter bank witii the same parameter values. The difference between the plots in

Figures 5.3, 5.14, and 5.15 is the input signal amplitude, ft can be seen that the plots in

Figure 5.3 have higher input signal amplitude than the plots in Figure 5.14 and lower

input signal amplitude than the plots in Figure 5.15. The SNR calculated for the plots in

Figure 5.3 is 80.62db. The SNRs calculated for the plots in Figures 5.14 and 5.15 are

76.3db and 80.86db. Thus, ft can be cleariy seen that SNR gets affected depending upon

the input signal amplitude.

Figure 5.14 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices (M = 8, D = 15, N = 32) and reduced input signal amplitude

53

Figure 5.15 Plots of the Original Signal (Top), Reconstructed Signal (Middle) and Error (Bottom) for the Filter Bank with Modulation Matrices (M = 8, D = 15, N = 32) and increased input signal amplitude

54

CHAPTER VI

CONCLUSION AND FUTURE WORK

6.1 Conclusion

In this thesis work, DSP implementation of the CMFB is presented. The DSP

implementation of the filter bank was successfully tested for real-time audio input.

It was verified that if modulation matrices are excluded, then the filter bank

provides perfect reconstruction irrespective of the filter length, overall system delay and

number of charmels.

It was observed that the modulation matrices induce an error in the reconstructed

signal. The natvire of this error depends upon the input signal.

It was shown that the SNR depends upon the input signal amplitude. Higher the

input signal amplitude better is the SNR.

6.2 Future Work

The cosine transform is used for modulation for various reasons. However since

the cosine ftmction is expressed using Pi and Taylor series, we will never able to

represent the cosine values exactiy in a digftal system. Thus it may be interesting to look

for an alternative ftmction that can be exactly represented, ft will help in avoiding the

possible quantization error.

55

REFERENCES

1. Peter Niels Heller, Tanja Karp, Truong Nguyen, A general formulation of Modulated Filter Banks, IEEE Transactions on Signal Processing 47 (1999), no. 4, 986-1002.

2. Tanja Karp, Alfred Mertnis and Gerald SchuUer, Efficient biorthogonal cosine modulated filter banks, EURASIP, Signal Processing 81(2001), no.5, 997-1016.

3. DSP/BIOS by Degrees: Using DSP/BIOS (CCStudio 2.0) Features in an existing Application, Application report, SPRA783A, Texas Instruments, Dallas, TX, September 2001.

4. Applications using the TMS320C6000 Enhanced DMA, Application report, SPRA 636A, Texas Instruments, Dallas, TX, October 2001.

5. TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide, SPRU580A, Texas Instruments, Dallas, TX, October 2003.

6. Mullish Cooper, The Spirit of ' C , West Publishing Company, St. Paul, MN, 1993.

7. Yang Yuan, Juuso Alhava, Marku Renfors, Implementation of Perfect Reconstruction Cosine Modulated Filter banks, Telecommunications Laboratory, Tampere University of Technology, Tampere, Finland.

8. Florian Keiler, Udo Zolzer, DSP Implementation of a Low-Delay Filter Bank for audio applications, Department of Signal Processing and Communications, University of German Federal Armed Forces, Hamburg, Germany.

9. Ryan Casey, Efficient Realization of low delay fixed point cosine modulated filter banks with perfect reconstruction. Master's thesis, Texas Tech University, Lubbock, TX, 2001.

10. Magnus Nord, Cosine Modulated Filter banks Implementation and Comparison, Master's Thesis, Linkoping Institute of Technology, Linkoping, Sweden 2003.

11. Moorer James A, "48-Bft Integer Processing beats 32-bit Floating point for professional Audio Applications." Presented at the 107th AES Convention, Preprint Number 5038 (L-3), September 24-27, 1999.

12. Texas Instruments, Worid Wide Web, www.ti.com.

56

http://www.ti.com

13. TMS320C6000 Chip Support Library, API reference guide, SPRU401G, Texas Instruments, Dallas, TX, June 2003.

14. TLC320AD535C/I Dual Channel Voice/Data CODEC Data Manual, SLAS202B, Texas Instruments, Dallas, TX, 2000.

15. Nasser Kehtarnavaz and Mansour Keramat, DSP system design using TMS320C6000, Prentice Hall, Englewood Cliffs, NJ, 2001.

16. TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) controller reference guide, SPRU234, Texas Instruments, Dallas, TX, July 2003.

17. Emmanuel C Lfleachor and Barrie W. Jervis, Digital Signal Processing, A practical approach, 2"'' edition. Prentice Hall, Harlow, England, 2002.

18. P. P. Vaidyanathan, Multirate Systems and Filter Banks, Englewood Cliffs, NJ, Prentice Hall, 1992.

19. H. Malvar, Signal Processing with lapped transforms, Artech House, Norwood, MA, 1992.

20. Lim Hong Swee, Implementation of G.729 on the TMS320C54X, Application report, SPRA656, Texas Instruments, Dallas, TX, March 2000.

57

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