Q1. N number of EX-NOR gates is connected in series such that
the N inputs (A0, A1, A2......) are given in the following way:
A0 and A1 is being given to first EX-NOR gate and A2 and output
of first EX-NOR is being given to second EX-NOR gate and so on. Nth
EX-NOR gate's output is final output. How does this circuit work?
Explain in detail?
Q2. A component called "CMPR" with 2 inputs - A and B, and 2
outputs - K and R. If you pass 2 n-bit numbers to the component
CMPR, the component produced the biggest number at the output K and
the smallest number at the output R.Using minimum numbers of these
components "CMPR", Design a component "ARK" with 4 inputs A, B, C
and D and 4 outputs P, Q, R and S in which
'P' is the max (A, B, C, D), 'S' is the min(A, B, C, D). 'Q' is
bigger than 'R' but smaller than 'P' and 'R' is bigger than 'S' and
smaller than 'Q'
Q3. In a base-7 number system having the digits 0,1,2, A,B,6
respectively and their place values are -3,-2,-1,0,+1,+2,+3
respectively, then:a). What is the maximum decimal value that can
be formed? b). (A0B1) + (1AB0) = ?
Q4. Perform BCD addition and subtraction of followinga). 87 39b)
18 72c). 65 12
Q5. Represent following decimal numbers in OCTAL a). 128b).
123c). 8 Q6. Design a state machine, that outputs a '1' one and
only when two of the last 3 inputs are '1'. For example, if the
input sequence is 0110_1110 then the output will be 0011_1101.
Assume that the input 'Z' is a single bit serial line.
Q7. What is tpd (Propagation delay) for this circuit? What is
tcd (Contamination delay) for this circuit? What is tpd of the
fastest equivalent circuit built using only above 3 components?
Here: tpd - Max. cumulative propagation delay considering all path
b/w input and output. tcd - Min. cumulative contamination
delayInverter: tcd = 0.5ns, tpd = 1.0ns, tr = tf = 0.7ns2-input
NAND: tcd = 0.5ns, tpd = 2.0ns, tr = tf = 1.2ns2-input NOR: tcd =
0.5ns, tpd = 2.0ns, tr = tf = 1.2ns
Q8. Construct a synchronous moore state machine with two inputs,
A and B, and two outputs, X and Y. The machine accepts data on two
input lines synchronously with the clock. The output X is 1 if and
only if the data on the two input lines have been identical (i.e. A
and B are both 1, or A and B are both 0) for the last three or more
consecutive clock cycles. Output Y is 1 if and only if the data on
the two input lines have been complements of each other (i.e. A = 1
and B = 0, or A = 0 and B = 1) for the last three or more
consecutive clock cycles.
Q9. During third world war in the land of Logicia in the year
2099 there is a shortage of XOR gates. Unfortunately, the only
logic gates available are two weird components called X and Y. The
truth table of both components is presented below - Z represents a
High-Z value on the output. Could you help the poor engineers of
Logicia to build an XOR gate?
Q10. Construct a 4-bit Johnson counter using 4-bit shift
register and inverter cell.
Q11. Construct a 4-bit Johnson counter using a ring counter.
Q12. Write a verilog code for following circuitsa). 1-Bit D-flip
flopb). 1-Bit toggle (T) flip flopc). Clock divider by 6 with 50 %
duty cycle using 1-Bit D & T flip flops d). Clock divider by 3
with 50 % duty cycle using 1-Bit D & T flip flop
Q13. Write a Verilog code for Factorial N
Q14. A and B are the signed inputs to an arithmetic circuit. A
is 8-bit width and B is 5-bit width. Write Verilog code to generate
following outputs, X = A + B; Y = A * B Z = B - A
Q15. Write a Verilog code using function. The inputs to function
are A, B, and C, each input is of n-bit width. Function should
return following outputs X, Y, Z, X = A + B; Y = X * C; Z = A*C + B
*C; Q16: Draw the waveforms for the following reg clk ;reg q;always
#10 clk = ~clk;a). always @(clk) q = #5clk;b). always @(clk) q =
#10 clk;c). always @(clk) q = #15 clk;Q12: Draw the waveforms for
the following reg clk ;wire q; a). assign #5 q = clk;b). assign #10
q = clk;c). assign #15 q = clk;
