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Digital Integrated Circuits - week six -. Gheorghe M. Ş tefan http://arh.pub.ro/gstefan/ - 2014 -. Non-recursive definition. Size = ? Depth = ? Fan-out = ?. Application: computes min-terms. Example of using DCDs as CLC. Demultiplexors. - PowerPoint PPT Presentation
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Gheorghe M. Ştefan http://arh.pub.ro/gstefan/
- 2014 -
Non-recursive definition
2014 Digital Integrated Circuits - week five 2
Size = ?Depth = ?Fan-out = ?
Application: computes min-terms
2014 Digital Integrated Circuits - week five 3
Example of using DCDs as CLC
2014 Digital Integrated Circuits - week five 4
Demultiplexors
2014 Digital Integrated Circuits - week five 5
The signal enable is demultiplexed (distributed, scattered) in m = 2n places according to the code xn-1, xn-2, … x0
Formal definition
2014 Digital Integrated Circuits - week five 6
The circuit is simpleThe Verilog description is synthesisable Size = ?Depth = ?Complexity = ?
Recursive definition
2014 Digital Integrated Circuits - week five 7
Size = ? Depth = ? Fan=out = ? Complexity = ?
Multiplexors
2014 Digital Integrated Circuits - week five 8
Gathers data form m=2n placesaccording to the selection code xn-1, xn-2, … x0
Size = ?Depth = ?
Formal definition
The code is ready for synthesis Complexity = ?
2014 Digital Integrated Circuits - week five 9
Recursive definition
2014 Digital Integrated Circuits - week five 10
Recursive definition (cont)
2014 Digital Integrated Circuits - week five 11
Expanding the input size
2014 Digital Integrated Circuits - week five 12
Application: logic function implementation
2014 Digital Integrated Circuits - week five 13
Increment
2014 Digital Integrated Circuits - week five 14
EINC: half-adder Good news: Size O(n)Bad news: Depth O(n)
Adder
2014 Digital Integrated Circuits - week five 15
Good news: Size O(n)Bad news: Depth O(n)
Adder: behavioral description
2014 Digital Integrated Circuits - week five 16
Carry-Look-Ahead
2014 Digital Integrated Circuits - week five 17
Bad news: Size O(n3)Good news: Depth O(log n)
Arithmetic & Logic Unit (ALU)
2014 Digital Integrated Circuits - week five 18
Home work 6 Problema 1: Folositi metoda descrisa in slide-ul 4 pentru a
realiza un scazator complet de un bit (tableul de adevar l-ati definit in prima tema de casa)
Problema 2: Folositi metoda descrisa in slide-ul 13 si proiectati un circuit care semnaleaza cand pe intrare majoritea bitilor au valoarea 1.
Problema 3: Desenati cu porti AND si OR un circuit Carry-Look-Ahead pentru un sumator de numere de 4 biti. Care este size-ul si depth-ul circuitului rezultat?
2014 Digital Integrated Circuits - week five 19