Digital Integrated Circuits · © Digital Integrated CircuitsEE141 2nd 4 Wires Wire Models All-inclusive model Capacitance-only

EE141 1© Digital Integrated Circuits2nd Wires

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

The WireThe Wire

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

July 30, 2002


The WireThe Wire

transmitters receivers

schematics physical


Interconnect Impact on ChipInterconnect Impact on Chip


Wire ModelsWire Models

All-inclusive model Capacitance-only


Impact of Interconnect ParasiticsImpact of Interconnect Parasitics

Interconnect parasitics reduce reliability affect performance and power

consumption Classes of parasitics

Capacitive Resistive Inductive


10 100 1,000 10,000 100,000

Length (u)

No

of

net

s(L

og

Sc

ale)

Pentium Pro (R)

Pentium(R) II

Pentium (MMX)

Pentium (R)

Pentium (R) II

Nature of InterconnectNature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie

So

urc

e:

Inte

l


INTERCONNECTINTERCONNECT


Capacitance of Wire InterconnectCapacitance of Wire Interconnect

VDD VDD

VinVout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CL

SimplifiedModel


Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

diint

ε=LL

Cwire SSS

SS

1=⋅

=


PermittivityPermittivity


Fringing CapacitanceFringing Capacitance

W - H/2H

+

(a)

(b)


Fringing versus Parallel PlateFringing versus Parallel Plate

(from [Bakoglu89])


Interwire CapacitanceInterwire Capacitance

fringing parallel


Impact of Interwire CapacitanceImpact of Interwire Capacitance

(from [Bakoglu89])


Wiring Capacitances (0.25 Wiring Capacitances (0.25 µµ m CMOS)m CMOS)




Wire Resistance Wire Resistance

W

L

H

R = ρH W

L

Sheet ResistanceRo

R1 R2


Interconnect Resistance Interconnect Resistance


Dealing with ResistanceDealing with Resistance

Selective Technology Scaling Use Better Interconnect Materials

reduce average wire-length e.g. copper, silicides

More Interconnect Layers reduce average wire-length


Polycide Gate MOSFETPolycide Gate MOSFET

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi

Conductivity: 8-10 times better than Poly


Sheet ResistanceSheet Resistance


Modern InterconnectModern Interconnect


Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric




InterconnectInterconnectModelingModeling


The Lumped ModelThe Lumped Model

Vout

Driver

cwire

V i nC l u m p e d

R d r i v e rV o u t


The Lumped RC-ModelThe Lumped RC-ModelThe Elmore DelayThe Elmore Delay


The Ellmore DelayThe Ellmore DelayRC ChainRC Chain


Wire ModelWire Model

Assume: Wire modeled by N equal-length segments

For large values of N:


The Distributed RC-lineThe Distributed RC-line


Step-response of RC wire as a Step-response of RC wire as a function of time and spacefunction of time and space

0 0 .5 1 1 .5 2 2 .5 3 3 .5 4 4 .5 50

0 .5

1

1 .5

2

2 .5

tim e (n se c)

volta

ge (V

)

x = L /1 0

x = L /4

x = L /2

x= L


RC-ModelsRC-Models


Driving an RC-lineDriving an RC-line

V i n

R s V o u t

(rw,cw,L)


Design Rules of ThumbDesign Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> √ tpgate/0.38rc rc delays should only be considered when the

rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RC when not met, the change in the signal is slower

than the propagation delay of the wire

© MJIrwin, PSU, 2000

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Digital Integrated Circuits · © Digital Integrated CircuitsEE141 2nd 4 Wires Wire Models All-inclusive model Capacitance-only