DIGITAL IMAGE WATERMARKING SYSTEM

8/7/2019 DIGITAL IMAGE WATERMARKING SYSTEM

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DIGITAL IMAGE WATERMARKING SYSTEMDESIGN & ANALYSIS FOR FPGA ANDSTANDARD CELL IMPLEMENTATION

1. INTRODUCTION

2. IMAGE WATERMARKING: THEORY OF IMPLEMENTEDAPPROACH

3. THE SYSTEM

4. HARDWARE IMPLEMENTATION

5. FPGA/STANDARD CELL/VPR ANALYSIS

6. WATTCH ANALYSIS

7. PROBLEMS FACED

8. CONCLUSION

9. REFERENCES

Introduction

Motivation

The recent growth of networked multimedia systems has increased the

need for the protection of digital media. This is particularly importantfor the protection and enforcement of intellectual property rights.Copyright protection involves the authentication of image ownership,and the identification of illegal copies of a (possibly forged) image.Techniques are needed to prevent the copying, forgery anunauthorized distribution of images and video. Without such methods,placing images or video sequences on a public network puts them atrisk of theft and alteration.


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The basic scenario is as follows: A user has created an electronicimage at some effort and expense, and wants to make it available on acommunications network. When unauthorized copies or forgeries of theimage appear elsewhere on the network, the user needs to prove thatthe image belongs to them. One also needs to determine if and by how

much the image has been changed from the original.

With the increase in the availability of digital data such as multimediaservices on the Internet, there is a pressing need to manage andprotect the illegal duplication of data. In the past few years many newtechniques and concepts based on data hiding or steganographyhave been introduced as a means for tamper detection in digitalimages and for image authentication. One approach involves addingan invisible structure to a host image to mark ownership of it. To beeffective, a watermark must be imperceptible within its host, discreteto prevent unauthorized removal, easily extracted by the owner and

robust to incidental and accidental distortions.

What is a Digital Image Watermark

A digital watermarkis a digital signal or pattern inserted into adigital image. Since this signal or pattern is present in each unalteredcopy of the original image, the digital watermark may also serve as adigital signature for the copies. A given watermark may be unique toeach copy (e.g. to identify the intended recipient), or be common to

multiple copies (e.g. to identify the document source). In either case,the watermarking of the document involves the transformation of theoriginal into another form. This distinguishes digital watermarking fromdigital fingerprinting, where the original file remains intact and a newcreated file 'describes' the original file's content.

Digital watermarking is also to be contrasted with public-keencryption, which also transform original files into another form. It is acommon practice nowadays to encrypt digital documents so that theybecome un-viewable without the decryption key. Unlike encryption,however, digital watermarking leaves the original image (or file)

basically intact and recognizable. In addition, digital watermarks, assignatures, may not be validated without special software. Further,decrypted documents are free of any residual effects of encryption,whereas digital watermarks are designed to be persistent in viewing,printing, or subsequent re-transmission or dissemination.


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The types of digital watermarks

Two types of digital watermarks may be distinguished, depending uponwhether the watermark appears visible or invisible to the casualviewer.

"Visible watermarks" are used in much the same way as their bondpaper ancestors, where the opacity of paper is altered by physicallystamping it with an identifying pattern. This is done to mark the papermanufacturer or paper type. One might view digitally watermarkeddocuments and images as digitally 'stamped'.

Invisible watermarks, on the other hand, are potentially useful as ameans of identifying the source, author, creator, owner, and distributoror authorized consumer of a document or image. For this purpose, theobjective is to permanently and unalterably mark the image so that thecredit or assignment is beyond dispute. In the event of illicit usage, the

watermark would facilitate the claim of ownership, the receipt ofcopyright revenues, or the success of prosecution.

Watermarking has also been proposed to trace images in the event oftheir illicit redistribution. Whereas past infringement with copyrighteddocuments was often limited by the unfeasibility of large-scaphotocopying and distribution, modern digital networks make large-scale dissemination simple and inexpensive. Digital watermarkingmakes it possible to uniquely mark each image for every buyer. If thatbuyer then makes an illicit copy, the illicit duplication may bconvincingly demonstrated.

Visible Vs Invisible watermarks

"Visible watermarks" are especially useful for conveying animmediate claim of ownership. The main advantage is that theyvirtually eliminate the commercial value of the document to a would-be thief without lessening the document's utility for legitimatauthorized purposes. A familiar example is in the video domain wherea logo is placed in a corner of the screen image.Invisiblewatermarks, on the other hand, are more of an aid in catching thethief than discouraging the theft in the first place. In general, "visible

watermarks" diminish the commercial value of a document or image,whereas invisible watermarks increase the likelihood of successfulprosecution. The invisible watermark may also act as a deterrent ifperpetrator is aware of their possible use.

Requirements of Watermarks


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To be effective in the protection of the ownership of intellectualproperty, the invisibly watermarked image should satisfy severalcriteria:

1. The watermark must be difficult or impossible to remove, at

least without visibly degrading the original image,2. The watermark must survive image modifications that arecommon to typical image-processing applications (e.g. scaling,dithering, cropping, compression),3. An invisible watermark should be imperceptible so as not toaffect the experience of viewing the image, and4. For some invisible watermarking applications, watermarksshould be readily detectable by the proper authorities, even ifimperceptible to the average observer. Such decidability withoutrequiring the original, un-watermarked image would benecessary for efficient recovery of property and subsequent

prosecution.

Techniques of watermarking

Several different methods enable watermarking in the spatial domain.The simplest is just to flip the lowest-order bit of chosen pixels. Thisworks well only if the image is not subject to any modification. A morerobust watermark can be embedded by superimposing a symbol overan area of the picture. The resulting mark may be visible or not,

depending upon the intensity value. Picture cropping, e.g., (a commonoperation of image editors), can be used to eliminate the watermark.Spatial watermarking can also be applied using color separation. Inthis way, the watermark appears in only one of the color bands. Thisrenders the watermark visibly subtle such that it is difficult to detectunder regular viewing. However, the mark appears immediately whenthe colors are separated for printing.

Watermarking can be applied in the frequency domain (and othertransform domains) by first applying a transform like the Fast FourierTransform (FFT). In a similar manner to spatial domain watermarking,

the values of chosen frequencies can be altered from the original. Theoriginal image is first transformed to the selected domain, and then arandomly generated (by some preferred distribution) watermark signalis superimposed upon a selected set of transform coefficients byadaptively modifying them. The watermarked image is obtained as aninverse transformation of the modified coefficients. The DiscreteCosine Transform (DCT) and the Discrete Wavelet Transform (DWT) arethe two most commonly used image transforms. For some algorithms,


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in order for the embedded watermark to withstand various forms ofimage processing and attack, the transform coefficients having thestrongest magnitudes are chosen for embedding the watermark signal.Since high frequencies will be lost by compression or scaling, thewatermark signal is applied to lower frequencies, or better yet, applied

adaptively to frequencies that contain important information of theoriginal picture. Since watermarks applied to the frequency domain willbe dispersed over the entirety of the spatial image upon inversetransformation, this method is not as susceptible to defeat by croppingas the spatial technique. However, there is more a tradeoff herebetween invisibility and decodability, since the watermark is in effectapplied indiscriminately across the spatial image.

There is a current trend towards approaches that make use ofinformation about the human visual system (HVS) to produce amore robust watermark. Such techniques use explicit information

about the HVS to exploit the limited dynamic range of the human eye.The perceptually invisible data hiding needs insertion of watermark inhigher spatial frequency of the cover image since human eye is lesssensitive to this frequency component. But in most of the naturalimages majority of the visual information are concentrated on thelower end of the frequency band. So the information hidden in thehigher frequency components might be lost after quantizationoperation of lossy compression.

Spatial Vs Frequency domain

Spatial watermarking is easy to implement from computational point ofview but too fragile to withstand large varieties of external attacks.Frequency or transformed domain approach offers robustwatermarking but in most cases implementation needs highecomputational complexity. Moreover the transform domain techniqueis global in nature (global within the block in block-based approach)and cannot restrict visual degradation of the cover image. But inspatial domain technique, degradation in image quality due to watermarking could be controlled locally leaving the region of interestunaffected.

IMAGE WATERMARKING: THEORY OF IMPLEMENTED APPROACH

Fragile Image Watermarking

A fragile watermark is a mark that is readily altered or destroyed whenthe host image is modified through a linear or nonlinear


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transformation. The sensitivity of fragile marks to modification leads totheir use in image authentication.Fragile watermarks are designed to detect every possible change inpixel values. In many schemes it can be shown that without the secretkey, the probability of a modification that will not be detected can be

related to a cryptographic element present in the scheme such as ahash function.

Desirable features of fragile marking system

1. Detect tampering: A fragile marking system should detect (withhigh probability) any tampering in a marked image.

2. Perceptual transparency: An embedded watermark should not bevisible under normal observation or interfere with thefunctionality of the image.

3. Detector should be able to locate and characterize alterations

made to a marked image: This includes the ability to locatespatial regions within an altered image which are authentic orcorrupt.

4. The watermark should remain detectable after image cropping.5. The marking key should be difficult to deduce from the detection

side information.6. The insertion of a mark by unauthorized parties should be

difficult.

The Image Authentication Framework

An owner embeds the mark into an original image. The marking key isused to generate the watermark and is typically an identifier assignedto the owner or image. The marked image is perceptually identical tothe original image under normal observation.

Fig.1 Watermark Embedding


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When a user receives an image, he uses the detector to evaluate theauthenticity of the received image. The detection process may requireknowledge of the marking key, the watermark and the original image.The detector is usually based on statistical detection theory whereby atest statistic is generated and from that test statistic the image is

determined to be authentic. If it is not authentic then it would bedesirable for the detector to determine where the image has beenmodified.

Fig.2 Watermark Detection

Algorithm

implemented forImage watermarkingand detection:Secure, Fragile

Authentication Watermark with Localization J. Fridrich et al

Background

Wongs scheme (P.Wong, N.Memon- Secret and Public Keyauthentication Watermarking Schemes that resist Vector QuantizationAttack: Proc. SPIE ,Security and Watermarking of multimedia

contents ,San Jose, Jan 2000) is one of the first public key spatialfragile watermarking algorithms. It works by partitioning the imageinto a number of blocks and inserting a digital signature authentication on a block-wise basis. In the embedding process, foreach block, a digital signature is computed after truncation of theLSBs. The signature for each block is then embedded in the LSBs inconjunction with a logo image. At the receiving end, the digitalsignature of each block is recomputed after truncation of LSBs and theblock is then authenticated by validating each block using embedded information in the LSBs of the block. Unauthenticatedblocks are assumed to have been manipulated, which provides the

mechanism for localization of image manipulations.

Algorithm Description

The algorithm implemented (Fragile Authentication Watermarking withlocalization J.Fridrich et al) differs from Wongs approach in theconstruction of the logo (watermark). The binary logo in this case is


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used to carry information about the block position and image indexand possibly other information relevant to the image such as itsoriginal dimensions, author ID etc. Furthermore, the block content willbe authenticated by creating a simply recognizable structure in eachbinary logo. (For eg. a 128 bit binary logo could comprise of 2

repetitions of a 64-bit stream)

Watermark Embedding

1. Divide the 8-bit grayscale image into 8x16 blocks (each blockcomprising of 128 8-bit pixels).

2. For each block, calculate the hash H of the MSBs of all 128pixels.

3. Xor the Hash with the Watermark bitstream (binary logo).4. Encrypt the xored output.5. Inserted the encrypted bitsream into the corresponding LSB

positions of the image block being watermarked.

Watermark Detection/Verification

1. Divide the 8-bit grayscale image into 8x16 blocks (each blockcomprising of 128 8-bit pixels).

2. For each block , calculate the hash H of the MSBs of all 128pixels.

3. Decrypt the bitstream corresponding to the LSB positions of theimage block under consideration.

4. Xor the decrypted bitstream with the Hash Function output.

5. Compare the output of the above step with the Watermark(Binary logo) bitstream.

6. If the 1st 64 bits of the generated watermark coincide with thenext 64 bits, it indicates that the block content is authentic.Swapping blocks and cropping can thus be readily detected.

Algorithms used for individual operations

Hashing: MD5 algorithm

In cryptography, MD5(Message-Digest algorithm 5) is a widely-used cryptographic hash function with a 128-bit hash value. As anInternet standard (RFC 1321), MD5 has been employed in a widevariety of security applications, and is also commonly used to checkthe integrity of files. The MD5 algorithm was designed by Prof. RonaldRivest at MIT in 1991 to replace the previous MD4 algorithm.

MD5 processes a variable length message into a fixed-length output of


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128 bits. The input message is broken up into chunks of 512-bit blocks;the message is padded so that its length is divisible by 512. Thepadding works as follows: first a single but, 1, is appended to the endof the message. This is followed by as many zeros as are required tobring the length of the message up to 64 bit less than a multiple of

512. The remaining bits are filled up with a 64-bit integer representingthe length of the original message.

The main MD5 algorithm operates on a 128-bit state, divided into four32-bit words, denoted A, B, C, and D. These are initialized to certainfixed constants. The main algorithm then operates on each 512-bitmessage block in turn, each block modifying the state. The processingof a message block consists of four similar stages, termed rounds;each round is composed of 16 similar operations based on a non-linearfunction F, modular addition, and left rotation. Figure 1 illustrates oneoperation within a round. There are four possible functions F, a

different one is used in each round.

Denote the XOR, AND, OR and NOT operations respectively.s denotes a left bit rotation by s places; s varies for each operation,denotes addition module 232.

Fig.3 One MD5 operation --- MD5 consists of 64 of these operations,grouped in four rounds of 16 operations. F is a non linear function; onefunction is used in each round. Mi denotes a 32-bit block of themessage input, and Ki denotes a 32-bit constant, different for eachoperation.
http://en.wikipedia.org/wiki/Image:Boxplus.pnghttp://en.wikipedia.org/wiki/Image:Lll.png


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Pseudo code for the MD5 algorithm

//Define r as the following

var int[64] r,k;r[0:15] := {7,12,17,22,7,12,17,12,17,22,7,12,17,22}r[16:31] := {5,9,14,20,5,9,14,20,5,9,14,20,5,9,14,20}r[32:47] := {4,11,16,23,4,11,16,23,4,11,16,23,4,11,16,23}r[48:63] := {6,10,15,21,6,10,15,21,6,10,15,21,6,10,15,21}

//Use binary integer part of the sines of integers as constants:

for i from 0 to 63

k[i] := floor(abs(sin(i+1))x2^32)

//Intitialize variable:

var inth0 := 0x67452301

var int h1 := 0xEFCDAB89

var int h2 := 0x98BADCFE

var int h3 := 0x10325476

// Pre-processing
http://en.wikipedia.org/wiki/Image:MD5.png


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append "1" bit to messageappend "0" bits until message length in bits = 448(mod 512)append bit length of message as 64-bit little-endian integer tmessage

//Process the message in succesive 512-bit chunks:

foreach 512-bit chunck of messagebreakchunk into sixteen-bit-little-endianwords w(i), 0


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h2:=h2+ch3:=h3+d

var int digest:=h0 append h1 append h2 append h3 //(expressed aslittle-endian)

Public Key Cryptosystem: Encryptor and Decryptor algorithm(RSA)

Public key cryptography is a form of cryptography which generallyallows users to communicate securely without having prior access to ashared secret key. This is done by using a pair of cryptographic keys,designed as public key and private key, which are relatedmathematically.

In cryptography, RSA is an algorithm for public key encryption. It wasdescribed in 1977 by Ron Rivest, Adi Shamir and Len Adleman at MIT.RSA invloves 2 keys: public key and private key (a key is a constantnumber later used in the encryption formula) .The public key is knownto everyone and is used to encrypt messages. These messages canonly be decrypted by use of the private key. In other words, anyonecan encrypt a message, but only the holder of a private keycanactually decrypt the message and read it.

The following steps are used to generate a public key and a privatekey:

1. Choose two large prime numbers p and q such that p is not equalto q , randomly and independently of each other.

2. Compute n = pq3. Compute the quotient (n) = (p-1)(q-1)4. Choose an integer e such that 1


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d, the private exponent (also called decryption constant which mustbe kept secret)

Encrypting messages : The cipher text corresponding to messagem is given as c = me mod n

Decrypting messages : Message m is recovered from c as m= cd

mod n

A working example: Let

p = 61 first prime number

q = 53 second prime number

n = pq =3233

modulus (to be made public)

e = 17 public exponent (to be made public)d =2753

private exponent (to be kept secret)

The public key is (e,n) and the private key is d. The encryption functionis:Encrypt(m) = me mod n = m17 mod 3233 where m is the message.The decryption function is:Decrypt(c) = cd mod n = c2753 mod 3233 where c is the cipher text.

To encrypt the plain text 123 we calculate

Encrypt(123) = 12317 mod 3233 = 855

To decrypt the cipher text 855, we calculateDecrypt(855) = 8552753 mod 3233 = 123

THE SYSTEM

Fig.4 Encoder Block Diagram

8-BIT GRAYSCALE IMAGE

128

pixels

128x8 bit Register Bank

Data[7:0]

Reg_msb[127:0]

Hashing_function

Encryptor

XORWatermark_Key

Reg_lsb[127:0]

Reg_enable Clock

msb_enable

lsb_enable

clock

reset

Msg_out_valid

ready

clock

E[4:0]

Dataready_in

Dataready_out


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Encoder (Watermark Embedder) operation

1. The entire 8-bit grayscale image is divided into blocks of 16x8(=128) pixels. For each of these image blocks the watermarkinsertion is carried out sequentially.

2. The 128 pixel block is loaded onto a register file 1 pixel at a timewith a reg_enable flag used to indicate every time 8-bits of apixel are successfully loaded. The register file comprises of abank of 128 8-bit registers to store the corresponding pixels. Italso comprises of 2 128-bit registers namely reg_lsb andreg_msb.

reg_msb is used to hold the 128 MSBs of the pixels that aregoing to be embedded with the watermark. reg_lsb is used tohold the watermark encoded bit stream that is ultimately loadedonto the 128 LSBs of the corresponding pixels.

3. Every time the register reg_msb gets loaded with data, theflag msb_enable goes high. This flag correspond to the signalmsg_in_valid of the Hasher. The Hasher is reset before everyhashing operation. The msg_in_width is set to 128-bits for the


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entire length of operation. When msg_in_valid goes high, thehasher takes in the 128 bit stream stored in reg_msb throughthe msg_in[127:0] port and generates a 128 bit hashedstream using the MD5 algorithm which is output to the portmsg_output[127:0]. As soon as the hashed output is

obtained at the above mentioned port, the msg_out_validsignal goes high indicating completion of the hash operation.Simultaneously, the ready signal also goes high indicating thatthe hasher is ready to receive the next stream of 128-bit data.

4. When the msg_out_valid signal goes high, the hasher outputis taken and XORed with the Watermark bitstream. As soon asthe computation is performed , the dataready_in signal of theDecryptor is made high.

5. When the dataready_in signal of the Decryptor goes high itloads the XOR output stream through the port datain[127:0].The encryption exponent (E) is input. (The same key is used for

the entire image). The Encryptor encrypts 16-bits of data at atime using the RSA algorithm for encryption. When the Encryptorcompletes its operation it makes dataready_out signal highand outputs the data to the port dataout[127:0].

6. The dataready_out signal corresponds to the lsb_enablesignal of the register file. When lsb_enable goes high theregister file takes the data from the port dataout[127:0] andloads it into the register reglsb. The bitstream present inreglsb is then used to replace the LSBs of pixels of the imageblock under consideration. (replacing bits in the 128 LSpositions)

7. The watermark embedded image block is then stored back at thesame location and the whole process begins again.

Fig.5 Decoder Block Diagram

8-BIT GRAYSCALE IMAGE

128

pixels

128x8 bit Register Bank

Data[7:0]

Reg_msb[127:0]

0

Hashing_function

Decryptor

XOR

Watermark_Key

Reg_lsb[127:0]

Reg_enable Clock

msb_enable

lsb_enable

clock

reset

Msg_out_valid

ready

clock

D[7:0]

Dataready_in

Dataready_out

XOR

Detection_result (all 0's indicate

MATCH)


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Decoder (Watermark Extractor) operation

1. The entire 8-bit grayscale image is divided into blocks of 16x8(=128) pixels. For each of these image blocks the watermarkextraction and detection is carried out sequentially.

2. The 128 pixel block is loaded onto a register file 1 pixel at a timewith a reg_enable flag used to indicate every time 8-bits of apixel are successfully loaded. The register file comprises of abank of 128 8-bit registers to store the corresponding pixels. It

also comprises of 2 128-bit registers namely reg_lsb andreg_msb that are used to store the LSBs and MSBs of thepixels.

3. Every time the registers reg_lsb and reg_msb get loadedwith their corresponding data, their respective flagslsb_enable and msb_enable go high. These flagscorrespond to the signals msg_in_valid and dataready_inof the Hasher and Decryptor functions respectively (within thedecoder).

4. The Hasher is reset before every hashing operation. Thmsg_in_width is set to 128-bits for the entire length of

operation. When msg_in_valid goes high, the hasher takes inthe 128 bit stream stored in reg_msb through themsg_in[127:0] port and generates a 128 bit hashed streamusing the MD5 algorithm which is then output to the portmsg_output[127:0]. As soon as the hashed output isobtained at the above mentioned port, the msg_out_validsignal goes high indicating completion of the hash operation.


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Simultaneously, the ready signal also goes high indicating thatthe hasher is ready to receive the next stream of 128-bit data.

5. When the dataready_in signal of the Decryptor goes high itloads the contents of reglsb register through the portdatain[127:0]. The decryption exponent is input. (The same

key is used for the entire image). The decryptor decrypts 16-bitsof data at a time using the RSA algorithm.When the Decryptorcompletes its operation it makes dataready_out signal highand outputs the data to the port dataout[127:0].

6. When both msg_out_valid and dataready_out are high,the outputs of the Hasher and the Decryptor i.e. msg_outputand dataout are XORed . The resultant bitstream representsthe extracted watermark of the particular image block. If itcomprises of identical bitvalues in its LSB and MSB halves, thatindicates an uncorrupted watermark.

7. The extracted watermark is then compared with the watermark

bitstream originally embedded by XORing the 2 bitstreams. Theresultant bitstream represents the comparison result. A streamof all zeroes indicates a perfect match and correct detection.

8. Once the detection is done the signal decout_ready goes highindicating the decoder is ready to decode the next block ofimage data.

9. The whole process begins again with the loading of the nextblock of image data onto the register file.

HDL IMPLEMENTATION

The modules for the Encoder and the Decoder were written in Verilogand their functional verification was done using MODELSIM 6.0a.

Fig.6 A Functional verification of the Encryptor

Fig.6 B Functional verification of the Decryptor

Fig.6 C Functional verification of the Hasher

Fig.6 D Functional verification of the Register File (decoder)

Fig.6 E Functional verification of the Encoder

Fig.6 F Functional verification of the Decoder
http://opt/scribd/conversion/tmp/scratch6657/encryptor_image.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decryptor_image.JPGhttp://opt/scribd/conversion/tmp/scratch6657/hasher-sim.JPGhttp://opt/scribd/conversion/tmp/scratch6657/regfile_dec_image.JPGhttp://opt/scribd/conversion/tmp/scratch6657/encoder_1_sim.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decoder_image.JPGhttp://opt/scribd/conversion/tmp/scratch6657/encryptor_image.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decryptor_image.JPGhttp://opt/scribd/conversion/tmp/scratch6657/hasher-sim.JPGhttp://opt/scribd/conversion/tmp/scratch6657/regfile_dec_image.JPGhttp://opt/scribd/conversion/tmp/scratch6657/encoder_1_sim.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decoder_image.JPG


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FPGA/STANDARD CELL ANALYSIS

FPGA

The HDL designs for both the Watermarking Encoder and Decoderwere Placed and Routed using the QuartusII software suite for theAltera DE2 board. The following results were obtained after running theplacement, power and timing analyzer.

Modules\Analysi

s

Area

Interconnec

t Usage (%)

Logicelements

(Max:10345)

DSP

blocks

I/O pins

(Max:426)

T_setu

p (ns)

Encoder 6356 48 399 45 2.17

Decoder 6343 48 372 51 2.789

Hasher 3121 0 269 33 11.219

Encryptor 3209 48 264 35 48.204

Decryptor 3210 48 267 33 46.852

Register FileEncoder

0 0 256 17 1.03

Register FileDecoder 0 0 256 14 1.1

Analysis Summary

For all the modules, even though the device I/O utilization was veryhigh, the logic utilization was relatively low. Also, we see that thehasher module consumes the maximum amount of power as itrepeatedly operates on 128 bit data. The encryptor and the decryptormodules were found to be the most sensitive to setup time violations.

STANDARD CELL BASED

The modules of the encoder and decoder were in Behavioral Verilogformat. These files were converted into Structural Verilog format usinga perl script. The Verilog netlist was then verified using SynopsysDesign Compiler. The verified design was then technology mapped toa set of gates with a maximum fan-in of three. The Verilog netlist was


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converted into standard cells using Synopsys Design Analyzer.Analysis was done on the area, power and timing of these standardcells.

Modules\Analysis

Area Po

#Ports

#Nets

#Cells

Total CellArea (um2)

CellInternalPower

NetSwitching Power

Encoder 527 10661 14562 1820151.87 38.9 W 14.3 W

Decoder 526 10403 13932 1760883.4 34.8 W 12.5 W

Hasher 269 9790 9491 857681.93 17.5 W 8.7 W

Encryptor 264 1265 381 989069.875 14.6 W 5.32 W

Decryptor 267 1269 369 929877.43 11.2 W 4.88 W

Register FileEncoder 260 261 131 34418.132 6.4 W 3.10 W

Register FileDecoder

261 273 127 38808.273 6.9 W 4.85 W

Standard Cell Layout Diagrams

Fig7a. Register File (Encoder)

Fig7b. Hasher

Fig7c. Encoder

Fig7d. Encryptor

Fig7.d Decryptor

Fig7.e Decoder

Fig7.f Register File (Decoder)

All the images above are the GDSII layouts of the individual modules

and the encoder/decoder as a whole. The above layouts were importedinto CoolViewPlus v7.0 for better clarity while displayed here.

Analysis Summary

As compared to the FPGA based approach, there was a markedincrease in power consumption in the Standard Cell based approach(orders of magnitude). Since the Design Compiler tool works on 250nm
http://opt/scribd/conversion/tmp/scratch6657/regfile.JPGhttp://opt/scribd/conversion/tmp/scratch6657/regfile.JPGhttp://opt/scribd/conversion/tmp/scratch6657/regfile.JPGhttp://opt/scribd/conversion/tmp/scratch6657/hasher.JPGhttp://opt/scribd/conversion/tmp/scratch6657/encoder.JPGhttp://opt/scribd/conversion/tmp/scratch6657/encrypt.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decrypt.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decoder.JPGhttp://opt/scribd/conversion/tmp/scratch6657/regfile2.JPGhttp://opt/scribd/conversion/tmp/scratch6657/regfile.JPGhttp://opt/scribd/conversion/tmp/scratch6657/hasher.JPGhttp://opt/scribd/conversion/tmp/scratch6657/encoder.JPGhttp://opt/scribd/conversion/tmp/scratch6657/encrypt.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decrypt.JPGhttp://opt/scribd/conversion/tmp/scratch6657/decoder.JPGhttp://opt/scribd/conversion/tmp/scratch6657/regfile2.JPG


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based library, the leakage power is always a negligible fraction of thetotal power consumption.

VPR ANALYSIS

The Verilog netlist obtained from above was converted into a gate levelnetlist. The gate level netlist was a BLIF netlist. The conversion wasdone using ABC (A System for Sequential Synthesis and Verification,developed by Berkeley Logic Synthesis and Verification Group), a logicminimization tool. These blif files were then used for VPR basedPlacement and Routing analysis.

Circuit:#BLE/cluster

:#

Inputs/cluster

Array Size( # of

CLBs)

OptimumChannelwidth

(W-detailed)

# oftransistorsPer logic

cluster

Total# of logic

transistors

Encoder:4:10 32 x 32 34 1432 1466368

Encoder:1:4 63 x 63 13 205 813645

Decoder:4:10 31 x 31 27 1398 1343478

Decoder:1:4 60 x 60 11 198 712800

Routing area in terms of no. of min. width transistors asreported by VPREncoder: 4:10

Routing area (in minimum width transistor areas):Assuming no buffer sharing (pessimistic). Total: 3.34263e+06, Per CLB:6318.78Assuming buffer sharing (slightly optimistic). Total: 2.26332e+06, PerCLB: 4278.48

Encoder:1:4Routing area (in minimum width transistor areas):Assuming no buffer sharing (pessimistic). Total: 6.36335e+06, Per CLB:3286.85Assuming buffer sharing (slightly optimistic). Total: 4.31675e+06, Per

CLB: 2229.73

Decoder: 4: 10Routing area (in minimum width transistor areas):Assuming no buffer sharing (pessimistic). Total: 2.71946e+06, Per CLB:3730.40Assuming buffer sharing (slightly optimistic). Total: 2.06824e+06, PerCLB: 2837.09


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Decoder: 1: 4Routing area (in minimum width transistor areas):Assuming no buffer sharing (pessimistic). Total: 7.88719e+06, Per CLB:2704.80

Assuming buffer sharing (slightly optimistic). Total: 5.37527e+06, PerCLB: 1843.37

For both encoder and decoder circuits the cluster size of 4 with 10distinct inputs was found to be more area efficient as compared to thecluster size of 1 with 4 distinct inputs. This is because in a clusteredFPGA many nets are completely absorbed within the clusters and theirrouting is taken care of by the intra-cluster multiplexers.

WATTCH ANALYSIS

Background

WATTCH is an architectural simulator that estimates CPU powerconsumption. The power estimates are based on a suite parametrizable power models for different hardware structures and onper-cycle resource usage counts generated through cycle levesimulation. The power models have been integrated into the SimpleScalar architectural simulator.

A modified version of SimpleScalars sim-outorderis used to collectresults by WATTCH. SimpleScalar provides a simulation environmentfor modern out-of-order processors with 5-stage pipelines: fetch,decode, issue, writeback and commit. Speculative execution is alsosupported. Separate banks of 32 integer and floating point registersmake up the architected register file and are only written on commit.The power oriented modifications provided by WATTCH (whosemodules are integrated within SimpleScalar) track which units are


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accessed on each cycle and how and compute the power valuesassociated with those units accordingly.These power modules have been verified against industrial circuits andhave been found to be within 10% for low level capacitance estimates.

Experimental Setup

To evaluate the power-performance of the Watermarking algorithm(used for FPGA and Standard Cell based implementation in this project)in a general purpose processor environment WATTCH was used tosimulate the algorithm. Similar simulations were performed usingbinaries of three other watermarking algorithms namely HartleyTransform based, Fast Cosine Transform based and Sub-band DiscreteCosine Transform based (All developed by Vassilis Fotopoulis: signalprocessing 98, European Signal Processing Conference 00). Despitethe availability of source codes of a lot many other watermarking

algorithms, the analysis was restricted to the above algorithms due tothe high level of complexity involved in generating PISA binaries(requisite for SimpleScalar simulation) for them. The GNU tool chainused for generating the PISA binaries for SimpleScalar is very selectivein the sort of commands it would allow for compilation unfortunately most of the algorithms could not be compiled using thistool chain.

Simulation Results

Power dissipated per simulation cycle in milli-watts by

Encoders

HartleyTransfor

m

FastCosine

Transform

Sub-bandDCT

WM_Algo

BranchPrediction

Unit0.4988 0.5051 0.5671 0.301

ResultBusUnit 0.4601 0.4666 0.6034 0.613

InstructionCache Unit

0.6547 0.6674 0.7015 0.661

ALU Unit 2.299 2.315 2.61 1.95


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Hartley

TransformFast

Cosine

Transform

Sub-band

DCTWM_algo

Branch Prediction Unit

ResultBus Unit

Instruction Cache UnitALU Unit

0

0.5

1

1.5

2

2.5

3

Pow er dissipated per simulation c ycle in milli-watts by W atermark Enc

WATTCH)

Branch Predicti

ResultBus Unit

Instruction Cac

ALU Unit

Performance Penalty

HartleyTransfor

m

Fast

CosineTransfor

m

Sub-bandDCT

WM_Algo

#ofsimulation

cycles15158 17250 20898 15230


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Total simulation time of the Encoders(# of SIMPLESCALAR simulation cycles)

0

5000

10000

15000

20000

25000

Hartley Transform Fast Cosine

Transform

Sub-band DCT WM_algo

#ofsimulationcycles

# of simulation c

Power dissipated per simulation cycle in milli-watts byDecoders

Hartley

Transform

FastCosine

Transform

Sub-

bandDCT

WM_algo

BranchPrediction

Unit0.5034 0.6152 0.6672 0.415

ResultBusUnit

0.4004 0.412 0.4887 0.412

InstructionCache Unit

0.7124 0.7328 0.79 0.654

ALU Unit 3.65 3.67 3.92 2.98


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Hartley

TransformFast

Cosine

Transform

Sub-band

DCTWM_algo

Branch Prediction UnitResultBus Unit

Instruction Cache Unit

ALU Unit

0

0.5

1

1.5

2

2.5

3

3.5

4

Pow er dissipated per simulation cycle in milli-watts by Watermark Decoder (on

WATTCH)

Branch Prediction

ResultBus Unit

Instruction Cache

ALU Unit

Performance Penalty

HartleyTransfor

m

FastCosine

Transform

Sub-band

DCT

WM_algo

# ofsimulation

cycles16240 19310 21650 16348


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Total simulation time of Decode rs (# of simulation cycles on SIMPLESCALAR)

0

5000

10000

15000

20000

25000

Hartley Transform Fast Cosine

Transform

Sub-band DCT WM_algo

# of simulation c cles

Algorithm

# of simulation c

Analysis Summary

Expectedly, the Watermarking algorithm implemented by us in thisproject (as against the other algorithms) did much better in terms ofaverage power dissipation by the 4 most power hungry resource units(top 4 max. total power dissipation units). The power benefits did not

incur a big increase in the simulation time. The appreciable differencein the power values were anticipated since any spatial watermarkingalgorithm is much less computationally intensive as compared to afrequency domain watermarking algorithm and thus exercises theresource units much lesser.

PROBLEMS FACED

The conversion of Behavioral to Structural Verilog was very tedious dueto the selectiveness of the Design Compiler library. Generating PISAbinaries for existent and our image watermarking source code wasextremely difficult.

CONCLUSION


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Documents

DIGITAL IMAGE WATERMARKING SYSTEM