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Digital Engineering Laboratory Course Introduction & FPGA ... CLB - Configurable Logic Block •See Figure 5: Detailed View of Virtex Slice •Logic Function Implementation –2 Function

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  • 7/13/2009 1

    Digital Engineering Laboratory

    Course Introduction & FPGA

    Concepts and Design

    ECE 554

    Department of Electrical and

    Computer Engineering

    University of Wisconsin - Madison

  • 2009-7-13 2

    Instructors and Course Website

    • Nam Sung Kim, [email protected] – Office: 4615 Engineering Hall

    – Office hours: Tue,Wed,Thur - 2:00 to 3:00 PM

    Additional hours by appointment

    • Chunhua Yao, [email protected] – Teaching Assistant for Labs

    – Office hours are assigned lab hours – 3:30 to 6:30 Tuesday and Thursday

    • The course website and wiki are at:

    http://homepages.cae.wisc.edu/~ece554/new_website/

    https://cgi.cae.wisc.edu/~ece554/pmwiki/pmwiki.php

    mailto:[email protected] http://homepages.cae.wisc.edu/~ece554/new_website/ https://cgi.cae.wisc.edu/~ece554/pmwiki/pmwiki.php

  • 7/13/2009 3

    Course Objectives

    • Deal with problems and solutions associated with many aspects of a large digital design project

    • Work effectively as a member of a moderate- sized team

    • Use contemporary commercial design tools

    • Use programmable user-defined devices (FPGAs) for rapid prototyping

    • Learn to live on Pizza and get by on very little sleep  at least during the last part of the course.

  • 7/13/2009 4

    Prerequisites and Location • ECE 351 – Digital Logic Laboratory

    • ECE/CS 552 – Introduction to Computer

    Architecture

    • ECE 551 - Digital System Design and

    Synthesis (strongly recommended)

    • Laboratory: 3628 Engineering Hall

    • Lecture: 3444 EH

    • Lectures and Reviews during Lab Hours:

    3444 EH

  • 7/13/2009 5

    Access to the lab

    • Laboratory: 3628 Engineering Hall

    The lab access is password protected and

    you will have access to the lab 24/7

    • Password

  • 2009-7-13 6

    Course Overview Grading

    • 15% Miniproject – due 2/5

    – Design a Special Purpose Asynchronous

    Receiver/Transmitter (team of 2)

    • 20% Bench Exam – on 2/26

    – Designed to test your understanding of Design

    Specifications, Verilog, Debugging, Lab Environment,

    etc. (individual)

    • 65% Project – demos 5/5, report 5/14

    – Design, implement, test, and program a general or

    special purpose digital computer that emphasizes

    some particular features (team of 4 to 6)

  • 7/13/2009 7

    Miniproject

    • For the miniproject, you will – Design a Special Purpose Asynchronous

    Receiver/Transmitter (SPART) and its testbench in

    Verilog/VHDL and use EDK toolset

    – Simulate the design to ensure correct performance

    – Download the design and associated files and

    demonstrate correct functionality

    – Preparing a report on your design

    – https://cgi.cae.wisc.edu/~ece554/pmwiki/pmwiki.php?

    n=Main.MiniProject

    https://cgi.cae.wisc.edu/~ece554/pmwiki/pmwiki.php?n=Main.MiniProject https://cgi.cae.wisc.edu/~ece554/pmwiki/pmwiki.php?n=Main.MiniProject

  • 7/13/2009 8

    Midterm Bench Exam • You will be given a set of specifications for a small

    system along with Verilog code for some pre-designed

    modules for the system.

    • You will be expected to:

    – Understand the specifications

    – Understand the Verilog code provided

    – Write one or more Verilog modules

    – Debug one or more Verilog modules

    – Simulate one or more modules and the entire system

    – Synthesize and implement the design

    – Download, test, and demonstrate the design on the

    FPGA board

  • 7/13/2009 9

    Project • Design, simulate, synthesize, test, download and

    demonstrate a non-trivial computer with an original

    instruction set architecture (ISA)

    • Four key requirements

    – It must be an original ISA (somewhat negotiable)

    – It must be non-trivial

    – It must be tractable - everything takes at least twice as

    long as you expect

    – It must interface through the serial port with the

    terminal emulator on the lab workstations (negotiable)

    • Often has significant software component and utilizes

    FPGA board interfaces

  • 2009-7-13 10

    Project Milestone • Several major milestones

    – Project team selection – each team of 5 or 6 (2/3)

    – Project proposal presentation (2/12)

    – Architecture review presentation (2/19)

    – ISA report due (2/24)

    – Microarchitecture review presentation (3/24)

    – Testing and demo review presentation (4/7)

    – Several progress reviews (see syllabus)

    – Project demonstrations (5/5)

    – Project report due (5/14)

    • For details see:

    https://cgi.cae.wisc.edu/~ece554/pmwiki/pmwiki.php?n=Main.Milestones

    https://cgi.cae.wisc.edu/~ece554/pmwiki/pmwiki.php?n=Main.Milestones

  • 7/13/2009 11

    Major Lab Enhancement

    • We have done a major enhancement to the

    ECE554 lab recently, bear with us for version

    updates

    – All new computers and monitors

    – All new FPGA boards and updated digital design

    software

    – Overall objectives of the lab will stay the same

    – Some additional changes may happen this semester

    – We will try to make the transition as smooth as

    possible – thanks to Mitch

    • Go over the syllabus

  • 7/13/2009 12

    FPGA Concepts and Design

    • CMOS IC design alternatives

    • RAM cell-based FPGA uses

    • The Xilinx Virtex Series FPGA technology

    • The Xilinx Integrated Software Environment (ISE)

    design process

  • 7/13/2009 13

    CMOS IC Design Alternatives

    STANDARD

    IC

    FULL

    CUSTOM

    SEMI-

    CUSTOM

    FIELD

    PROGRAM-

    MABLE

    STANDARD

    CELL

    GATE ARRAY,

    SEA OF GATES CPLD

    ASIC

    FPGA

    • Field Programmable Gate Array (FPGA) – a hardware

    device with programmable logic, routing, memory, and I/O

  • 7/13/2009 14

    RAM Cell-Based FPGA Uses

    • Prototyping gate array, standard cell,

    or full custom integrated circuits (ICs)

    • Prototyping complete systems

    • Implementing “hardware simulation”

    • Replacing ICs

    • Providing multifunction reconfigurable

    system ICs

    • Hardware accelerators

  • 7/13/2009 15

    • Primary Reference: – On-Line Xilinx Data Sheet DS003 (v.2.5, April 2,

    2001) - http://www.xilinx.com/partinfo/ds003.pdf

    • Figure 1: Virtex Architecture Overview – IOBs - Input/Output Blocks

    – CLBs - Configurable Logic Blocks • Function generators, Flip-Flops, Combinational Logic, and

    Fast Carry Logic

    – GRM - General Routing Matrix

    – BRAMs - Block SelectRAM (configurable memory)

    – DLLs - Delay-Locked Loops for clock control

    – VersaRing - I/O interface routing resources

    Xilinx Virtex FPGA Architecture

    http://www.xilinx.com/partinfo/ds003.pdf http://www.xilinx.com/partinfo/ds003.pdf

  • 7/13/2009 16

    Figure 1- Virtex Architecture Overview

  • RAM-based FPGA

    7/13/2009 17

    Xilinx XC4000ex

  • 7/13/2009 18

    • Logic configured by values stored in SRAM cells

    – CLBs implement logic in SRAM-stored truth tables

    – CLBs also use SRAM-controlled multiplexers

    – Routing uses “pass” transistors for making/breaking connections between wire segments

    – Block RAMs allow programmable memories with configurable widths (1, 2, 4, 8, or 16 bits)

    Virtex FPGA Architecture

  • Look-up Table Based Logic Cell

    7/13/2009 19

    Out

    ln1 ln2

    M e m

    o ry

    In Out

    00 00

    01 1

    10 1

    11 0

  • Programmable Routing

    7/13/2009 20

  • 7/13/2009 21

    Table 1 – Virtex FPGA Family Members

    • We use the XCV800 device

    • 0.22 micron, five-layer metal process

  • 7/13/2009 22

    • See Figure 2: Virtex Input/Output Block – Separate signals for input (I), output (O), and output

    enable (T)

    – Three storage elements function as D flip-flops or latches with clock enable (CE) and set/reset (SR)

    – I/O pins can connect directly to internal logic or through the storage element

    – Programmable input delay

    – 3-state output buffer

    – I/O pad can use pull-up, pull-down, or weak keeper

    – Supports a wide range of voltages

    IOB - Input/Output Block

  • 7/13/2009 23

    Figure 2: Virtex Input/Output Block

  • 7/13/2009 24

    CLB - Configurable Logic Block

    • See Figure 4: 2-Slice Virtex CLB

    • Each slice contains two logic cells (LCs) and consists of

    – 2 4-input look-up tables (LUTs)

    – 2 D flip-flops/latches

    – Fast carry and control logic

    – Three-state drivers

    – SRAM control logic

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