Digital Electronics_Lab Manual

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Digital Electronics Lab Manual

AIR UNIVERSITYDepartment of Electrical Engineering

Digital Electronics

(Lab Manual)


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Digital Electronics Lab Manual

DIGITAL ELECTRONI CS

Lab Manual

Name: _____________________

Roll No: _____________________

Class: _____________________


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CONTENTS

Lab Title Page #1 Introduction to PSpice 1

2 NMOS Inverter 4

3 CMOS and Pseudo NMOS 9

4 NAND and NOR 14

5 Dynamic and Domino 18

6 SR Flip Flop 23

7 SRAM Cell 26


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PREFACE

This lab manual is created in order to facilitate the learning of the course of

Digital Electronics. Most of the contents read in the theory of the subject will be

covered using the software simulations.

The software used is PSpice. It is very handy software for the simulation of the

Digital Electronics circuit. The DC simulation in the software has no

comparison. Also, the practical aspects of the circuits that cant be handled

when dealing with the hardware can be easily compensated in the software.

Most of the digital electronics circuits required match pair which are costly.

This is compensated by the PSpice. One can easily choose the sizing. Hence the

lab and the software must be necessarily covered in order to teach the effect of

the circuits covered in the course.

The course can lay a good foundation to the VLSI circuits. VLSI is being

largely used in the industry for the Integrated circuit making. Clear concepts in

the digital electronics course will also lead to the better concepts in VLSI.


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GENERAL INSTRUCTIONS

COURSE DESCRIPTION:Digital Electronics is a basic electrical engineering laboratory course. It laysimportant theoretical foundations of electrical engineering and covers techniques

used in VLSI.

NOTES AND TEXTBOOKS:Lab Manual is required..

Reference BooksMicroelectronic Circuits by Sedra/Smith.

LAB NOTEBOOKS:You are required to maintain a lab (engineering) notebook. In a lab notebook,

experimentation is recorded as it is done. (This means, don't take data on scrap paper and

recopy it into your lab notebook at home.) The lab notebook is discussed in detail in the

section on lab notebooks.

The lab instructor will collect and grade your lab notebook several times during thesemester. Lab work should be completed at the time of the experimentation; however,

most people will require some time outside the lab to complete the analysis and write up.

We feel that after a week or so, going back and trying to analyze and write up

experimentation is of little value and a waste of your time; therefore, all work must be

complete in your lab notebook within one week of the experimentation. After that, you

should be working on the next week's laboratory work and not going back. After one

week, your lab instructor may grade without notice any experimentation in your lab

notebook (missing work counts as zero).

You are required to date and sign each entry in your lab notebook.


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PREPARATION AND PLANNING:

Some preparation is necessary before coming to lab. Before you start an experiment,

make sure you read and understand the lab. This should be done BEFORE coming to

l a b . Good experimentation requires adequate planning. You should have a good idea

what your objectives are, how you plan on accomplishing them, and what the results are

that you expect to get.

An experiment will usually run more smoothly if you have some idea what the outcome

of the experiment should be beforehand. Errors in procedure can often be identified

and corrected if you can see that the result doesn't make sense.

QUIZZES:

There will be a quiz in almost every lab session. The quizzes will normally be entrance quizzes, that is, they will be conducted at the start of the lab. You should be well

prepared for the quiz and should make sure that you read and understand the theory

relative to the lab. In fact, the quizzes will test you on your theoretical proficiency. The

students will always be intimated about the quiz one week before it is scheduled.

ATTENDANCE:Experiments are normally performed in your assigned laboratory section.If for any

reason, such as illness, you perform the lab with another section, you should have that lab

instructor sign and date your lab notebook at the end of the l a s t entry, f o r that lab.

(This w ill serve as verification that you have attended a lab section for that lab.)

Attendance and completion of a l l laboratory work is required.

The recitation and pre-lab by the instructor is normally at the beginning of the lab;

therefore, it is essential to be in lab on time even though the remaining time will usually

be unstructured.

CHEATING AND PLAGIARISM:

Cheating and plagiarism are inconsistent with the professionalism required of anengineer. We therefore take a strict action against this in the electrical engineering

laboratory courses. Both are grounds for an F in the course.


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LAB NOTEBOOK

You are required to maintain a lab (engineering) notebook in the electrical

engineering laboratory courses.

Lab notebooks are customarily used in engineering as permanent records ofexperimentation (or engineering) done. In engineering and research, it is often necessary

to either go back to work done at an earlier date or have records to prove that you

invented something being patented.

Your lab notebook should be a permanent record of your experimentation (or

engineering). You are required to make entries in it as you do the experimentation (or

engineering) and analyze the results.

OUTER COVER:The outer cover should have course name, your name, roll number, discipline, class,section and semester on it.

FIRST PAGE:The first page should be used as an index or table of contents. List all experiments on it.

RECORDING EACH LAB:Each lab should contain the following parts: (The order may vary for different labs, and

some of the parts listed may not apply to all labs.)

1. Title: This should include the title of the lab and the lab n umb e r .

2. Objectives: Briefly state the purpose of the experiment and the concepts to beinvestigated.

3. Equipment list: List all critical equipment and instruments used. Include themanufacturer's name, model number, and serial number (or laboratory number)

should not be listed. Equipment can be listed either in an initial list or as used. You

should have enough information to go back and repeat the lab with the sameequipment.

4. Block diagrams you have to draw block diagrams of all the experiments that youwill implement(This will almost always save you time in the end since without a good

design diagram to work from, you will make more mistakes, have more difficulty

taking data, and have more difficulty troubleshooting your circuits.)

5. Data: Data should be tabulated in vertical columns. Data tables should be labeled.Listing the units at the top of a column i s usually preferred to repeating the same unit

with each data entry.


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6. Calculations: Include sample calculations of each type. (Include enough to showhow the calculations were done; however, do not use your notebook as a worksheet.)

7. Graphs: Include curves of data, wave shape diagrams, etc. Each curve or diagramshould have a title. When plotting curves, the independent variable should be on

horizontal axis. Use scales that are easily interpolated and consistent with theaccuracy of the data. Draw the vertical and horizontal axis inside the border of the

graph paper, and label the variable and units on each axis. Draw small circles around

each data point, and draw the best smooth curve through the data.

8. Analysis and Conclusions: Discuss and evaluate the results. Don't just present theresults, but interpret what they mean. If you get an unexpected result, explain why it

is unexpected and what may be the cause of the error. Be clear and concise.

9. Procedural Explanations: As you do the experiment, include brief statements of

what you are doing. Another person should be able to follow what you did.


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Air UniversityDepartment of Electrical Engineering

Lab # 1

Introduction to PSPICE

Objective:

The objective of this session is to give initial exposure to the software environment PSPICE(Simulation Program with I ntegrated circui t Emphasis). This experiment introduces the

fundamentals of PSPICE and concentrates on DC analysis.

Introduction:

SPICE is a general purpose circuit simulation programming language that performs non-

linear Dc, transient and linear steady state AC analysis. Linear circuit elements of resistance,

capacitance, inductance, independent and dependant current and voltage sources are modeled.

Four of the most common nonlinear semiconductor devices (diodes, BJTs, JFETs and

MOSFETs) and many other useful circuit relationships including transmission lines andmutual inductance are also modeled.

General Theory and Procedure:

To start PSPICE, click: Start > Programs > DesignLabEval8 > Design Manager

Click on the PSPICE schematic icon given on the left side of the design manager

window or select schematic directly from the design EVAL software menu.

Draw Schematics:

Select the desire components from Draw > Get New Part and place the part. Repeat the first step until all the necessary parts are placed.

Connect each component with the Draw > Wire command.

Save the circuit.

Select Desired Analysis:

Click Analysis > Setup and set the options.

Click DC Sweep and select values from -5v to +5v in 0.1v increment.

Click Analysis > Electrical Rule Check to check your result.

Run The Simulation:


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Analysis > Simulation

If errors are found, they will be described in the File_name.out file after execution.

View the contents of this file using Analysis > EXAMINEOUTPUT.

To See The Graph:

Click Analysis > Run Probe

Click Analysis > Probe Setup > Probe Start up. Select the option Automatically run

probe so that probe window will open automatically after every simulation.

In probe window: click Trace> Add. Add the traces which you want to display andclick OK. You will see the required results.

Circuit #1:

Graph:

Circuit #2:


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Introduction to PSpice

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Graph:

Note:Show the results to the instructor


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Air University


Lab # 2

NMOS Inverter

Objective:

After successfully completing the first lab you understand the basics of using Pspice to build

and simulate circuits. Now incorporating MOS transistors into circuits should be a simple

extension of what you already know. To illustrate the basic approach with MOSFETs this

lab will get through two examples: the voltage transfer characteristics (VTC) and switching

speed of a simple NMOS inverter.

Theory:

1. How Pspice handle MOS transistors:

Before starting this lab, a bit of background on MOSFETs in Pspice is needed. The basic

approach reflects the fact that the vast majority of MOS transistors are used in integrated

circuits. since all of the transistors in an IC are made at the same time , most of the properties

of similar devices are shared , meaning that all of the NMOS transistors will have the same

V ,COX , Lambda , etc thus it makes little sense to specify these parameters repeatedly for

each individuals transistors. Instead, a general model which specifies these quantities can bedefined and used throughout the circuit definition. However individual transistors may have

different sizes, the most important being W and L (or the W/L ratio), so we do need to be

able to specify these quantities for each transistor.

In PSpice , there are a several generic MOSFET models that can be used for our simple

circuits. Most of these have names like MbreakN3 or MbreakP4. In spice M is the

designator for MOSFET. The break part of the name refers to the fact that the individual

leads are broken out for making attachments .the N or P part refers to NMOS or PMOS. The

final number refers to how many leads are available for connection. in general MOSFETs

leads (D,G,S,B), but if the source is tied to the substrate internally there will be only 3 leads

available ( D,G,S).

As we place the transistors into circuit schematic, we can use the MbreakN3 model. Then for

each individual transistor, we will need to specify the length and width. Also each transistor

will have its own designator. (Many transistors can use the parameter defined by MbreakN3

but each device must have a unique name). If we need to use transistors that have different

values of V ,COX (e.g a unique transistor), then we need to define a a different model for

those transistors.


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NMOS Inverter

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Procedure:

Start Pspice and draw schematic of the NMOS inverter as given below:

Change the value of the resistor to 5k the value of the power supply to 5V.You mayalso want to change the names, just keep things from being confusing. You dont need

to change the voltage of the input DC supply, which will be done as part of the DCsweep analysis.

Now its time to work on the transistor.

1. first step is to give the MbreakN family the properties we want. Double click on the

transistor. You will see parameters in the window. Just click on the parameter like L

and put the value e.g. 1u. click Save Attr so that the value will appear in front of the

parameter L

2. Repeat the same procedure for width W. Put W =10u.

3. if you scroll down the bar, you will see the MODEL = MbreakN because you haveselected the same transistor from the Get New Part menu. Thos simply says that the

MbreakN is an NMOS transistor and all of its parameters are set to the default values.

We will not change any parameter in the model at this stage.

4. Click OK.

Save the file and add DC sweep as you did in the first lab.

Now we are in a position to set up the simulation. And check for errors. Iferrors occur then see output file for details otherwise Run Probe and Add

Traces to see the VTC of the NMOS inverter.


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In Add Traces window you will see the variables like, V (M1:d), it means

drain voltage of M1 transistor.

Results:

Draw VTC below and show the results to the instructor.

Inverter Switching Speed:

Now we would like to use SPICE to show us how fast the inverter output can go high and

low when a capacitive load is attached. This requires a different type of analysis determining

switching speed implies looking at the output as a function o f time. Thus we need to have the

input change at some point in time and have PSPICE analyze the circuit for a series of time

steps which can then be combining together to give the response of the circuit as function of

time. In SPICE, this is known as a transient analysis. This is in contrast to the DC sweep

analysis that weve seen in previous example. Each type of analysis has its place and

knowing which type of analysis to use in a given situation is an important skill for a circuitdesigner.

We can use the same basic inverter circuit for the switching speed analysis, with three

changes: 1) add a capacitor at the output to serve as the effective capacitive load seen by the

inverter. 2) Change the input from a DC source to a voltage pulse input which will make the

inverter switch, and 3) change the simulation settings to a transient analysis.

Procedure:

1. Go back to the circuit schematic. Add a capacitor at the output of the inverter.

Change the value to 20p (10 Pico farads), which might be a typical value in an IC.

2. Change the input voltage source to a pulse. Remove the DC source at the input.Use place part to select VPULSE from the SOURCE library, Insert the VPULSE part


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NMOS Inverter

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into the input. The VPULSE part comes with seven parameters that govern its

behavior. Explanations for each of the parameters are listed in the table below along

with the settings we will use for this example. (We need to choose the pulse times at

the input so that we can get a reasonable view of the voltage swings at the output.

Often, is becomes a matter of trial and error to determine the best values for the pulse

source. As with many things, a bit of experience will help reduce the number of trialsand errors).

Pulse parameter Explanation Value for this example

V1 The starting voltage (at t=0)

for the pulse.0

V2The second voltage for the

pulse.5

TD

The delay time. At t=0, the

input is at V1 and stays at V1

until time TD, at which timeit begins to switch to V2.

0.15u (0.15 s)

TR

The rise time. This is how

long it takes to make the

transition from V1 to V2.

(This can be very small but

should not be set to 0.)

1p (1 picoseconds We arent

interested in rise and fall at

the input, so we make it very

short.)

TF

The fall time. How long it

takes to transition back to V1

from V2. The same

comments regarding TR

apply to TF.

1p

PW

The pulse width. The time

that the pulse stays at V2

before dropping back to V1.

0.15u

PER

The period. The pulse repeats

after this amount of time. By

setting the analysis time to

about 1 period, we will see

just onepulse. Thats

sufficient for our purposes.

By setting the analysis timemuch longer than one period,

we can view many pulses.

0.6u

Note that we will be using a a pulse that starts low, goes high , and then goes low again.

However the voltage pulse could be inverted simply by changing the relative values of V1

and V2.


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3. At this point the circuit is completed and should look similar to the figure below.

4. Change the Simulation Settings. Last but not least, we must tell Pspice to do a

transient analysis. Open the analysis set up dialog. Change the Analysis type to time

domain (transient). Set the print step to 5ns and Final Time to 0.5us. by these settings

the circuit will be analyzed at least 100 points (0.5us/5ns = 100).

5. Run the Simulation: if no errors occurs, we will be looking at the empty graph that

probe presents us. This time the horizontal axis will be a time scale from 0 to 500ns.

Display the input and output signals on the graph.

6. Add Cursor. Click TOOLS> CURSOR > DISPLAY. Cursor will be displayed on the

probe window. Now measure the propagation time on both rising and falling edges at50% of the VOH which is 2.5 V (approx) in our case.

7. Results: Draw graph below, Note tPHL and tPLH and show the results to the instructor.


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Air University


Lab # 3

CMOS & Pseudo NMOS Inverter

Objective:

How to handle a MOSFET in PSpice is not an issue after the completion of second lab. In this lab our

objective is to address the issues that were not solved in the NMOS inverter. The VTC of the CMOS

& Pseudo NMOS inverter will be observed.

Theory:

Why CMOS inverters are needed:

In previous lab when the voltage transfer characteristics of an NMOS inverter were observed,

we noticed that the digital logic high was VDD whereas the digital logic low was not entirely

zero volts or ground. We just assumed the latter to be logic zero because it was far less than

VDD/2. But still it would be nice and more convenient if logic zero really meant ground or

zero volts. So, another option was to switch to a PMOS inverter. The inverters digital logic

zero is actually zero volts or ground. But unfortunately, the digital logic high is not

completely VDD, Similarly like NMOS inverter the logic high is greater than VDD/2 in case of

PMOS inverter.

To solve the issues addressed above we use the combination of both PMOS and NMOS to

make another inverter which is commonly known as CMOS or Complementary MOSFET

inverter. Whenever the input is zero the PMOS turns on and the NMOS turns off and V DD

appears at the output. This is because when PMOS conducts, the output node connects with

the power supply. When the input is high or VDD, the NMOS turns on and PMOS turns off

and ground appears at the output. Similar like PMOS when NMOS turns on the output node

connects to the ground.


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While designing the CMOS inverter, last but not least issue is of assignment of the W/L

ratios. It is known that the mobility of the carriers in NMOS is 3 times greater than the

mobility of the carriers in PMOS. The mobility can be referred as to the ability of the

MOSFET to allow the certain amount of current in certain time. The more the mobility, the

more the current flows and quickly the node settles to a certain value. The mobility, isincorporated in k of the MOSFETS i.e. kn=ncox. So kn=3kp, so to keep the current

through both the MOSFET same, we need to balance the kn and kp factors with something

else in the equation of the current. We choose (W/L)p=3(W/L)n and keeping the L same, we

conclude Wp=3Wn.

Procedure:

1. Start Pspice and draw schematic of the CMOS inverter as given below:

2. Change the value the value of the power supply to 5V.You may also want to change

the names, just keep things to avoid confusion. You dont need to change the voltage

of the input DC supply, which will be done as part of the DC sweep analysis.

3. Now its time to work on the transistor.

4. Double click on NMOS, the parameters of NMOS will be shown. Double click on L.

Put L=1u and click save attr to save attribute.



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CMOS and Pseudo NMOS Inverter

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6. Similarly put L=1u for PMOS.

7.Now it is time to decide W for PMOS. As we kept the W for NMOS 10u, we mustkeep W for PMOS 30u.

8. Click OK.

a. Save the file and add DC sweep as you did in the first lab.

b. Now we are in a position to set up the simulation. And check for errors. If

errors occur then see output file for details otherwise Run Probe and Add

Traces to see the VTC of the CMOS inverter. Observe and Note the VTC

curve.

9. After observing the VTC, now we will make two changes in the same circuit. For fast

response add a capacitor of 10pf at the output. Replace the input DC source with pulse

voltage source. The parameters for the pulse voltage source are the same as in the

previous lab.

10.Apply the transient analysis for this circuit for print step= 5ns and final time =0.5 us.

11.Find the propagation delay using cursor.

Results:

Draw Curve below and show the results to the instructor.

Pseudo NMOS Inverter:

The CMOS circuits have an advantage of giving the true logics at the output according to the

input. But when it comes to the size of the designed circuit, we are at a far greater

disadvantage. The reason is that the size of the PMOS is greater than the NMOS due to themajority of p carriers whose size is greater than the n carriers. Also, for the CMOS circuits


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the W/L ratio of the PMOS needs to be 3 times greater than the W/L ratio of the NMOS. In

case of inverters, both the CMOS and Pseudo NMOS will have the same number of PMOS,

so it is good to choose CMOS which gives us correct logics i.e.5 for high and 0 for low. But

when the design is increased and a logic circuit is created, we need to implement the Pseudo

NMOS technology to keep the size of the circuit less. Due to the fact that the PMOS remainsconstantly on, the low logic is shifted to a level above than zero volts. The W/L ratio of the

PMOS used in Pseudo NMOS is also kept so that it should allow a certain amount of current

that would help the low logic remain near the zero volts.

Procedure:

1. Start Pspice and draw schematic of the Pseudo NMOS inverter as given below:


the names, just keep things from being confusing. You dont need to change the

voltage of the input DC supply, which will be done as part of the DC sweep analysis.

3. Now its time to work on the transistor.

4. Double click on NMOS, the parameters of NMOS will be shown. Double click on L.

Put L=1u and click save attr to save attribute.



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CMOS and Pseudo NMOS Inverter

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6. Similarly put L=1u for PMOS.

7.

Keep W=10us for PMOS. We dont want to spoil the logic zero further than it wouldbe already by keeping PMOS on even when input to the circuit is high.

8. Click OK.

a. Save the file and add DC sweep as you did in the first lab.

b. Now we are in a position to set up the simulation. And check for errors. If

errors occur then see output file for details otherwise Run Probe and Add

Traces to see the VTC of the CMOS inverter. Observe and Note the VTC

curve.

12.After observing the VTC, now we will make two changes in the same circuit. For fast

response add a capacitor of 10pf at the output. Replace the input DC source with pulse

voltage source. The parameters for the pulse voltage source are TD=0.15u, TR=1p,

TF=1p, PW=0.15u, PER=0.6u.

13.Apply the transient analysis for this circuit for print step= 5ns and final time =0.5 us.

14.Find the propagation delay using cursor.

Results:



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NAND and NOR Gates

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output to the logic high and logic low level respectively e.g. if there are four MOSFETs that

can drive the output to the low, so the worst case will be only one MOSFET pulling the

output low. The cases are chosen so as to keep the minimum delay for the transition of the

output. The delays can cause a problem if the designed digital circuit is a part of another

larger circuit.

Procedure:

1. Start Pspice and draw schematic of the NAND gate as given below:


the names, just keep things to avoid confusion. For the input of the MOSFETs keep

the clock as input. i.e. pulse. For both the inputs the clocks will be individual and will

be assigned the parameters so that the exhibit all the four combinations of the two

binary bits.

3. Now its time to work on the W/L of the transistors.

4. Set L of PMOS and NMOS to 1u.

5. Set W of NMOS to 20u that was found out according to the calculations.

6. Set W of PMOS to 30u (10u for software) that was found out according to thecalculations and the fact that Wp= 3Wn.


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7. Now, we set the two input pulses parameter so that the two bit combination pattern is

adjusted.

8. For pulse V1, set V1=0V, V2=5V, TD=0.3u, TR=1p, TF=1p, PW=0.3u, PER=0.6u.


10.Apply the transient analysis for this circuit for print step= 5ns and final time such thatall the four combination are provided for the input i.e. 0.6us.

Results:


Procedure:

1. Start Pspice and draw schematic of the NOR gate as given below:


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NAND and NOR Gates

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the names, just keep things from being confusing. For the input of the MOSFETs keep



binary bits.


4.Set L of PMOS and NMOS to 1u.

5. Set W of NMOS to 10u that was found out according to the calculations.

6. Set W of PMOS to 60u (20u for software) that was found out according to the

calculations and the fact that Wp= 3Wn.

7. Set parameters for pulses and transient analysis same as done for previous circuit of

the lab

Results:



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Lab # 5

Dynamic and Domino Logic

Objective:

The objective of this lab is to study the disadvantages provided by the CMOS and Pseudo

NMOS technology and to study the techniques which would overcome these disadvantages.

Theory:

Disadvantages of CMOS and Pseudo NMOS technology:

CMOS technology excels in nearly every performance category. It is easy to design, has the

maximum possible logic swing, dissipates no static power and can be designed to achieveequal low-to-high and high-to-low propagation delays. Its main disadvantage is the

requirement of two transistors for each additional gate input, which for high fan-in gates can

make the chip area large and increase the total capacitance and correspondingly, the

propagation delays and the dynamic power dissipation. Pseudo- NMOS reduces the number

of required transistors at the expense of static power dissipation.

Designing of Dynamic Logic:

In this logic, we have two switches in series with the PDN that are periodically operated by

the clock signal . When is low, PMOS is turned on, and the circuit is said to be in thesetup or pre-charge phase. When is high, NMOS is turned on and circuit is in the

evaluation phase. The logic has a PDN connected to the supply through the PMOS and

connected to ground through NMOS and a capacitor is connected at the output. The PMOS

and NMOS are being operated by the clock signal discussed above.

During pre-charge PMOS conducts and charges load capacitance so that, at the end of the

pre-charge interval, the voltage at Y is equal to VDD. Also during pre-charge, all the inputs of

PDN are allowed to change and settle to their proper values. Because NMOS is off, no path

to ground exists. During evaluation phase PMOS is off and NMOS is turned on. Now, if

input combination is one that corresponds to a high output, the PDN does not conduct and the


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output remains high at VDD and no propagation low to high delay is required. On the other

hand, if the combination of the input is one that corresponds to a low output., the appropriate

NMOS transistors in the PDN will conduct and establish a path between the output node and

ground through the NMOS transistor below the PDN.

Procedure:

Start PSpice and draw schematic of the Dynamic logic gate as given below:

Change the value the value of the power supply to 5V.You may also want to changethe names, just keep things to avoid confusion. For the input of the MOSFETs keep



binary bits. Here one input is the clock discussed above. Other input is the input to

the PDN which is NMOS.

Now its time to work on the W/L of the transistors.

Set L of PMOS and NMOS to 1u.

Set W of all NMOS to 10u.

Set W of PMOS to 30u (10u for software) that was found out according to thecalculations and the fact that Wp= 3Wn.

Now, we set the two input pulses parameter so that the two bit combination pattern isadjusted.

For pulse V1, set V1=0V, V2=5V, TD=0.3u, TR=1p, TF=1p, PW=0.3u, PER=0.6u.

For pulse V2, set V1=0V, V2=5V, TD=0.15u, TR=1p, TF=1p, PW=0.15u, PER=0.3u.


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Apply the transient analysis for this circuit for print step= 5ns and final time such that

all the four combination are provided for the input i.e. 0.6us.

Results:

Draw Curves below and show the results to the instructor.

Designing of Domino Logic:

The domino logic needs to be designed to compensate a disadvantage of the dynamic logic.

Whenever the dynamic logic is cascaded, for a certain combination of the input the output

level is less than the desired. (For detailed studies refer to Microelectronic circuits by

Sedra/Smith, Chapter 10, Section 10.6.2, Cascading Dynamic Logic Gates) Above

experiment was also about the cascaded dynamic logic to see the effect it does to the output.

To remove this effect we use the Domino CMOS Logic.

Domino CMOS logic is a form of dynamic logic that results in cascade-able gates. An

additional static CMOS inverter is connected after every dynamic logic state. First

considering a single dynamic logic with a single inverter, the operation is simple. During pre-charge X (output after dynamic) will be raised to VDD and the gate output Y (after CMOS

inverter) remain low or X will be brought down to 0V and the output Y will raise to VDD.

Thus, during evaluation the output either remains low or makes only one low-to-high

transition.

Now, we consider the case of cascading the two dynamic logic circuits with two CMOS

inverters. At the end of pre-charge, X1 (output after first dynamic circuit) will be at VDD. Y1

(output after first inverter) will be 0V. X2 (output after second dynamic circuit) will be at VDD

and Y2 (output after second inverter) will be at 0 V. As in the preceding case, assume A is

high at the beginning of evaluation. Thus, as goes up, output capacitor C L1 , after first

dynamic circuit, will begin discharging, pulling X1 down. Meanwhile, the low input at the


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gate of first PDN keeps it off, and CL2 remains fully charged. When X1 falls below the

threshold voltage of first CMOS inverter, Y1 will go up turning second PDN on, which in

turn begins to discharge CL2 and pulls X2 low. Eventually, Y2 rises to VDD.

Procedure:

1. Start PSpice and draw schematic of the Domino logic gate as given below:




be assigned the parameters so that the exhibit all the four combinations of the twobinary bits. Here one input is the clock discussed above. Other input is the input to

the PDN which is NMOS.


4.Set L of PMOS and NMOS to 1u.

5. Set W of NMOS to 10u.

6. Set W of PMOS to 30u (10u for software) that was found out according to the

calculations and the fact that Wp= 3Wn.

7. Set parameters for pulses and transient analysis same as done for previous circuit of

the lab


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Results:



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Lab # 6

SR Flip Flop

Objective:

The objective of this lab is to study the CMOS implementation of the SR Flip Flop that can

be used as a memory element to store a single bit.

Theory:

The SR Flip Flop:

The simplest type of the flip flop is set/reset (SR) flip flop. It has two inputs labeled by S and

R and two outputs Q and Q. When the inputs S & R both are low, there is no change in theoutput of the SR flip flop, hence acting as a memory device. When S is high and R is low, the

output is set or high. When R is high and S is low, the output is reset or low. When S & R

both are high, the output cannot be determined; hence the state is not used. Below is the truth

table of the SR flip flop.

R S Output(Qt+1)

0 0 No change

(Qt)

0 1 Set (1)

1 0 Reset(0)

1 1 Not used

CMOS Implementation of SR flip-flop:

The circuit of this implementation is given below in PSpice diagram. There are two inverters

whose outputs are the input of each other thus forming a latch. The output of the left inverter

is Q and that of the right one is Q. The output Q is attached to the NMOS whose input is S


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through another NMOS whose input is clock. The output Q is attached to the NMOS whose

input is R through another NMOS whose input is clock. The clock here is the common one.

Lets say Q is high, so it will act as input for the inverter whose output is Q and it will go

low and in turn this output Q will drive Q high because it is the input of the inverter whose

output is Q.

Now the clock is a square wave with 50% duty cycle. So whenever the input is low, the

NMOS will be off and hence the inputs S and R will have no effect. Whenever the input is

high, the NMOS will be on and the outputs will set or reset according to the input

combination of S and R. Now first if S & R both are low, there is no path for the Q and Q to

the ground, so the outputs Q and Q will not change their previous state, hence we have no

change. If S is high and R is low, the output Q will have a path to the ground, so even if Q

is high, it will have to discharge and will go towards low. In effect the output Q will be high.

So, we have set state. If R is high and S is low, the output Q will have a path to the ground,

so even if Q is high, it will have to discharge and will go towards low. So, we have set state.In effect the output Q will be high. If S & R both are high, there will be a path for both the Q

and Q to the ground and both will try to discharge simultaneously and due to the feedback

structure they will also try to pull each other high, the output state will never go to set or

reset. So that is why, we do not use this state.

To implement the SR flip flop in the PSpice, we have to use an additional element called

sw_topen. It is a switch that opens after the parameter t_open is over. It is used to make the

output state of the flip-flop determined before it is used. One end is connected to the supply

and other to the output Q. The parameters of the switch are t_open and t_tran. t_open

determines after how much time, the switch opens and t_tran determines that after how longthe effect of the switch wears off.

Procedure:

1. Start PSpice and draw schematic of the SR flip flop as given below:


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the names, just keep things to avoid confusion. For the input of the MOSFETs keepthe clock as input. i.e. pulse. For all the inputs the pulses will be individual and will

be assigned the parameters so that the exhibit all the eight combinations of the three

binary bits. Here one input is the clock discussed above and other two inputs are S &

R.



5. Set W of NMOS in the inverter to 10u and for the rest of the NMOS set W to 40u.

6. Set W of PMOS to 30u.

7. Now, we set the three input pulses parameter so that the three bit combination patternis adjusted.

8. For pulse V1 (input = S), set V1=0V, V2=5V, TD=0.3u, TR=1p, TF=1p, PW=0.3u,

PER=0.6u.

9. For pulse V2 (input = clk), set V1=0V, V2=5V, TD=0.15u, TR=1p, TF=1p,

PW=0.15u, PER=0.3u.

10.For pulse V3 (input = R), set V1=0V, V2=5V, TD=0.6u, TR=1p, TF=1p, PW=0.6u,

PER=1.2u.

11.Apply the transient analysis for this circuit for print step= 5ns and final time such that


Results:



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Lab # 7

SRAM Cell

Objective:

The objective of this lab is to study how the data is read from an SRAM cell.

Theory:

The SRAM cell read process:

In the previous lab, we studied the SR flip flop that was used as the memory element to store

a single bit. The main storing structure was the back to back inverters. The similar structure is

used to store the bit. But to read the data from the cell, we need extra circuitry. First of allcomes two NMOS both connected to the Q and Q output of the back to back inverters. These

MOSFETs are considered to be functioning when the corresponding word line is functioning.

Another circuitry is the equalization and pre-charge circuitry. This circuitry helps in reading

the stored data from the cell. It includes three MOSFETs in total. One MOSFET is used to

equalize the charge and the other two to pre-charge the bit lines. The bit lines are connected

to the other end of the MOSFETs whose input is controlled by word line. The input of all the

MOSFETs of the pre-charge and equalization circuit is common and is given as a clock. The

body terminal of all the MOSFETs except the back to back inverters is grounded. One end of

both the pre-charge MOSFETs is connected to 2.5 V and the other end to the remaining end

of the MOSFETs activated by the word line. (Remember that their one end was with the Q

and Q) Both the ends of the equalization MOSFET are connected with the second end of the

MOSFETs activated by the word line. This second end is also called the bit line. (See the

figure in the experiment for the clarification.)

For the experiment we connect one pulse to Q of the back to back inverter to vary the stored

data. One pulse to the equalization and pre-charge circuitry where clock was supposed to be

given and one pulse to the MOSFETs activated by the word line. We can store high or low

data as we have the control on it. Then, to read the data first we pre-charge the bit lines bygiving high to these MOSFETs. As the equalization MOSFET is connected to both bit lines


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(B and B), it equalizes both the lines to 2.5 V. Now, this circuitry turns off and the pulse

simulating the word line is turned on. The MOSFETs turns on. On one end of the MOSFETs

is 2.5 V and on other end is the stored data (Q and Q). Suppose a 1 was stored, so now the

B-line will get charged to 5 V. and B-line discharges to 0 V. Thus, we can read the data.

Procedure:

1. Start PSpice and draw schematic of the SRAM read circuitry as given below:



the clock as input. i.e. pulse. Here two pulses will be inverted version of each other

and one pulse will go low and then high for the simulation of stored data.



5. Set W of NMOS in the inverter to 10u and for the rest of the NMOS set W to 40u.

6. Set W of PMOS to 30u.

7. Now, we set the three input pulses parameter as discussed above


9. For pulse V2 (input = clk), set V1=0V, V2=5V, TD=0.15u, TR=1p, TF=1p,

PW=0.15u, PER=0.3u.

10.For pulse V3 (input = R), set V1=0V, V2=5V, TD=0.3u, TR=1p, TF=1p, PW=0.3u,

PER=0.6u.


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11.Apply the transient analysis for this circuit for print step= 5ns and final time such that


Results:


Documents

Digital Electronics_Lab Manual