Digital Electronics Lab Manual

7/17/2019 Digital Electronics Lab Manual

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DIGITAL ELECTRONICS LAB MANUAL



List Of Experiments

DIGITAL ELECTRONICS LAB PRACTICE &eCAD TOOLS LAB PRACTICE

Subject Title : Digital Electronics &eCAD Tools LabPractice

Subject Coe : EC!"#$Perios%ee' : #(Perios%Se)ester : $#

Rationale: This is a core lab .stuent is e!"ecte to unerstan an e#onstrate

"ractical s$ills in hanlin% & ienti'( an usin% i''erent instru#ents an )arious

Di%ital ICs *ith ease .E#"hasis is lai on i#"artin% "ractical s$ills use'ul in the

inustr(. CAD tools "art is also inclue to enable the stuents learn latest

so't*are tools use in the inustr( .

LIST O* E+PERI,ENTS

I- Basic Gates an Logic *a)ilies

.- Ienti/0 Digital ICs an noting o1n 2in etails /ro) ata s3eets a+ Ienti'( the %i)en i%ital ICs an ra* the "in ia%ra#s. , use TTL an

CMOS ICs o' AND& OR&NOT& NAND& NOR an -OR %ates *ith t*o an three in"uts+

b+ Realie basic %ate 'unctions usin% to%%le s*itches an a bulb

S- No- ,ajor To2icsNo- o/ Perio

s

I- Basic Gates an Logic *a)ilies .4

II-

Reali5ation o/ Boolean *unctions using Gates

.4

III-Reali5ation o/ Boolean *unctions using,ulti2le6ers an De,ulti2le6ers

.4

I7-*li2 *lo2s & Ti)ing Circuits

.4

7-Counters & S3i/t Registers

.4

7I Digital Circuit si)ulation using eCAD tools "#

$#



/. 0eri'( the truth tables o' AND& OR&NOT& NAND& NOR Gatesa+ Measure threshol )olta%es resultin% in chan%e o' a state o' a NAND %ateb+ 0eri'( the truth table o' 1234 IC ,o"en collector 5ua /in"ut NAND %ate+.c+ 0eri'( the Truth table o' 2314 IC

4. Realie AND& OR& NOT& 'unctions usin% / in"ut NAND an NOR TTL Gatesa8 I#"le#ent 6ire AND 7 6ire OR circuit an )eri'( the truth tableb+ 8ro# the ata sheets 'in out CMOS E5ui)alent o' abo)e ICs

II- Reali5ing Boolean *unctions

9- I)2le)ent +OR Logic using 4 in2ut Nan Gates an NOR Gates aneri/0 t3e trut3 table

a+ I#"le#ent a 2bit co#"le#ent %enerator usin% 129 5ua -OR ICb+ Realie a si#"le co#"arator usin% -OR Gatec+ Realie a NOT %ate usin% -OR %ate

;. a+ I#"le#ent the %i)en lo%ic 'unction *ith 4 )ariables usin% / in"ut CMOSNAND Gates onl(b+I#"le#ent %i)en lo%ic 'unction *ith 4 )ariables usin% / In"ut CMOS NORGates onl(.

(- I)2le)ent ;al/ aer an /ull aer circuits using TTL%C,OS gates aneri/0 t3e trut3 tables.

a+ 0eri'( the truth table o' BCD to 1 se%#ent Decoer 1229 IC

<- a8 7eri/0 t3e Trut3 table o/ Decoer an E62lore t3e *eatures o/ <9."=Decoer IC

b+ Co#bine t*o 4 to 9 ecoer to realie a 2 to < Decoer

= -7eri/0 t3e Trut3 table o/ <9.9= Encoer IC a+ 0eri'( the 'unction o' 12<29 Encoer an *rite the truth table b+ Co#bine t*o 12<29 Encoer an 0eri'( the truth table

III- Reali5ation o/ Boolean *unctions using ,ulti2le6ers anDe)ulti2le6ers

$- 7eri/0 t3e Trut3 table an *unction o/ ,ulti2le6er IC <9.>"a+ 0eri'( the truth table o' IC 12<;4b+ Co#bine t*o 12<;4 Multi"le!ers ICs to realie 9:< #ulti"le!er c+ I#"le#ent the %i)en 'unction usin% IC 12<;3 <:< line #ulti"le!er

.#- 7eri/0 t3e Trut3 table an *unctions o/ De )ulti2le6ers ?@sing IC <9.>98



..- 7eri/0 t3e /unction o/ 9!bit )agnitue co)2arator <9=>IC-a+ 0eri'( the e''ect o' %i)in% i''erent lo%ic in"uts to "ins /&4&2 o' ICb+ Realie a si#"le /bit co#"arator usin% -OR Gate

I7- *li2 *lo2s & Ti)ing Circuits

.4- Construct an eri/0 t3e trut3 tables o/ NAND & NOR latc3esa+ Realie a Bistable ele#ent *ith t*o NOT %ates an a 8eebac$

Resistor b+ I#"le#ent a bounce Eli#ination s*itch usin% the abo)e Gatesc+ Realie a cloc$ circuit usin% 23=4 CMOS NanGate & Resistor anca"acitor an obser)e the *a)e'or# on CRO

."- Construct cloc'e RS ** using NAND gates an 7eri/0 its trut3 table-a+0eri'( the truth table o' CD 23<4 Dual D 'li" 8lo"b+0eri'( the 'unctionalit( an truth table o' 12L1< RS 'li" 'lo" *ith >reset

an Clear

c+ 0eri'( the Truth table o' ?@ 88 usin% 121 IC.+ Construct D an T 'li" 'lo"s usin% 121 an )eri'( the truth tables.

7 - Counters an S3i/t Registers

.9- Construct an eri/0 t3e /unction o/ ecae counter using <9$# ICs-a+ chan%e the #oulus o' the counterb+Cascae t*o 12=3 ecae counter ICs to count u" to == or an( other

#oulusc+ Dis"la( eci#al nu#ber usin% 1221+ Cascae t*o 1221 ICs to count u" to ==

.>- 7eri/0 t3e /unction o/ u2%o1n counter using <9.$# <9.$"a+ chan%e the #oulus o' the counter an )eri'(b+ 0eri'( the 8unctionalit( o' CD23/= u"o*n counterc+ Loa the >reset in"uts o' CD23/= Counter *ith a binar( nu#ber

.(- 7eri/0 t3e /unction o/ s3i/t register ?ICs li'e <9$> <9.$9 etc-8

.<- 7eri/0 t3e /unction o/ o3nson counter using CD 9#.< ICa+ Chan%e the #oulus o' the counterb+ Desi%n a 8re5uenc( i)ier circuit usin% 23<1 IC

c+ I#"le#ent runnin% LED circuit *ith 23<1 IC

.=- Ienti/0 7arious ,e)or0 ICs an Note t3eir 2in Con/iguration /ro) t3eatas3eets

a+ RAM b+ ROM c+ E>ROM + EE>ROM

Part 4:eCAD TOOLS LAB PRACTICE ? "# Perios8



<=.8a#iliariation o' usa%e o' ORCAD suite o' tools 'or the esi%n an la(out o'"rinte circuit boars ,>CBs+.,4+

/3.Si#ulate a 2 bit 'ull aer subtractor an test./<.Desi%n an si#ulate coe con)erters usin% lo%ic %ates,i+ BCD to e!cess4 coe an )ice )ersa,ii+ Binar( to %ra( an )ice)ersa

//.Desi%n an si#ulate < bit oe)en "arit( chec$er %enerator usin% IC12<93/4.Desi%n an Si#ulate 2 bit ri""le counter *ith Mo<3 an Mo <//2. >rouce >CB la(outs 'or abo)e circuits/;. Desi%n a >CB 'or the DAC93 circuit



The B readboard

The breadboard consists of two terminal strips and two bus strips (often

broken in the centre). Each bus strip has two rows of contacts. Each of the

two rows of contacts are a node. That is, each contact along a row on a bus

strip is connected together (inside the breadboard). Bus strips are used primarily for power supply connections, but are also used for any node

requiring a large number of connections. Each terminal strip has 6 rows and

! columns of contacts on each side of the centre gap. Each row of ! contacts

is a node.

"ou will build your circuits on the terminal strips by inserting the leads of

circuit components into the contact receptacles and making connections with

##$#6 gauge wire. There are wire cutter%strippers and a spool of wire in the

lab. &t is a good practice to wire '! and power supply connections to

separate bus strips.

Fig 1. The breadboard. The lines indicate connected holes.

The ! supply MUST NOT BE EXCEEE since this will damage the

&s (&ntegrated circuits) used during the e*periments. &ncorrect connection



of power to the &s could result in them e*ploding or becoming +ery hot $

with the possib!e serio"s in#"r$ o%%"rring to the peop!e &or'ing on the

experiment( Ens"re that the po&er s"pp!$ po!arit$ and a!! %omponents

and %onne%tions are %orre%t before s&it%hing on po&er .

B"i!ding the Cir%"it

Throughout these e*periments we will use TT chips to build circuits. The

steps for wiring a circuit should be completed in the order described below-

. Turn the power (Trainer /it) off before you build anything0

#. 1ake sure the power is off before you build anything0

2. onnect the '! and ground (345) leads of the power supply to

the power and ground bus strips on your breadboard.

. 7lug the chips you will be using into the breadboard. 7oint all the

chips in the same direction with pin at the upper$left corner. (7in

is often identified by a dot or a notch ne*t to it on the chip

package)

!. onnect '! and 345 pins of each chip to the power and ground

bus strips on the breadboard.

6. 8elect a connection on your schematic and place a piece of hook$

up wire between corresponding pins of the chips on your

breadboard. &t is better to make the short connections before the

longer ones. 1ark each connection on your schematic as you go,so as not to try to make the same connection again at a later stage.

9. 3et one of your group members to check the connections, before

$o" t"rn the po&er on.

:. &f an error is made and is not spotted before you turn the power on.

Turn the power off immediately before you begin to rewire the

circuit.

;. <t the end of the laboratory session, collect you hook$up wires,

chips and all equipment and return them to the demonstrator.

.Tidy the area that you were working in and lea+e it in the same

condition as it was before you started.



Common Ca"ses of )rob!ems

. 4ot connecting the ground and%or power pins for all chips.

#. 4ot turning on the power supply before checking the operation of

the circuit.

2. ea+ing out wires.

. 7lugging wires into the wrong holes.!. 5ri+ing a single gate input with the outputs of two or more gates

6. 1odifying the circuit with the power on.

&n all e*periments, you will be e*pected to obtain all instruments, leads,

components at the start of the e*periment and return them to their proper

place after you ha+e finished the e*periment. 7lease inform the demonstrator

or technician if you locate faulty equipment. &f you damage a chip, inform a

demonstrator, don=t put it back in the bo* of chips for somebody else to use.

Examp!e *mp!ementation of a Logi% Cir%"it

Build a circuit to implement the Boolean function > ? %(%<.%B), please note

that the notation +, refers to . "ou should use that notation during the

write$up of your laboratory e*periments.

@uad # &nput 9 Ae* 9 &n+erter



Fig -. The complete designed and connected circuit

8ometimes the chip manufacturer may denote the first pin by a small

indented circle abo+e the first pin of the chip. 7lace your chips in the same

direction, to sa+e confusion at a later stage. emember that you must

connect power to the chips to get them to work.



Usef"! *C )in detai!s

/00N,N2

9#(4C)



9(4CT)

9:(<45)

9(2$i%p <45)



92#(C)

7486(EX-OR)



9(2$i%p 4<45)

9#($i%p 4<45)



A<>%>D <55E

,im- $ To realie half%full adder

,pparat"s 3e4"ired5 6

& 9:6, & 92#, & 9:, & 9, etc.

)ro%ed"re5 6

. erify the gates.#. 1ake the connections as per the circuit diagram.

2. 8witch on and apply +arious combinations of input according to

truth table.

. 4ote down the output readings for half%full adder and half%full

subtractor sum%difference and the carry%borrow bit for different

combinations of inputs.

Cir%"it iagram56







MUX/DEMUX USING 74153 & 74139

,im- $ To +erify the truth table of 1DF and 5E1DF .


IC 74153, IC 74139 etc.

)ro%ed"re5 6 *C /1782

. The 7in G6H is connected to ' cc.

#. 7in G:H is connected to ground.

2. The inputs are applied either to I<J input or IBJ input.

. &f 1DF I<J has to be initialied, Ea is made low and if 1DF IBJ

has to be initialied, Eb is made low.

!. Based on the selection lines one of the inputs will be selected at the

output and thus +erify the truth table

)ro%ed"re5 6 *C /1892

. The inputs are applied to either IaJ input or IbJ input

#. The demu* is acti+ated by making Ea low and Eb low.

2. erify the truth table .







B&4<" TC 3<" <45 3<" TC B&4<"

C4E8&C4

,im- $ To con+ert gi+en binary numbers to gray codes.


& 9:6, etc

)ro%ed"re5 6

. The circuit connections are made as shown in fig.

#. 7in () is connected to 'cc and 7in (9) to ground.

2. &n the case of binary to gray con+ersion, the inputs B, B, B#

and B2 are gi+en at respecti+e pins and outputs 3, 3, 3#,

32 are taken for all the 6 combinations of the input.

. &n the case of gray to binary con+ersion, the inputs 3, 3, 3#

and 32 are gi+en at respecti+e pins and outputs B, B, B#, and

B2 are taken for all the 6 combinations of inputs.

!. The +alues of the outputs are tabulated.





C17<<TC8

,im5 6 To +erify the truth table of one bit and four bit comparators using

logic 3ates and & 9:!


& 9:6, & 9, & 9:, & 9:!etc.

)ro%ed"re5 6

. erify the gates.

#. 1ake the connections as per the circuit diagram.

2. 8witch on cc.

. <pplying i%p and heck for the outputs.

!. The readings of outputs should be tabulated .

ircuit diagramK truth tables-$



Tabular column -$



8A&>T E3&8TE

<im-$ To study shift register using & 9;! in all its modes i.e.

8&7C%8&8C, 7&8C%7&7C.


& 9;!, etc.

)ro%ed"re56

Seria! *n )ara!!e! O"tS*)O256

. onnections are made as per circuit diagram.

#. <pply the data at serial i%p

2. <pply one clock pulse at clock (ight 8hift) obser+e this data at @<.

. <pply the ne*t data at serial i%p.

!. <pply one clock pulse at clock #, obser+e that the data on @< will shift to

@B and the new data applied will appear at @<.

6. epeat steps # and 2 till all the bits data are entered one by one into the

shift register.Seria! *n Seria! O"tS*SO256


#. oad the shift register with bits of data one by one serially.

2. <t the end of th clock pulse the first data IdJ appears at @5.

. <pply another clock pulseL the second data IdJ appears at @5.

!. <pply another clock pulseL the third data appears at @5.6. <pplication of ne*t clock pulse will enable the th data Id2J to appear at

@5. Thus the data applied serially at the input comes out serially at @5

)ara!!e! *n Seria! O"t )*SO256




#. <pply the desired bit data at <, B, and 5.

2. /eeping the mode control 1? apply one clock pulse. The data applied at

<, B, and 5 will appear at @<, @B, @ and @5 respecti+ely.

. 4ow mode control 1?. <pply clock pulses one by one and obser+e the

5ata coming out serially at @5

)ara!!e! *n )ara!!e! O"t )*)O2-$


#. <pply the bit data at <, B, and 5.

2. <pply one clock pulse at lock # (4ote- 1ode control 1?).

. The bit data at <, B, and 5 appears at @<, @B, @ and @5

respecti+ely.

Cir%"it diagram 56





)*SO56



<8"4AC4CD8 CD4TE 5E8&34 <45 1C5$4

CD4TE

,im5 6 ealiation of 2$bit <synchronous counter and 1od$4 counter

design ..


& 9:, & 996, & 9, & 92# etc.

)ro%ed"re5 6


#. lock pulses are applied one by one at the clock &%7 and the C%7 is

obser+ed at @<, @B K @ for & 996.

2. erify the Truth table .

Cir%"it iagram5









8"4AC4CD8 CD4TE 5E8&34

,im5 6 ealiation of 2$bit synchronous counter design.

.


& 9:, & 996, & 9, & 92# etc.

)ro%ed"re5 6


#. lock pulses are applied one by one at the clock &%7 and the C%7 is

obser+ed at @<, @B K @ for & 996.

2. erify the Truth table .

Cir%"it iagram: Tr"th tab!e5



Tr"th tab!e 56



>&7$>C7

,im56 Truth table +erification of >lip$>lops- (i) 8$Type

(ii) 5$ Type

(iii) T$ Type.

(i+)M/$Type


& 9,& 9 etc.

)ro%ed"re5 6


#. erify the truth table for +arious combinations of inputs.

Cir%"it iagram: Tr"th tab!e5

i23S F!ip6F!op



Qn

/Qn

RSQn+1

/Qn+1

0 1 00

1 0 00

0 1 01

1 0 010 1 10

1 0 10

0 1 11

1 0 11

ii2 F!ip6F!op



iii2 T F!ip6f!op







Documents

Digital Electronics Lab Manual