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DIGITAL DESIGN FLOW For EDA Tools:
Synopsys Design Compiler
Cadence SOC Encounter
July 2012
LOGIC SYNTHESIS SYNOPSYS DESIGN VISION
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Digital Design Flow
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Front-end Back-end
Specification
RTL Coding
Testbench
P & R Back
Annotation
Timing
Constraints
Synthesis
Standard
Cells
Simulation
Pass?
Pre-Layout
Timing
Analysis
Post-Layout
Timing
Analysis
Logic
Verification
Tape-out
We are here
Starting Design Vision
[user#@ICICHP home]$ cd digital_workshop/synthesis
[user#@ICICHP synthesis]$ design_vision
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Hierarchy browser
Console
Console Command Line
Setup
File -> Setup
/home/pouri/digital_workshop/synthesis/.synopsys_dc.setup
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RTL HDL Model Analysis
File -> Analyze
analyze -library WORK -format vhdl
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Design elaboration
File -> Elaborate
elaborate ADDSUB -architecture DFL -library WORK -parameters "NBITS = 8"
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Create design Schematic
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Design Environment Definition
Attributes -> Operating Environment -> operating Condition
set_operating_conditions -library slow slow
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Design Environment Definition
Attributes -> Operating Environment -> Wire Load
set_wire_load_model -name tsmc18_wl10 -library slow
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Design Constraint Definition
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Design Constraint Definition
Attributes -> Specify Clock…
create_clock -name "clk“
-period 10 -waveform {0 5}{ clk }
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Design Constraint Definition
Attributes -> Optimization Constraints -> Design Constraints…
set_max_area 0
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Design Mapping and Optimization
Design -> Compile Ultra…
compile_ultra -map_effort medium -area_effort medium
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Report Generation and Outputs
Design -> Report Area…
Timing -> Report Timing Path
write -hierarchy -format ddc –output ./out/addsub.ddc
write -hierarchy -format verilog –output ./out/addsub.v
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STANDARD CELL
PLACEMENT AND ROUTING CADENCE SOC ENCOUNTER
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Digital Design Flow
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Front-end Back-end
Specification
RTL Coding
Testbench
P & R Back
Annotation
Timing
Constraints
Synthesis
Standard
Cells
Simulation
Pass?
Pre-Layout
Timing
Analysis
Post-Layout
Timing
Analysis
Logic
Verification
Tape-out
We are here
Starting SOC Encounter
[user#@ICICHP home]$ cd digital_workshop/place_Route
[user#@ICICHP place_Route]$ encounter
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Toolbar widgets
Status
Design Views
Color Options
Satellite Window
Setting
gedit source/addsub_NBITS8.conf
################################################
# #
# FirstEncounter Input configuration file #
# #
################################################
# Created by First Encounter v08.10-s338_1 on Sat Nov 12 12:31:56 2011
global rda_Input
set cwd /home/pouri/digital_workshop/place_Route
set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1 -useLefDef56 1 }
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Design Import
Design -> Design Import
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Design Import
Design -> Design Import
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Design Import
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Floorplan Specification
Floorplan -> Specify Floorpaln
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Power Planning- Add Rings
Power -> Power Planning -> Add Rings
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Power Planning- Add Rings
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Power Planning- Add Stripes
Power -> Power Planning -> Add Stripes
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Power Planning- Add Stripes
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Global Net Connection
Floorplan -> Connect Global Nets
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Sroute
Route -> Special Route…
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Sroute
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Operating Conditions Definition
Timing -> Analysis Condition -> Specify Operating Condition/PVT…
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Core Cell Placement
Place -> Standard Cells…
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Core Cell Placement
Place -> Standard Cells…-> Mode
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Core Cell Placement
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Design -> Save Design As … -> SoCE
Post-Placement Timing Analysis
Timing -> Analyze Timing…
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Post-Placement Timing Analysis
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Clock Tree Synthesis
Clock -> Design Clock…
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Clock Tree Synthesis
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Clock Tree Synthesis
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Design Routing
Route -> NanoRoute -> Route
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Design Routing
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Post-Routing Timing Optimization and Analysis
Timing -> Optimize…
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Filler Cell Placement
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Place -> Physical Cells -> Add Filler…
Filler Cell Placement
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Design Checks
Verify -> Verify Connectivity…
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Design Checks
Verify -> Verify Geometry…
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Report Generation
Design -> Report -> Netlis Statistics…
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Report Generation
Design -> Report -> Gate Count…
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Report Generation
Design -> Report -> Summary…
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Post-Route Timing Data Extraction
Timing -> Extract RC…
Timing -> Calculate Delay…
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Post-Route Netlist Generation
Design -> Save -> Netlist
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GDSII File Generation
Design -> Save -> GDS/OASIS
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Thanks For your
Attention
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