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Digital CMOS Library Design
João Lucas dos Santos Munhão
Thesis to obtain the Master of Science Degree in
Aerospace Engineering
Supervisor: Prof. Marcelino Bicho dos Santos
Examination Committee
Chairperson: Prof. José Fernando Alves da SilvaSupervisor: Prof. Marcelino Bicho dos Santos
Member of the Committee: Prof. José João Henriques Teixeira de Sousa
November 2017
ii
To my parents...
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iv
Acknowledgments
I want to thank my parents for all they’ve done. Their sacrifice and determination is what allowed me to
be where I am. They are the reason I’m finishing this course and this thesis, they are my inspiration, my
support and the people that I love the most.
I would like to thank Professor Marcelino Bicho dos Santos for guiding me trough this process and
giving me the chance to work inside a company like SiliconGate.
The people at SiliconGate helped me throughout this journey and teached me most of what I know
now about microelectronics. They are among some of the most smartest, hardworking and dedicated
people I’ve known. And I would like to thank them for making me part of their team.
I would also like to thank Diogo Roma, a fellow Aerospace Engineering student, for helping me in the
beginning of this thesis.
And last but not least, my mates, Tiago Paulino and Rafael Girao. I thank you for being with me along
this crazy journey that studying in IST was.
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Resumo
A caracterizacao de celulas logicas e uma parte essencial do fluxo de projecto digital de circuitos inte-
grados nos dias de hoje. Ficheiros contendo informacoes sobre tempos de atraso de propagacao, lim-
ites para possıveis violacoes temporais em celulas sequencias, potencia dinamica e estatica sao a base
desta caracterizacao. Para tal, simulacao destas celulas com diferentes combinacoes de tensao, tem-
peratura, capacidade de carga e transıstores com diferentes caracterısticas tecnologicas (corners) sao
necessarias. Embora com precisao reduzida, a simulacao digital de grandes circuitos integrados e ex-
tremamente rapida utilizando este tipo de ficheiros em vez do simulador analogico SPICE. Os ficheiros
sao tambem importantes em ferramentas de sıstese automatica para optimizacao do funcionamento
logico e na minimizacao da potencia consumida pelo circuito. Licencas profissionais para software
capaz de caracterizar bibliotecas inteiras de celulas logicas sao por norma extremamente caras. O
algoritmo e a metodologia desenvolvida nesta tese foram feitos a medida para uma pequena empresa
especializada em design de circuitos analogicos com uma pequena presenca no mercado digital. O
objectivo e assim desenvolver uma metodologia e o software necessario para ajudar um engenheiro
de design digital na tarefa de caracterizar uma nova biblioteca de celulas logicas, minimizando tarefas
manuais e automatizando grande parte do processo.
Palavras-chave: fluxo de projecto digital, biblioteca de celulas digitais, caracterizacao de
celulas, analıse em corners, ficheiro liberty
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Abstract
Digital cell characterization is essential in modern integrated circuits digital design flow. Characterization
files that contain information as propagation time delays, timing constraints in sequential cells and both
dynamic and static power consumption are the cornerstone of this type of work. They can be obtained by
simulating standard cells with different combinations of supply voltage, temperature, load capacitance
and MOS fabrication processes (corners) . Although with reduced accuracy, the digital simulation of
large integrated circuits is a significantly faster using this type of data files instead of the analog SPICE
simulation. The files are also important for automatic synthesis tools to optimize logic functionality of
circuits and minimize power consumption of digital circuits. Professional licenses for software capable
of characterizing entire cell libraries are usually expensive. The algorithms and methodology developed
in the scope of this thesis are custom suited for a small company specialized in analog design and with
a small market presence in digital design. The goal, therefore, is to create a methodology and design
the required software capable of assisting a digital design engineer in characterizing a new standard cell
library, by minimizing manual tasks and automate most of the process.
Keywords: digital design flow, digital cell library, cell characterization, corner analysis, liberty
file
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Contents
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Resumo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
List of Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Background 3
2.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Used tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Digital Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Synopsys Liberty Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Liberty File Generation Methodology 11
3.1 Methodology Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Digital Cells Characterization Testbench 15
4.1 Timing Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1 Propagation Time Delays and Transition Times . . . . . . . . . . . . . . . . . . . . 17
4.1.2 Timing Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1.2.1 Minimum Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1.2.2 Setup Time and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.2.3 Recovery Time and Removal Time . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Power Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1 Leakage Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1.1 Junction Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
xi
4.2.1.2 Gate-Oxide Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.1.3 Subthreshold Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.2 Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.2.1 Switching Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.2.2 Internal Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4 HSPICE Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4.1 HSPICE Timing Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4.1.1 Propagation Time and Transition Time HSPICE Code . . . . . . . . . . . 30
4.4.1.2 Minimum Pulse Width HSPICE Code . . . . . . . . . . . . . . . . . . . . 31
4.4.1.3 Setup and Hold Time HSPICE Code . . . . . . . . . . . . . . . . . . . . . 32
4.4.1.4 Recovery and Removal Time HSPICE Code . . . . . . . . . . . . . . . . 32
4.4.2 HSPICE Power Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.2.1 Leakage Power HSPICE Code . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.2.2 Dynamic Power HSPICE Code . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.3 HSPICE capacitance code example . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 Testbench Repository . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5 Methodology Automation Scripts 37
5.1 Netlist and Testbench Generation - gen netlist.py . . . . . . . . . . . . . . . . . . . . . . . 38
5.2 Automatic Spice Simulation Management - lib maker.py . . . . . . . . . . . . . . . . . . . 38
5.2.1 Alter Creation - alter creator.py . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.2 Simulation File Preparation - nhfi thread.py . . . . . . . . . . . . . . . . . . . . . . 41
5.2.3 Multicore Simulation Management - hsp thread.py . . . . . . . . . . . . . . . . . . 42
5.3 Liberty File Writing - lib designer.py . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1 Mt files indexation - index creator.py and alt permuter.py . . . . . . . . . . . . . . 45
5.3.2 Mt file data dictionary - gen dic creator.py and seq dic creator.py . . . . . . . . . 45
5.3.3 Liberty file Writing- lib organizer.py, concat writer.py complete writer.py . . . . . . 47
6 Evaluation and Validation 49
6.1 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.1 Negative edge D flip-flop characterization . . . . . . . . . . . . . . . . . . . . . . . 50
6.2 Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7 Conclusions 57
7.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Bibliography 59
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A Hspice Simulation Files 61
A.1 Hspice Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A.2 Hspice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A.3 Hspice Footer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
B Liberty Shell 65
C Complete Negative Edge D Flip-Flop Liberty File 69
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List of Tables
4.1 Input and Output logic combinations for leakage power. . . . . . . . . . . . . . . . . . . . 33
6.1 Negative edge D flip-flop simulation time, using different alter files. . . . . . . . . . . . . . 52
6.2 NAND2 simulation time, using different alter files. . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 XOR truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4 XOR input to output delay in HSPICE simulation . . . . . . . . . . . . . . . . . . . . . . . 56
6.5 XOR input to output delay in Verilog simulation . . . . . . . . . . . . . . . . . . . . . . . . 56
6.6 Relative error between the HSPICE and Verilog measures . . . . . . . . . . . . . . . . . . 56
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List of Figures
2.1 Typical design flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Methodology for digital library characterization. . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Testbench design flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Blackbox test circuit for a standard cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 NAND gate signal delay between input transition and output transition . . . . . . . . . . . 18
4.4 Delay and transition times definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 D flip-flop with reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Minimum pulse width time violation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 Setup and Hold time definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8 Clock to Q delay for different D pin transitions before and after setup time. . . . . . . . . . 22
4.9 Clock to Q delay dependence with D to clock time. . . . . . . . . . . . . . . . . . . . . . . 22
4.10 Recovery and removal time between a clock and a reset pin. . . . . . . . . . . . . . . . . 23
4.11 CMOS Inverter schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.12 CMOS Inverter diffusion junctions parasitic diodes. . . . . . . . . . . . . . . . . . . . . . . 26
5.1 Methodology automation scripts’ tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 Flowchart of genNetlist script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3 Flowchart Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4 On top graphics depicting the work time of 5 idle threads and 5 idle processes. At the bot-
tom graphics depicting the work time of 5 busy threads and 5 busy processes processes.
Permission to reproduce these images granted by Nathan Grigg [18] . . . . . . . . . . . . 44
6.1 XOR synthesized circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2 XOR testbench circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3 XOR layout after P&R in Cadence Soc Encounter. . . . . . . . . . . . . . . . . . . . . . . 55
6.4 HSPICE and verilog stimuli. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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List of Codes
2.1 Liberty file library and general parameters definition. . . . . . . . . . . . . . . . . . . . . . 7
2.2 Look-up table examples for delay and power characterization . . . . . . . . . . . . . . . . 7
2.3 Cell group general syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Two dimensional LUT for timing characterization . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Propagation delay and slew rate liberty tables. . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Minimum pulse width liberty table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Setup time liberty table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4 Recovery and removal time liberty table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Liberty file leakage power statement example. . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6 Power consumption for non-output transition . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.7 Power consumption for output transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.8 Libety File input pin capacitance definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.9 Propagation delay measure statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10 Minimum pulse width measurement optimization definition . . . . . . . . . . . . . . . . . . 31
4.11 Minimum pulse width measure statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.12 Setup time measurements optimization definition. . . . . . . . . . . . . . . . . . . . . . . . 32
4.13 Setup time measurement values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.14 Recovery and Removel time general measurements optimization definition. . . . . . . . . 32
4.15 Recovery and Removal time general measurements values. . . . . . . . . . . . . . . . . . 32
4.16 HSPICE leakage power measure statements. . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.17 HSPICE dynamic power measurement statements. . . . . . . . . . . . . . . . . . . . . . . 34
4.18 HSPICE non-output transition power measurement statements. . . . . . . . . . . . . . . . 34
4.19 Pin capacitance measurement statements. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.20 Generic testbench directory tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 Simulation general configuration file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2 Alter file example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 Simulation folder directory tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.4 hspiceSim directory tree after simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.5 Simulation parameter based indexation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.6 Group indexation based on look-up table construction. . . . . . . . . . . . . . . . . . . . . 45
xix
5.7 Simulation files after being moved higher in the tree directory hierarchy. . . . . . . . . . . 46
5.8 Cell’s mt files data dictionary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.9 Library and cell configuration file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Hspice Library inclusion code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 Alter file example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3 XOR logic RTL description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4 XOR logic synthesized description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
xx
Nomenclature
2D 2-Dimensional
3D 3-Dimensional
ASIC Application Specific Integrated Circuits
CCS Composite Current Source
CMOS Complementary Metal-Oxide-Semiconductor
CPLD Complex Programmable Logic Device
CPU Central Processing Unit
CSM Current Source Model
DRC Design Rule Check
ECSM Effective Current Source Model
FPGA Field-Programmable Gate Array
GDSII Graphic Data System II
HDL High level Design Language
I/O Input/Output
IC Integrated Circuit
LEF Library Exchange Format
LUT Look-Up Table
LVS Layour Versus Schematic
MOSFET Metal–Oxide–Semiconductor Field-Effect Transistor.
NAND A NAND gate only outputs 1 if all the inputs are 0.
NLDM Non Linear Delay Model
NMOS N-type Metal-Oxide-Semiconductor
xxi
P&R Place and Route
PMOS P-type Metal-Oxide-Semiconductor
PVT Process, Voltage and Temperature
PWL Piece-Wise Linear
RTL Register Transfer Level
SDF Standard Delay Format
SPDM Scalable Polynomial Delay Model
SPEF Standard Parasitic Exchange Format
SPICE Simulated Program with Integrated Circuits Emphasis
SSTA Statistical Static Timing Analysis
VHDL VHSIC Hardware Description Language
VHSIC Very High Speed Integrated Circuits
VLSI Very Large Scale Integration
xxii
Chapter 1
Introduction
1.1 Motivation
The characterization of digital cells is an essential process in the microelectronics industry nowadays, as
fast circuits with low power consumption became an important characteristic in the dawn of the computer
age, motivated by the diminishing size of eletronic circuits in the age of smartphones and tablets.
Application Specific Integrated Circuits (ASIC) are semi-custom or full-custom purpose built inte-
grated circuits designed using standard cells. Standard cells are standarized logic building blocks that
can be created with N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor
(PMOS) transistors, the so called Complementary Metal-Oxide-Semiconductor (CMOS) technology.
The increased complexity of ICs and the increasing transistor density have greatly increased the time
needed to simulate and validate this type of circuits. Therefore, a simplified model for functionality, delay,
power and load capacitance was developed at gate level, where the simulation is a lot simpler and less
time consuming.
By simulating the small building blocks first, in different operating conditions, the time needed to cre-
ate and to validate large ICs is reduced considerably, cutting costs and allowing faster development of
cutting edge circuit designs. The data from these simulations is compiled in timing and power charac-
terization files.
The IC market nowadays contains a plethora of professional software capable of handling the work-
load of characterizing standard cells, like the Cadence® Virtuoso® Characterization Suite applications,
Synopsys® SiliconSmart® and Silvaco® AccuCell XT™. The licenses of this type of software is substan-
tially expensive, making it difficult for small companies to characterize their libraries in-house.
In a partnership with SiliconGate®, a company specialized in developing state-of-the-art IPs, a pro-
posal was made to develop a methodology and a software capable of oprtimizing the characterization of
digital cell libraries.
The aim of this thesis is to, based on the work started by a previous intern student Henrique Luiz,
create a poweful tool and respective methodology capable of creating library characterization files.
1
1.2 Objectives
The methodology has to acquiesce to the following subobjectives:
1. Automation of the work needed to characterize a digital cell library;
2. Generic characterization procedures to ease the process of characterizing different libraries;
3. Minimization of manual tasks, where automation is difficult or not necessary;
4. Modular programming, facilitating code debug and future inclusion of additional chracterization
parameters;
5. Software capable of safely run and manage multicore simulations.
The methodology created shall be adopted by SiliconGate to characterize its internal cell libraries
on a professional level. At the end, the software should be able to generate characterization files in
Synopsis® open-source Liberty format.
1.3 Thesis Outline
Chapter 2 contains a recollection of previous work, exposing the most important tools used during the
thesis, discussing the typical design flow for designing an IC and the importance of time and power
characterization files. The Synopsys Liberty format is also described here.
Chapter 3 presents the general methodology developed.
Chapter 4 describes the necessary steps to design a cell testbench.
Chapter 5 explains the different scripts designed to be used in the methodology.
Chapter 6 exposes how the methodology is used to charactere a negative edge D flip-flop cell and
compares simulation results between an analog simulation tool and gate level models annotated with
library characterization files.
Chapter 7 contains a summary of the work done, the problems that were detected, limitations of the
current method and future work.
2
Chapter 2
Background
2.1 Previous Work
In [1], Sulistyo uses the Non-Linear Delay Model (NLDM) for cell characterization, giving detailed de-
scription of the applied time delay analysis and power characterization SPICE testbenches. In the end,
a characterized library using the elaborated analysis method is presented.
The diminishing process sizes brought new challenges to cell characterization. In [2], Goyal and
Kumar discuss the various limitations of characterizing sub 90 nm technologies. The increased wiring
delays, interconnect resistances and non-linearity of waveforms are not taken into account by the NLDM.
Cadence’s Effective Current Source Model (ECSM) and Synopsys’ Composite Current Source (CCS)
model are possible solutions which this paper analyzes and compares with Simulated Program with
Integrated Circuits Emphasis (SPICE) models. By modelling the cell as a voltage-controlled current
source, it’s possible to map the non-linear behaviour between the inputs and outputs of standard cells
more accurately.
The smaller cell footprint also meant short channel effects became extremely important as stated in
[3]. With this issue becoming relevant in two dimensional (2D) transistor design, three dimensional (3D)
transistor design, FinFETs, with better leakage current characteristics were developed, [4]. In [5], Yuan
et al. propose a method for characterizing this type of cells using a surface potential based model called
BSIM-CMG.
The NLDM’s Look-up tables (LUT) is the most common structure of Liberty files one can find, however
in [6], Kenza and Ouardi describe a new methodology to characterize standard cells where instead of
simulating a multitude of process corners to create the standard LUT’s, a small set of transistor Process,
Voltage and Temperature (PVT) values are chosen and their results interpolated. The so called Scalable
Polynomial Delay Model (SPDM) is an equation based characterization method, capable of reducing
simulation time by staggering values as it only needs to write a single time characterization file for all
operating conditions and operating ranges of a particular technology. However, it loses accuracy as it
models cell delay behaviour using a very limited number of variables.
Besides the usual timing delays, other timing characteristics called timing violations need to be char-
3
acterized. In [7], Nareshkumar estimates the setup and hold times of a cell through Statistical Static
Timing Analysis (SSTA), claiming high accuracy and faster simulations times for the cells tested.
The research done for previous work on characterization tools unveiled a lack of custom made tools
on the market. Most of the library characterization work found, focused in the delay and power models
used in characterization, in the way the measures can be obtained, and on different ways to characterize
different standard cells.
2.2 Used tools
Synopsys® HSPICE® is a circuit simulation tool, based in device modeling. It is one of the most widely
adopted simulation tool worldwide, containing a large ammount of foundry-certified MOS device models.
It is mainly used in analog and digital design, cell and memory characterization, and it is capable of
transient, steady-state, and frequency domain analyses. This is the main professional tool necessary
for the purposes of the developed design flow.
Python™ is a high-level programming language created by Guido Van Rossum. Emphasizing in
high-level built-in data structures, object-oriented programming and modular development that makes
it an ideal platform for managing other programs and fast code development. It is in this programming
language that the main part of the developed characterization design flow is implemented.
Cadence® Virtuoso™ Schematic Editor XL is a schematic-entry tool, that allows the design of inte-
grated circuits on graphical medium. It’s also capable of creating SPICE netlists based on schematic
designs done by the user. It is in this tool that the cells’ testbenches are designed and then extracted as
SPICE netlists.
Synopsys® Custom WaveView™ is a simple waveform visualizer software, exceptionally useful for
testbench debugging and timing verification.
Synopsys® Design Compiler™ is tool useful for circuit synthesis based on verilog models and timing
characterization files.
Finally, Synopsys® Design Vision™ was used to verify the correct syntax of the liberty file.
2.3 Digital Design Flow
The typical design flow of new IC is exhibited in figure 2.1.
The first step within a new project is to write a behavioural model using a Hardware Description Lan-
guage (HDL), examples of these languages are Very High Speed Integrated Circuits HDL (VHDL) and
Verilog. This model describes the general structure and a specific behaviour at a high abstraction level,
allowing Register Transfer Level (RTL) verification of the models. A testbench, which is a environment
to verify the correctness of the model, should be made to evaluate the functionality of the design.
The second step is to synthesize the RTL model to a target technology, using designer defined
restrictions like maximum area, power and time constraints. It is at this phase that library timing char-
acterization files are first useful, as their timing data allows the software to identify critical paths on the
4
VHDL Editing(emacs, vim...)
VHDL RTL models
RTL Synthesisand
Logical Optimization
Floor Planning and
Place & Route
RTL simulation
Final Layout
Design Constraints(e.g. max area)
Post synthesislogic simulation
Timing simulation&
DRC/LVS checks
Design Constraints(Max Area, Power
Consumption, Timing)
Std Cell Library+
Cell Liberty files
VHDL models+
Sub modules Liberty files
LEF and Tech files
GDSII file
File preparation scripts
Figure 2.1: Typical design flow.
synthesized circuits and possible timing violations. The design can then be refined where needed. At
this phase, the circuit design, using a standard cell library, should be obtained. Normally a foundry or IP
company can provide the standard cells that form a digital cell library together with library timing char-
acterization files. Each logic function can be implemented with output transistors with different sizes,
providing different fanout and drive strength capabilities for each cell.
The above mentioned library timing characterization files, contain simulations of the digital library
standard cells in different conditions of temperature, supply voltage, transistor fabrication processes,
input signal slew rate and ouput load capacitance. These different conditions constitute the so called
process corners. The simulations are made in these corners, as a result of the cells’ transistor having
non linear behaviour when they are subject of different input conditions.
After synthesis, logic simulations reusing the testbench used at RTL can be used, to guarantee that
the logic level circuit also performs as expected.
Digital circuits place and route (P&R) can be made automatically using software like Cadence®
Encounter™, needing only the HDL logic description files, the standard cell and the IC sub modules
5
library characterization file, and the Library Exchange Format (LEF) files for the technology and abstract
view.
After generating a new layout using an automatic P&R software, timing simulation, along with Design
Rule Check (DRC) and Layout Versus Schematic (LVS) check, can be run to ensure that the circuit
satisfies the constraints imposed on the first design flow step. This also ensures the circuit adheres to
technology design rules and matches the schematic design.
After P&R, parasitic extraction or Resistance and Capacitance (RC) Extraction can be made. Ide-
ally the interconnections between the standard cells do not affect performance, however a wire has
resistance, capacitance and inductance, therefore a signal that flows through it suffers delay. An RC
extraction generates a Standard Parasitic Exchange Format (SPEF) file. Based on this file and on the
cells’ timing characterization files, it is possible then to generate an Standard Delay Format (SDF) file,
which in turn contains the cells’ delays as well as the delays of their interconnections. The SDF files can
be used for accurate postlayout simulation and backannotation.
Finally, a Graphic Data System II (GDSII) file, a binary format file representing planar geometric
shapes and other layout hierarchical forms, is generated.
2.4 Synopsys Liberty Format
During the design flow, the simulation and P&R software can refer to time characterization files to esti-
mate propagation delay through the different critical and non-critical circuit paths. This characterization
is done based on input slew rate, output load capacitance, temperature, supply voltage, transistor fabri-
cation process, among others. Power consumption can also be included in the liberty files.
Nowadays multiple timing and power file standards exist [8]:
• Synopsys Liberty Format (LIB);
• Timing library Format (TLF);
• Delay and Power Calculation System (DPCS);
• Open Library Architecture (OLA);
• Advanced Library Format (ALF);
Being the Synopsis Liberty format one of the most widely adopted in the industry today, this is the
format chosen to characterize standard cells.
Liberty files have a specific writing syntax [9], and it’s very important that its rules are followed. In
code 2.1, a typical header is presented.
The file is composed of group definitions between curly brackets, the highest hierarchy is the library
definition, composed of attributes on how software should read the file, e.g. the type of delay model
used, signal thresholds during characterization, variable units and operating conditions.
6
Code 2.1: Liberty file library and general parameters definition.library (name) {
technology (name) ; /* library -level attributes */delay_model : generic_cmos | table_lookup | cmos2 |
piecewise_cmos | dcm | polynomial ;bus_naming_style : string;
slew_lower_threshold_pct_fall : value;slew_upper_threshold_pct_fall : value;slew_lower_threshold_pct_rise : value;slew_upper_threshold_pct_rise : value;input_threshold_pct_fall : value;input_threshold_pct_rise : value;output_threshold_pct_fall : value;output_threshold_pct_rise : value;slew_derate_from_library : value;
time_unit : unit ;voltage_unit : unit ;current_unit : unit ;pulling_resistance_unit : unit ;capacitive_load_unit (value , unit) ;leakage_power_unit : unit ;
nom_process : value ;nom_temperature : value ;nom_voltage : value ;
/* default values for environment definitions */
operating_conditions (name) {/* operating conditions */
}lu_table_template (name) {
/* time lookup table template information */}power_lut_template (name) {
/* power lookup table template information */}cell (name1) {/* cell definitions */
/* cell information */}cell (name2) {
/* cell information */}
...
Groups lu_table_template and power_lut_template are particularly important, as they provide
information about the values of input net transition and output load capacitance changed for corner sim-
ulation. Code 2.2 exemplifies these look-up tables. The variable_1 and variable_2 attributes identify
what variable the table contains, index_1 and index_2 contain the values the attributes variable_1 and
variable_2 take.
Code 2.2: Look-up table examples for delay and power characterizationlu_table_template (delay_template_5x5_0) {
variable_1 : input_net_transition;variable_2 : total_output_net_capacitance;index_1 ("0.0001 , 0.0003 , 0.0005 , 0.0006 , 0.0007");index_2 ("0.001 , 0.01, 0.05, 0.1, 0.2");
}
power_lut_template (power_template_5x5_0) {variable_1 : input_transition_time;
7
variable_2 : total_output_net_capacitance;index_1 ("0.0001 , 0.0003 , 0.0005 , 0.0006 , 0.0007");index_2 ("0.001 , 0.01, 0.05, 0.1, 0.2");
}
After the file wide definitions, cell groups are instantiated with their respective attributes, see Code
2.3.
Code 2.3: Cell group general syntaxcell (cellname) {
area : value;cell_footprint : string ;pg_pin (powerpin_1) {
pg_type : string ;voltage_name : string ;
}pg_pin (powerpin_2) {
pg_type : string ;voltage_name : string ;
}
...
pg_pin (powerpin_n) {pg_type : string ;voltage_name : string ;
}
/* leakage power groups */
pin(A) {direction : input | output | inout ;related_ground_pin : powerpin_n ;related_power_pin : powerpin_m ;capacitance : value ;rise_capacitance : value ;fall_capacitance : value ;
/* internal power groups */
/* timing delays groups */
}}pin(B) {
direction : input | output | inout ;related_ground_pin : powerpin_n ;related_power_pin : powerpin_m ;capacitance : value ;rise_capacitance : value ;fall_capacitance : value ;
/* internal power groups */
/* timing delays groups */
}}pin(C) {
...
The cell groups contain information about cell area, leakage power and subgroup definitions for each
pin. The pin subgroups have different parameters based on the direction of the pin. For instance, time
8
Code 2.4: Two dimensional LUT for timing characterizationtiming () {
related_pin : "CLK";timing_sense : non_unate;timing_type : rising_edge;cell_fall (delay_template_5x5) {
index_1 ("0.0001 , 0.0003 , 0.0005 , 0.0006 , 0.0007");index_2 ("0.001 , 0.01, 0.05, 0.1, 0.2");values( " 9.96742e-01, 1.02424e+00, 1.05653e+00, 1.58831e+00, 2.16578e+00",\
" 9.96567e-01, 1.02394e+00, 1.05647e+00, 1.58808e+00, 2.16604e+00" ,\" 9.99196e-01, 1.02739e+00, 1.05870e+00, 1.58857e+00, 2.16837e+00" ,\" 1.03241e+00, 1.05982e+00, 1.09205e+00, 1.62179e+00, 2.19744e+00" ,\" 1.37469e+00, 1.40195e+00, 1.43445e+00, 1.96515e+00, 2.54195e+00");
}
delay measurements are always measured with signal edges of output pins and input pins, so these
type of measurements only appear on pins that have direction attibute set to output.
Every signal pin has a power and ground pin associated with it that can also be indicated. Pin
capacitance in both steady state and in rising and falling situations can also be indicated.
For effectively characterizing a standard cell library, a delay model must be choosen. The delay
model influences the way the liberty file is written. One of the most common structures are liberty files
with a two dimensional timing model [10], this format corresponds to the Non Linear Delay Model, first
mentioned in section 2.1.
Code 2.4 shows a partial delay timing table of the output of a D flip-flop. The timing() group
contains specifications on the conditions the measures are performed. The related_pin attribute
defines the pin or pins that are the starting point of the timing arc. timing_sense indicates if the
transition of the related_pin causes a rise or fall transition on the output, in this case, non_unate
means the output value change cannot be determined with the direction of the change in the input
value. timing_type distinguishes between combinational and sequential cells, as the D flip-flop is a
sequential cell, this attribute simply indicates the output value changes with a rising edge on the clock
(CLK) pin. After the timing attributes are defined, the propagation delay table can be displayed. The
cell_fall(delay_template_5x5) group indicates the clock edge causes a falling edge on the output
and references the look-up table of code 2.2. This indicates the values on the table were measured with
the clock pin transitioning in the time contained in index_1 while the output was connected to a load
capacitance whose value is indicated in index_2. For instance, if the clock edge transitions from high to
low in 0.0005 ns, while the output is connected to a load capacitance of 0.05 pF, the delay between the
rising edge on the input and the falling edge on the output will be 1.0587 ns.
Statistical Timing Analisys (STA) tools use these tables to calculate cell delay. If a particular com-
bination of input net transtition and output net capacitance are not present on the table, the tools can
interpolate the closest values in the tables to obtain an estimation.
9
10
Chapter 3
Liberty File Generation Methodology
To create a methodology, it’s necessary to identify the necessary tasks to characterize a standard cell:
• Design of SPICE testbench;
• Corner simulation in HSPICE;
• Measured data writing in liberty format;
The first task presents a difficult dilemma. Automation facilitates the designers job, saves time during
the characterization process and ensures human error is minimized. However, a script, capable of
automatically creating a testbench for every cell in a digital library, is extremely complex to develop.
The script would need to generate input signal combinations to test how the output reacts, then
deduce the correct cell logic. It would also need to ascertain how the necessary time, power and
capacitance measures could be made. After this, the testbench could be generated and validated.
As this script would be too laborious to write, a method of reusable testbenches was conceived.
With this method, each cell testbench needs to be made and validated manually. However, testbenches
generated for previous libraries can be reused for same logic cells when characterizing new digital
libraries, since the cells functionality and pin names are mantained in all different techologies.
The second and third tasks are more manageable to code and cannot be done manually in a time
sensible way.
3.1 Methodology Description
The methodology developed during the work of this thesis is capable of characterizing a cell’s time,
power and pin capacitance characteristics. It is the direct continuation of the work done in SiliconGate,
concerning digital library characterization. Figure 3.1 shows the developed methodology for character-
izing a standard cell library.
The first thing needed to characterize a standard cell, is a testbench. The testbench is a test environ-
ment for the cell, in it, different input pin stimuli are fed into the cell, and each input signal combination
11
Figure 3.1: Methodology for digital library characterization.
will induce a certain behaviour on the cell’s outputs. If the inputs change their logic state one at a time,
it’s possible to isolate output changes due to a specific input change, this in turn, means that propagation
delay, power consumption and pin capacitance measurements can relate a cell’s outputs with its inputs.
By creating a test environment with multiple combinations of input transitions, it’s possible to evaluate a
cell’s characteristics in a broad range of situations, and with the generated data create a liberty file.
The reusability of testbenches here is important. For instance, suppose there are two digital standard
cell libraries, A and B, and each one of these libraries contains one of the simplest standard cells, an
inverter. An inverter, as the name suggests, inverts the value of its input pin. So if a inverter is fed
with a high/low signal on its input pin, a low/high signal will come out of its output pin. This means that
the inverter in A has the same logic functionality, pin number and pin name as the inverter in library
B. What distinguishes these inverters is the technology with which they are made. This will influence
their propagation delay, power consumption and pin capacitance, among other characteristics, however,
their functionality, remains the same. Therefore, if a testbench is designed to characterize the inverter
from library A, it can be used to characterize the inverter from library B. As these testbenches have to
be made manually, making them reusable is extremely desirable, as this saves time and effort. After a
testbench is designed, it can be stored in a testbench repository, so everytime a new library needs to be
characterized, the propability of having already designed testbenches for its type of cells increases.
The design of the testbench targueting timing measures, power measures and pin capacitance mea-
sures are detailed in chapter 4.
After having our repository updated with all the necessary cell testbenches, gen netlist.py makes a
matchmaking between the cell’s netlist, which is a description of the connections inside a cell, and the
files in the repository directory. If a cell’s schematic is updated, it’s only necessary to reextract the netlist
and rerun the script to have the files ready for simulation.
12
Next, a script manages and launches the corners’ HSPICE simulations. The script can launch the
simulations in multiple Central Processing Unit (CPU) cores, speeding up the total simulation time.
After obtaining the simulation results, the main script for writing liberty files, lib designer.py, can be
run. To facilitate the scripts’ work, a file similar to code 2.1 is used. It contains keywords which the script
can identify and replace with data. These files are called empty liberty shell files.
Chapter 5 details the scripts that allow to automate most of the processes of the proposed method-
ology.
With the liberty files written, it’s necessary to evaluate if they have the correct syntax. Synopsys
Design Compiler is used here, as it can read liberty files and identify if there are mistakes or wrongful
information in the liberty files.
13
14
Chapter 4
Digital Cells Characterization
Testbench
If a new, never before characterized cell is present in a digital library, there are two possible ways to
create its testbench. A new one can be created from scratch, or it can be adapted from an similar one.
Figure 4.1 displays both flows. Here, it’s admitted that the cells’ netlist were extracted from a schematic
editing software, like Cadence® Virtuoso Schematic L.
When a similar cell testbench already exists, i.e. if the similar cell is a D flip-flop with reset pin and
the new cell a D flip-flop with set pin, the majority of signal stimuli and measurement statements can be
adapted with reasonable low effort. As long as the pin count and the input pin functions do not change
in a significant way, the new testbench can be easily created.
After adaptation, one must ensure the measurements are done at the correct time. This can be done
using a signal viewer, like Synopsys Custom WaveView, and the output listing file, *.lis, generated after
a simulation. The output listing file contains detailed information of where in time each measurement is
made, besides warnings and possible errors that can occur. By comparing the .lis file with the signals in
the signal viewer, one can verify if measurements are done at the correct time.
If there are no similar cells, it’s necessary to create a testbench from scratch. The first thing to do is to
design a test schematic like the one in figure 4.2. The inputs are connected to VPWL voltage generators,
and the outputs to capacitors.
By putting the cell in a test circuit, the extracted netlist will have the subcircuit instantiation with the
pins connected correctly, minimizing possible human error.
With the testbench verified, one can break it in three independent files. The header contains param-
eter definitions, type of simulation instantiation and simulation options. The input, contains the stimuli
created by the designer. The footer, contains measures of the cell’s time, power and pin capacitance
characteristics.
The following sections describe each type of measurement made in detail. Section 4.1 presents
the timing measures, section 4.2 explains power, and finally, section 4.3, displays the capacitance.
Throughout the explanations, liberty file code of each measure type is displayed. To end the chapter,
15
Are theresimilar cells?
Adapt timemeasurements
YES
Create Simschematic circuit
(Cadence Virtuoso®)
Extract schematicnetlist
Adapt powermeasurements
Adapt capacitancemeasurements
HSPICESimulationCorrect?NO
YES
Create timemeasurements
Create powermeasurements
Create capacitancemeasurements
HSPICESimulationCorrect? NO
Create generictestbench files
Create libertyshell
Copy files to generictestbenches folder
YES
New Cell XYZNetlist
New CellTestbench
CellTestbench
Created
SimilarCell WXY
HSPICE testbench
NO
HSPICE Simulation Launch
HSPICE Simulation Launch
Figure 4.1: Testbench design flow.
16
Figure 4.2: Blackbox test circuit for a standard cell.
section 4.4 displays HSPICE code example of each type of measures.
4.1 Timing Measures
In this section various forms of timing measurements of logic cells will be discussed, the so called timing
arcs. First, propagation delay and transition times are explained, later, timing measurements specific to
sequential cells, like setup time and hold time are presented.
4.1.1 Propagation Time Delays and Transition Times
Propagation timing delay refers to the time it takes an input pin signal transition to drive the output pin
signal to a certain logic value. For example, with a NAND cell, see figure 4.3, if input A logic value is 1
and input B logic value changes from 1 to 0, the output Y , after a certain ammount of time, transits from
logical value 0 to 1.
Figure 4.4, shows the definition of delay and transition times for logic circuits. The input rise and
fall times are labeled tr and tf , whereas tLH and tHL are the output rise and fall time. tPLH and tPHL
correspond to the propagation delay for the rising and falling edge respectively. The propagation delay
is measured from a 50% value change on the input pin, to a 50% value change on the output pin. The
slew rate, or output transition time, is the time the signal takes to vary from 10% to 90% of the supply
voltage value on a rising edge, while on a falling edge it’s from 90% to 10%, [11].
The propagation delay and slew rate are proportional to the input transition and to the output load. A
slow transition on the input, corresponds to a slow transition at the output. Large values of output load
capacitance lead to an increase in propagation delay.
Due to this reason, the liberty file exhibits propagation delays and timing transitions, as a 2 dimen-
sional table of input net transition versus output net capacitance. Code 4.1, contains the LUT of propa-
gation delay and output slew rate of the D flip-flop output. The pin group contains various attributes, like
pin direction, power down condition, logic function and the related power pins. The max_capacitance at-
tribute refers to the maximum connections this pin can drive with reasonable performance. For instance,
17
Figure 4.3: NAND gate signal delay between input transition and output transition
Figure 4.4: Delay and transition times definition.
if Q pin was connected to the inputs of two other standard cells, and if the summed input capacitance of
both cells surpass 0.2 pF , then Q would probabily provide insufficient current to effectvely drive the two
cells’ inputs.
Code 4.1: Propagation delay and slew rate liberty tables.pin (Q) {
direction : output;power_down_function : !VDD + VSS;function : "IQ";related_ground_pin : VSS;related_power_pin : VDD;max_capacitance : 0.2;timing () {
related_pin : "CLK";timing_sense : non_unate;timing_type : falling_edge;cell_rise (delay_template_5x5_0) {
index_1 ("0.012 , 0.055, 0.078, 0.096, 0.118");index_2 ("0.00041 , 0.00108 , 0.0148 , 0.00258 , 0.00348");values ( "0.02944 , 0.03263 , 0.0374 , 0.04913 , 0.06977" , \
"0.03027 , 0.03345 , 0.03923 , 0.04995 , 0.07065" , \"0.03222 , 0.03537 , 0.04115 , 0.05174 , 0.07256" , \"0.03637 , 0.03949 , 0.04521 , 0.05577 , 0.07656" , \"0.04177 , 0.04514 , 0.05102 , 0.06175 , 0.07249" \
);}rise_transition (delay_template_7x7_0) {
18
index_1 ("0.012 , 0.055, 0.078, 0.096, 0.118");index_2 ("0.00041 , 0.00108 , 0.0148 , 0.00258 , 0.00348");values ( "0.01676 , 0.02112 , 0.0297 , 0.04791 , 0.07594" , \
"0.0169 , 0.02113 , 0.02977 , 0.0479 , 0.08597" , \"0.01677 , 0.02115 , 0.0297 , 0.04794 , 0.08594" , \"0.01725 , 0.02144 , 0.02996 , 0.04792 , 0.07591" , \"0.01924 , 0.02327 , 0.0315 , 0.04886 , 0.07593" \
);}
}}
4.1.2 Timing Violations
Besides propagation delays and slew rates, sequential cells have other types of timing measurements
due to its synchronous nature.
Figure 4.5 represents a D flip-flop with four pins. Three inputs, data (D), clock (CLK) and reset (RST),
and one output (Q). This basic sequential cell is used in the following subsections to exemplify signal
behaviour.
Figure 4.5: D flip-flop with reset pin.
4.1.2.1 Minimum Pulse Width
Minimum pulse width is defined for an input pin as the time between rising edge, at 50% VDD, till falling
edge at 50% VDD for a high signal, that guarantees an output transition. Whereas, for a low signal, it
is the time enclosed by the falling edge at 50% VDD, and the following rising edge at 50% VDD. If such
value is not respected, three situations may arise:
1. The input signal may still be successfully captured;
2. The sequential cell may not react to the change at input, resulting in a invalid signal at output;
3. The sequential cell may go meta-stable.
Figure 4.6 exemplifies the 2nd case where a shorter CLK pin pulse is not able to produce a signal
rise at Q pin.
The minimum pulse width depends, specifically, on the input transition rate, so its liberty file table is
unidimensional. Code 4.2 contains an example for a RST pin timing group. The related_pin attribute
indicates the pin or pins corresponding that are the startpoint of a timing arc. The timing_type attribute
indicates different types of timing in combinational and sequential cells. The sdf_cond is important for
backend annotation, as it allows for Standard Delay Format (SDF) file generation.
19
Figure 4.6: Minimum pulse width time violation.
Code 4.2: Minimum pulse width liberty table.timing () {
related_pin : "RST";timing_type : min_pulse_width;sdf_cond : "nCLK_SDFCHK ";when : "!CLK";fall_constraint (mpw_constraint_template_1x3) {
index_1 ("0.012 , 0.078, 0.118");values ( "0.07324 , 0.08789 , 0.4468" \);
}}
As these simulations take more time to complete, which is explained later in sub-subsection 4.4.1.2,
the input net transition values in index_1 are fewer in this case compared to the LUT of propagation
delay in subsection 4.1.1.
4.1.2.2 Setup Time and Hold Time
Setup time is defined as the time the input needs to be stable before a capturing edge clock. Hold time is
the time the input must remain stable after a capturing clock edge. Figure 4.7 shows the three D flip-flop
pin signals. For this example, the clock edge that captures the logical value on the D pin is the rising
edge. Setup (ts) and hold (th) time are defined with reference to that rising edge and the respective D
pin edge.
As the D pin transition occurs closer to a capture clock edge, the delay between the signal change
in Q pin and the clock edge, will increase until a failure region is reached. In this region, input changes
may not influence the output value.
In figure 4.8, CLK to Q delay, is exemplified with different time intervals between a D pin transition
and the capture clock edge. In figure 4.9 their relation is plotted.
A safe estimation of setup time, can be done, by finding the D to CLK edge time that causes a
10% increase in CLK to Q delay, relative to it’s nominal value. Although tighter values are possible,
20
Figure 4.7: Setup and Hold time definitions.
this cautious approach provides an useful safety margin when characterizing digital cells on its worst
corners. Here, low voltages, slow transistors, high load capacities and extreme temperatures, lead to a
dramatic increase in cell propagation delay.
The hold time calibration methodology is similar, where we consider the same 10% CLK to Q delay
change to the nominal value to determine it.
Code 4.3 exemplifies the setup time LUT on a liberty file. The attributes in the timing group have
already being explained before when codes 4.1 and 4.2 were explained. This is a 2 dimensional LUT
the signal transition time of the analyzed pin versus the transition time of the related pin. However, setup
time and hold time information can also be displayed as a scalar value.
Code 4.3: Setup time liberty table.pin (D) {
direction : input;related_ground_pin : VSS;related_power_pin : VDD;capacitance : 8.82012e-03;rise_capacitance : 8.27858e-03;fall_capacitance : 8.82012e-03;timing () {
related_pin : "CLK";timing_type : setup_rising;sdf_cond : "RST_SDFCHK ";when : "RST";fall_constraint (constraint_template_3x3) {
values( " 2.56348e-01, 2.69563e-01, 6.51680e-02",\" 2.43133e-01, 2.56348e-01, 5.19531e-02" ,\" 6.30633e-01, 5.82812e-01, 4.39453e -01");
}rise_constraint (constraint_template_3x3) {
values( " 1.95312e-01, 2.69563e-01, 1.66766e-01",\" 2.06512e-01, 1.95313e-01, 1.55566e-01" ,\" 4.71941e-01, 4.60742e-01, 1.09863e -01");
}}
21
Figure 4.8: Clock to Q delay for different D pin transitions before and after setup time.
Figure 4.9: Clock to Q delay dependence with D to clock time.
22
As in the minimum pulse width measures, sub-subsection 4.1.2.1, the more complex simulations,
explained later in sub-subsection 4.4.1.3, implies that the number of corners simulated are less so the
LUTs are smaller.
4.1.2.3 Recovery Time and Removal Time
In sequential cells that have asynchronous pins, like set (SET) and reset (RST), besides the timing
measurements specified in sub-subsections 4.1.2.1 and 4.1.2.2, two more forms of time characterization
may be needed.
Recovery time is the time an asynchronous pin signal must be stable before a clock edge, while
removal time is the time such signal must be stable after a clock edge. This ensures situations of
metastability on the output do not occur.
For instance, the D flip-flop in figure 4.5 only asynchronous pin is the RST pin. Therefore, the
recovery time is the minimal time between the deassertion of the reset pin, and a capture clock edge,
that ensures the clock controls the flip-flop. Removal time is the minimum time between an active clock
edge, and the deassertion of the reset pin, that guarantees the clock will not drive the output. Figure
4.10 illustrates this situation, where trc is recovery time and trm represents removal time.
As these timing measurements relate two input pins, their representation on liberty format will be a
two dimensional table of the reference pin input net transition versus the related pin input net transition
as in code 4.4.
The timing group syntax here is similar to code 4.3.
Figure 4.10: Recovery and removal time between a clock and a reset pin.
For the same reason of sub-subsection 4.1.2.2, the size of the LUTs here is smaller than the ones
for propagation delay of subsection 4.1.1.
23
Code 4.4: Recovery and removal time liberty table.timing () {
related_pin : "CLK";sdf_cond : "D_SDFCHK ";timing_type : recovery_rising;when : "D";rise_constraint (constraint_template_3x3) {
index_1 ("0.012 , 0.078, 0.118");index_2 ("0.012 , 0.078, 0.118");values ( \
" -0.07146 , -0.06664, -0.009721" , \" -0.08391 , -0.07818, -0.02348" , \"-0.1419, -0.1383, -0.09912" \
);}
}timing () {
related_pin : "CLK";sdf_cond : "D_SDFCHK ";timing_type : removal_rising;when : "D";rise_constraint (constraint_template_3x3) {
index_1 ("0.012 , 0.078, 0.118");index_2 ("0.012 , 0.078, 0.118");values ( \
"0.1039 , 0.1087 , 0.1674" , \"0.1142 , 0.1181 , 0.1772" , \"0.1645 , 0.1705 , 0.229" \
);}
}
4.2 Power Measures
In cell characterization, power consumption can be divide in two groups, leakage power and dynamic
power. Leakage power is the power the cell consumes when all of its pins are stable, while dynamic
power is the dissipated power when at least one pin is changing its value.
In this section, static power and dynamic power are discussed. What they are, the main causes for
their existence, their mathematical description, and their presentation in liberty format.
4.2.1 Leakage Power
Leakage power is the power a standard cell dissipates when both its inputs and outputs are not making
signal transitions. CMOS technology has the benefit of low power consumption, as only one transistor
of each PMOS and NMOS pair is turned on at each time, this can be better visualized with an example.
Consider the CMOS inverter present in figure 4.11.
When input Y is low, the PMOS device is on and the NMOS is off, this implies that the output YZ is
high. When input Y is high, the PMOS device is off and the NMOS device is on, therefore the output
YZ is low. In these steady states, no current should flow from supply to ground, however, due to the
transistors internal structure, this is not the case.
To measure leakage power in a standard cell, formula 4.1 can be used:
24
Figure 4.11: CMOS Inverter schematic.
Code 4.5: Liberty file leakage power statement example.leakage_power () {value : 2.890951;related_pg_pin : VDD;}leakage_power () {value : 1.855507;when : "!RST !CLK !D !Q";related_pg_pin : VDD;}leakage_power () {value : 2.134887;when : "!RST !CLK D !Q";related_pg_pin : VDD;}leakage_power () {value : 3.564855;when : "!RST CLK !D !Q";related_pg_pin : VDD;}...
PLP =VDD
∫ t2t1IVDD dt
t2 − t1(4.1)
Here VDD is the supply voltage and IVDD is the sum of leakage currents, equation 4.2, which are
explained in this section’s sub-subsections.
IVDD = Ijunc + Iox + Isub (4.2)
Code 4.5 shows how leakage power is presented in liberty syntax. Every pin combination must be
evaluated, the liberty presents the leakage power for each case and their average value. The related
power pin should also be specified.
4.2.1.1 Junction Leakage
The junctions of the p and n diffusion regions in transistors, form parasitic diodes, see figure 4.12. This
parasitic diodes although reverse biased still have a leakage current that contributes to the static power
dissipation of the CMOS devices [12].
The junction leakage current of the diode can be described by equation 4.3:
25
Figure 4.12: CMOS Inverter diffusion junctions parasitic diodes.
Ijunc = is(eqV/kT − 1) (4.3)
Where:
• is is the reverse saturation current;
• q is the electronic charge (1.602× 10−19 C);
• V is the diode terminal voltage;
• k is the Boltzmann’s constant (1.38× 10−23 J/K);
• T is the absolute Temperature in Kelvin;
The magnitude of this current depends primarily on the nwell, source and drain diffusion areas and
on the doping concentration.
4.2.1.2 Gate-Oxide Leakage
Another source of static power consumption has become increasingly important. As the gate size of
CMOS devices decreases every year, in CMOS technology below 90nm, gate oxide tunneling is an im-
portant player in leakage power, as carriers (electrons) can tunnel from the channel to the gate electrode
[13].
The formula 4.4, taken from [14], shows the gate leakage current dependence with oxide thickness:
Iox = K1W
(V
Tox
)2
e−αTox/V (4.4)
Where:
• K1 is an experimental parameter;
• W is the gate width;
• V is the supply voltage;
• Tox is the oxide thickness;
26
• α is an experimental parameter.
It’s clear that an increase in Tox leads to a decrease in leakage current, however, with the scaling
down of transistor size, gate size continues to diminish. New technology like high K dieletrics present a
possible solution to control such problem [15].
4.2.1.3 Subthreshold Leakage
In the last two decades, with the constant miniaturization of transistors and the resulting increase in
power dissipation per chip unit area, the supply voltage has been scaled down. This has been a nec-
essary approach to reduce device operating temperature, while also mantaining an adequate level of
reliability. These measures also lead to a reduction of the threshold voltage (Vth), which has the dis-
advantage of making subthreshold leakage current an important player in static power consumption of
integrated circuits [16].
Isub = K2We−Vth/nVθ(1− eV/Vθ
)(4.5)
Formula 4.5 taken from [14] shows the negative exponential dependance of the subthreshold leakage
current with the threshold voltage, where:
• K2 and n are experimental parameters;
• W is the gate width;
• V is the supply voltage;
• Vth is the threshold voltage;
• Vθ is the thermal voltage.
Vθ increases linearly with temperature, so if Isub rises enough to build heat, Vθ will rise and so Isub
will rise also. Note however the exponential dependence with Vth, with suggests that small threshold
voltages induces a large subthreshold leakage current.
4.2.2 Dynamic Power
Dynamic power is obtained by adding switching power consumption (PSW ), and internal power con-
sumption (PI ). Being this the total power, it can be calculated as energy by:
Etot =∫ t2
t1
VddIVdd dt (4.6)
4.2.2.1 Switching Power Consumption
When an input logic change drives an output pin, it will also charge or discharge an external load. In
a circuit, this corresponds to the input pin load of other cells. For characterization purposes, the output
27
load is replaced by a capacitor whose value, during characterization, is chosen according to typical cell
fan-out. Most of the power consumed by a CMOS circuit is due to the charge and discharge cycles of
this output load.
The characteristic formula of a capacitor can be given by:
I = Cdvdt
(4.7)
Using formula 4.7, the switching energy can be written as:
Esw =∫ t2
t1
VDDIsw =∫ VDD
0
CVDD dv =12CV 2
DD (4.8)
Where C is the output load capacitance and Vdd is the supply voltage;
4.2.2.2 Internal Power
Internal power not only represents charging and discharging power of the cells’ internal nets, but also
power that is wasted due to momentary turn on of NMOS and PMOS network that connects the cells’
supply and ground pins. Depending on the supply voltage, this value can be rather negligible compared
with the necessary energy to change the exterior load of the cell. In complex cells however, with a high
transistor count like flip-flops, the power consumed by the internal circuitry can be meaningful and power
characterization should be made even for non output changing transitions.
The internal power can be obtained by using equations 4.6 and 4.8:
EI = Etot − Esw =∫ t2
t1
VddIVdd dt− 12CV 2
dd (4.9)
By summing both switching energy and internal energy we get the total dynamic energy consumed
by a cell:
ED = Esw + EI (4.10)
Code 4.6 is an example of a liberty file representing the situation where an input transition does not
drive the output. Attributes indicating other pins logic states, and related power pin can be presented.
The power consumption when the analyzed pin is rising or falling can be different, so each situation has
its own table.
The LUT is unidimensional, as power depends only on the input pin transition time.
When an input pin transition can drive the output, the structure is similar to the timing tables presented
in subsection 4.1.1. Code 4.7 displays exactly this situation.
Here the input pin transition leads to an output transition, the power now will not only depend upon the
rise or fall transition of the input, but also on the load capacitance of the output, therefore a 2 dimension
table is required. When a rising or falling edge of an input pin is not supposed to drive a logic transition,
no matter the other inputs’ combination, the liberty should have a note saying the value is scalar and
power consumption is equal to 0. The power dissipation is also dependent on other input pins logic
28
Code 4.6: Power consumption for non-output transition...internal_power () {
when : "!CLK&!D&!Q";related_pg_pin : VDD;rise_power (passive_power_template_5x1_0) {
index_1 ("0.0012 , 0.0055 , 0.078, 0.096, 0.118");values ( \
" -0.00141 , -0.001477 , -0.001499 , -0.00151, -0.001515" \);
}fall_power (passive_power_template_5x1_0) {
index_1 ("0.0012 , 0.0055 , 0.078, 0.096, 0.118");values ( \
"0.001523 , 0.001533 , 0.001532 , 0.00153 , 0.001528" \);
}}...
Code 4.7: Power consumption for output transition.internal_power () {
related_pin : "CLK";related_pg_pin : VDD;rise_power (power_template_5x5_0) {
index_1 ("0.0012 , 0.0055 , 0.078, 0.096, 0.118");index_2 ("0.00041 , 0.00108 , 0.0148 , 0.00258 , 0.00348");values ( \
"0.005489 , 0.005501 , 0.005535 , 0.005579 , 0.005632" , \"0.00549 , 0.005502 , 0.005536 , 0.005582 , 0.005634" , \"0.005487 , 0.005499 , 0.005531 , 0.005577 , 0.005631" , \"0.005491 , 0.005503 , 0.005533 , 0.005581 , 0.005634" , \"0.005515 , 0.005528 , 0.005563 , 0.005606 , 0.005656" \
);}fall_power (power_template_5x5_0) {
index_1 ("0.0012 , 0.0055 , 0.078, 0.096, 0.118");index_2 ("0.00041 , 0.00108 , 0.0148 , 0.00258 , 0.00348");values ( \
"0.005154 , 0.005161 , 0.005196 , 0.00526 , 0.005316" , \"0.005158 , 0.005172 , 0.005212 , 0.005266 , 0.005312" , \"0.005155 , 0.005174 , 0.005214 , 0.00526 , 0.005316" , \"0.005153 , 0.005171 , 0.005212 , 0.005261 , 0.005307" , \"0.005156 , 0.005176 , 0.005218 , 0.00526 , 0.005313" \
);}
}
29
Code 4.8: Libety File input pin capacitance definitions.pin (RSTZ) {
direction : input;related_ground_pin : VSS;related_power_pin : VDD;capacitance : 5.86744e-03;rise_capacitance : 5.86744e-03;fall_capacitance : 4.27833e-03;...
states’, as this may vary the different electric paths an logic change on the input pin of interest may or
may not affect.
4.3 Pin Capacitance
The input pin capacitance can be measured on rise and on fall transitions that causes output pin transi-
tions. Using equation 4.7, we can obtain:
C =
∫ t2t1Irise/fall dt
Vdd(4.11)
Code 4.8 contains examples of pin capacitance definitions. Rise and fall capacitance correspond to
the average value of the measures through the different input net transitions and output load capaci-
tances, while the capacitance attribute is the largest of them both.
4.4 HSPICE Example Code
The following sections contain HSPICE code examples for time, power and pin capacitance measure-
ments.
4.4.1 HSPICE Timing Code Examples
In this subsection, some HSPICE code samples of the D flip-flop described in subsection 4.1.2, and
illustrated in figure 4.5 are presented.
4.4.1.1 Propagation Time and Transition Time HSPICE Code
Propagation time and timing transitions require few commands to measure, and such simplicity permits
a complete characterization within a single transient analysis.
Propagation delay and output transition time are measured on a D flip-flop in two situations. The first,
the D pin (vin1) is high, so a rising clock edge (vin2) drives the output (vout1) to high. The second, the D
pin is low, so a rising clock edge drives the output(vout1) to low. Code 4.9 exemplifies these situations.
Code 4.9: Propagation delay measure statements.* Timing Arcs
30
* Output: vout1* First case vin2
* Rise delay vout1_vin2_vin1_vin3.measure tran cell_rise_vout1_vin2_vin1_vin3 trig v(vin2) val = ’0.5*avddpar ’ td
=p_width rise=3 targ v(vout1) val = ’0.5*avddpar ’ td=trig rise = 1
* Rise time vout1_vin2_vin1_vin3.measure tran rise_transition_vout1_vin2_vin1_vin3 trig v(vout1) val = ’0.1*
avddpar ’ td=p_width rise=1 targ v(vout1) val = ’0.9*avddpar ’ td=trig rise =1
*------------------------------------------------------------------------------* Second case vin2
*Fall delay vout1_vin2_!vin1_vin3.measure tran cell_fall_vout1_vin2_!vin1_vin3 trig v(vin2) val = ’0.5*avddpar ’
td=p_width rise=4 targ v(vout1) val = ’0.5*avddpar ’ td=trig fall = 1
* Fall time vout1_vin2_!vin1_vin3.measure tran fall_transition_vout1_vin2_!vin1_vin3 trig v(vout1) val = ’0.9*
avddpar ’ td=p_width fall =1 targ v(vout1) val = ’0.1*avddpar ’ td=trig fall =1
The testbenches contain pin state information in it’s variable names to facilitate liberty file writing later
on. With this system, the script can write in which situation the measure was taken.
4.4.1.2 Minimum Pulse Width HSPICE Code
An iterative analysis is required for the determination of this parameter. For instance, the Bisection
Methodology is an optimization method that uses a binary search to find the target value of an input
variable, which is associated to a goal value of an output variable [17]. Due to its iterative nature. it’s a
much more complex, time and memory consuming simulation than the one explained in sub-subsection
4.4.1.1, therefore increasing substantially the amount of resources needed to fully characterize a se-
quential cell.
Code 4.10 shows a parameter that is changed (width decrease). It shrinks the D flip-flop clock pin
pulse width, while another variable (Maxvout) is analyzed.
Code 4.10: Minimum pulse width measurement optimization definition.PARAM width_decrease=Opt ( low_est , low_est , high_est).MODEL OptMod Opt itropt =30 Method = Bisection.TRAN time_step end_sim Start=t1 Sweep Optimize=Opt Result=Maxvout Model =
OptMod
The last measure where Maxvout achieves 90 % of VDD is considered the minimum pulse width, i.e.
the last situation where an output transition occurs. Code 4.11 contains the HSPICE measure statement.
Code 4.11: Minimum pulse width measure statement..measure tran min_width_rise_vin2_vin2_vin1_vin3 trig v(vin2) val = ’0.5*avddpar
’+ td=’p_width/2’ rise=3 targ v(vin2) val = ’0.5*avddpar ’ td=’p_width/2’ fall=3.measure tran Maxvout Max v(vout1) GOAL = ’0.9* avddpar ’ FROM=t15 TO=end_sim
Again the variable contains the state of other pins, to facilitate the liberty writing process.
31
4.4.1.3 Setup and Hold Time HSPICE Code
To calculate setup time using the method described in 4.1.2.2, the time between the data pin transition
and the clock pin transition is first established by a golden value, Tclk2q in figure 4.9. In this initial situation
the D pin shifts far earlier than the capture clock edge, thus ensuring the D flip-flop internal circuitry is
ready with the right D pin logical value when the clock edge arrives. HSPICE then makes a binary
search for the D-to-CLK delay that corresponds to a 10 % increase to the CLK-to-Q delay, 1.1Tclk2q, of
the golden value.
The different approach used to calculate these timing characteristics required a different type of
HSPICE transient analysis, the so called Pushout Passfail Methodology. This ends up being a optimiza-
tion problem like the one in sub-subsection 4.4.1.2.
Code 4.12 displays the optimization done on the transient analysis. A variable changes the time sep-
aration between the CLK and D pin transition, setup delay. The clk to q delay is the variable analyzed
to detect the 10 % delay increase, between output and clock.
Code 4.12: Setup time measurements optimization definition..PARAM setup_delay=Opt ( low_est , low_est , high_est).MODEL OptMod OPT METHOD=PASSFAIL RELOUT = 0.1 close = 1.5 cut = 4.TRAN time_step end_sim Start=t1_1 Sweep Optimize=Opt Result=clk_to_q_delay
Model=OptMod
The code in 4.13 shows HSPICE statements where. A 10 % change in the variable clk_to_q_delay
is used to determine the setup_time_rise_vin1_vin2_vin3.
Code 4.13: Setup time measurement values..measure tran setup_time_rise_vin1_vin2_vin3 trig v(vin1) val = ’0.5*avddpar ’+ td=’p_width/2’ rise=1 targ v(vin2) val = ’0.5*avddpar ’ td=’p_width/2’ fall=3.measure tran clk_to_q_delay trig v(vin2) val = ’0.5*avddpar ’ td=’p_width/2’+ rise=3 targ v(vout1) val = ’0.5*avddpar ’ td=’p_width/2’ rise=1 pushout_per =0.1
lower
4.4.1.4 Recovery and Removal Time HSPICE Code
Recovery and removal time, like the Minimum Pulse Width HSPICE code described in sub-subsection
4.4.1.2, use the Bisection Method to be determinated. Unlike the latter, however, the parameter that
varies, (delay ), changes the time interval between the reset pin deassertion and the capture clock edge,
see code 4.14 and 4.15.
Code 4.14: Recovery and Removel time general measurements optimization definition..PARAM delay=Opt ( low_est , low_est , high_est).MODEL OptMod Opt Method = Bisection.TRAN 1e-14 end_sim Start=t1_1 Sweep Optimize=Opt Result=Maxvout Model = OptMod
Code 4.15: Recovery and Removal time general measurements values..measure tran recovery_time_rise_vin3_vin2_vin1 trig v(vin3) val = ’0.5*avddpar ’+ td=’p_width/2’ rise=1 targ v(vin2) val = ’0.5*avddpar ’ td=’p_width/2’ rise=3.measure tran Maxvout Max v(vout1) FROM=t12_2 TO=end_sim GOAL = ’0.9* avddpar ’
32
Code 4.16: HSPICE leakage power measure statements..measure average_i_llll INTEG i(v2)+ from=leak_llll_1 to=leak_llll_2.measure e_leak_llll param=’avddpar*average_i_llll ’.measure power_leak_llll param=’e_leak_llll /( leak_llll_2 -leak_llll_1)’
.measure average_i_llhl INTEG i(v2)+ from=leak_llhl_1 to=leak_llhl_2.measure e_leak_llhl param=’avddpar*average_i_llhl ’.measure power_leak_llhl param=’e_leak_llhl /( leak_llhl_2 -leak_llhl_1)’
.measure average_i_llhh INTEG i(v2)+ from=leak_llhh_1 to=leak_llhh_2.measure e_leak_llhh param=’avddpar*average_i_llhh ’.measure power_leak_llhh param=’e_leak_llhh /( leak_llhh_2 -leak_llhh_1)’
...
* Average static (leakage) power.measure power_leak_static param=’( power_leak_llll + power_leak_llhl +
power_leak_llhh + ...)/12’
D CLK RST QL L L LL L H LL L H H... ... ... ...
Table 4.1: Input and Output logic combinations for leakage power.
4.4.2 HSPICE Power Code Examples
In this subsection, examples of power measurements HSPICE code are given. Their measures are
made in parallel with the ones on subsection 4.1.1.
In the following sub-subsections a brief description of the HSPICE alongside short examples are
given.
4.4.2.1 Leakage Power HSPICE Code
Static power characterization requires measuring current when the signals in all pins have completely
settled. Employing large intervals of time between signal changes, increases the measures precision.
Following the formulas 4.1 and 4.2, leakage power can be measured at specific times, where the pin
logic combination matches specific pin states. See code 4.16.
The variable naming convention here needs to indicate which combination of inputs we have, and for
the D flip-flop of figure 4.5, table 4.1 exemplifies how the system works.
Comparing table 4.1 with the variable names on code 4.16, the pin logic combination is written on
each name, following a specific order in a way that will facilitate the liberty file writing.
4.4.2.2 Dynamic Power HSPICE Code
Dynamic power has two different situations when it can be measured. When there is output pin transition
and when there is no output pin transition.
33
Code 4.17: HSPICE dynamic power measurement statements.* Internal power for output pin transitions
* vout1* First case vin2
* Rise power vout1_vin2_vin1_vin3_vin4
.measure t1_rise_vout1_vin2_1 when v(vin2) = ’0.9*avddpar ’ fall = 3+ td = p_width.measure t2_rise_vout1_vin2_1 when v(vout1) = ’0.9*avddpar ’ rise = 1+ td = p_width.measure tran charge_rise_vout1_vin2_1 integral par(’-i(v2)’)+ from = ’t1_rise_vout1_vin2_1 ’ to = ’t2_rise_vout1_vin2_1 ’.measure ipower_rise_vout1_vin2_vin1_vin3_vin4 param = ’charge_rise_vout1_vin2_1
*avddpar ’
* Fall power vout1_vin2_!vin2_!vin3_vin4
.measure t1_fall_vout1_vin2_1 when v(vin2) = ’0.9*avddpar ’ fall = 4+ td = p_width.measure t2_fall_vout1_vin2_1 when v(vout1) = ’0.1*avddpar ’ fall = 1+ td = p_width.measure tran charge_fall_vout1_vin2_1 integral par(’-i(v2)’)+ from = ’t1_fall_vout1_vin2_1 ’ to = ’t2_fall_vout1_vin2_1 ’.measure ipower_fall_vout1_vin2_vin1_vin3_vin4 param = ’charge_fall_vout1_vin2_1
*avddpar ’
*-------------------------------------------------------------------------------* First case vin3
...
In code 4.17, the first measure of pin vin2, (CLK), a falling edge of the clock induces a rising edge on
the output pin, therefore the current is integrated between falling clock pin signal at 90 % supply value
until rising output pin signal at 90 % supply value.
By multiplying the current with the supply voltage, (avddpar ) we obtain the energy.
Code 4.18: HSPICE non-output transition power measurement statements.* Rise power vin2_vin1_vin3_vout1_!vout2
.measure t1_rise_vout1_vin2_1_n when v(vin2) = ’0.1*avddpar ’ rise = 4+ td = non_trans2.measure t2_rise_vout1_vin2_1_n when v(vin2) = ’0.9*avddpar ’ rise = 4+ td = non_trans2.measure tran charge_rise_vout1_vin2_1_n integral par(’-i(v2)’)+ from = ’t1_rise_vout1_vin2_1_n ’ to = ’t2_rise_vout1_vin2_1_n ’.measure ipower_rise_vin2_vin1_vin3_vout1_!vout2_1_n param = ’
charge_rise_vout1_vin2_1_n*avddpar ’
* Fall power vin2_vin1_vin3_vout1_!vout2
.measure t1_fall_vout1_vin2_1_n when v(vin2) = ’0.9*avddpar ’ fall = 4+ td = non_trans2.measure t2_fall_vout1_vin2_1_n when v(vin2) = ’0.1*avddpar ’ fall = 4+ td = non_trans2.measure tran charge_fall_vout1_vin2_1_n integral par(’-i(v2)’)+ from = ’t1_fall_vout1_vin2_1_n ’ to = ’t2_fall_vout1_vin2_1_n ’.measure ipower_fall_vin2_vin1_vin3_vout1_!vout2_1_n param = ’
charge_fall_vout1_vin2_1_n*avddpar ’
...
*-------------------------------------------------------------------------------
34
Code 4.19: Pin capacitance measurement statements....* Pin vin2 rise capacitance
.measure rise_cap_vin2_1 param = ’abs(charge_rise_vout1_vin2_1/avddpar)’* Pin vin2 fall capacitance
.measure fall_cap_vin2_1 param = ’abs(charge_fall_vout1_vin2_1/avddpar)’* Pin vin3 fall capacitance
.measure fall_cap_vin3_1 param = ’abs(charge_fall_vout1_vin3_1/avddpar)’
.measure fall_cap_vin3_2 param = ’abs(charge_fall_vout1_vin3_2/avddpar)’
.measure fall_cap_vin3_3 param = ’abs(charge_fall_vout1_vin3_3/avddpar)’
.measure fall_cap_vin3_4 param = ’abs(charge_fall_vout1_vin3_4/avddpar)’
...
The second example above shows the power measurement when there are no output transition,
consequently current is integrated only during the input transition.
In both cases the variable names indicate what the measure, which pin is being analyzed and what
are the other pins logic states during such measures.
4.4.3 HSPICE capacitance code example
The measures used to calculate power consumption in sub-subsection 4.4.2.2, can now be applied for
calculating capacitance. This has the advantage of measuring pin capacitance while taking into account
the other pin states.
The code that measures pin capacitance is displayed in 4.19.
4.5 Testbench Repository
After creating the testbench for the new cell, its files can be added to a testbench repository, whose
directory tree is similar to code 4.20. This constitutes our generic testbench database. As stated in
the beggining of the chapter, the testbench is divided in three files. The header contains the type of
simulation and parameters definitions. The input contains the stimuli, i.e. the different transitions the
inputs do during simulation. The footer contains all the measurement statements. The codes presented
in section 4.4 are examples of parts of each file, while appendix A contains a complete header, input
and footer file from a NAND2 testbench.
35
Code 4.20: Generic testbench directory tree..‘-- generic_netlist|-- _and2| ‘-- comb| |-- footer.cfg| |-- header.cfg| ‘-- input.ckt|-- _nand2| ‘-- comb| |-- footer.cfg| |-- header.cfg| ‘-- input.ckt|-- _dffnr| |-- comb| | |-- footer.cfg| | |-- header.cfg| | ‘-- input.ckt| ‘-- seq| |-- footer_hold_time_vin1_1.cfg| |-- footer_setup_time_vin1_1.cfg| |-- header_hold_time_vin1_1.cfg| |-- header_setup_time_vin1_1.cfg| |-- input_hold_time_vin1_1.ckt| ‘-- input_setup_time_vin1_1.ckt‘-- _or2‘-- comb|-- footer.cfg|-- header.cfg‘-- input.ckt
...
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Chapter 5
Methodology Automation Scripts
In this chapter the scripts used in the methodology are presented. How they manage the HSPICE
simulations and how they write the liberty files is explained.
Figure 5.1 contains the general tasks the different scripts execute in order to write liberty files, where
the colored boxes denote different scripts.
Figure 5.1: Methodology automation scripts’ tasks
All three scripts are intertwined by the files they generate. gen netlist.py is responsible for concate-
nating cell’s netlist with a testbench from the generic repository, lib maker.py uses a configuration file
and the generated testbenches from gen netlist.py to run and manage the HSPICE simulations and
37
lib designer.py is responsible for writing the liberty files. The following sections will explain more thor-
oughly each script’s functionality.
5.1 Netlist and Testbench Generation - gen netlist.py
Although automation of testbench design was not deemed necessary, automation of the reusable test-
benches with the respective cells’ netlist can be executed. To simplify coding, the cell cannot be directly
extracted from its schematic. Instead it must be inserted in a simulation circuit, with pulse generators
connected to its input pins and capacitors to the output pins. The script can them simply modify these
test circuit parameters to create an usable testbench.
The general work flow of the script is displayed in figure 5.2. Cadence Virtuoso Schematic L soft-
ware creates a specific folder directory when extracting a cell’s netlist, e.g. /home/Users/username/BA-
SICLIB/Sim/cell name/hspiceD/tr func/netlist/. By providing the script with the first half of the path, until
the library name BASICLIB, it lists all the cells in the library folder and matches their names with the
existing testbenches in the repository of code 4.20. If a match is found, the script copies the files to the
path indicated above and concatenates the cells’ netlist with them.
With this script, the user can freely change each and every cell netlist anytime it’s needed, only being
necessary to run the script again to ensure that the following script uses up-to-date cell testbenches in
it’s simulations.
5.2 Automatic Spice Simulation Management - lib maker.py
After the testbench matchmaking process, lib maker.py takes over. This is the main script of the method,
and it’s run in the following manner:
$ ./lib maker.py ’path netlist folder’ ’path empty lib shells’ ’execution path’
Where ’path netlist folder’ is the digital library folder, in which its cell’s directories contain the re-
spective netlists, e.g. ”/home/Users/username/BASICLIB/Sim/”, ’path empty lib shells’ is the directory
containing the empty shell liberty files, which are explained later in section 5.3 and ’execution path’ is
where the simulations are run and the liberty files are created.
The Python package ConfigParser is used to parse the configuration file, see code 5.1.
The configuration file is divided in sections lead by a [section_name] header. The [DEFAULT] sec-
tion contains the general configuration, like the simulation folder name and the number of threads and
computer cores the program can use. Paths to the digital library folder, the generic testbench repository
and the file containing technology models are also here defined. The [CTE_PAR] section consists of sim-
ulation parameters that do not change in any corner, as an example, p_width is the minimum time an
input signal remains constant. Section [ALTER_LIB_PAR] contains corner parameters whose information
are in the path indicated in the [DEFAULT] section, for instance, processes refers to different MOS tech-
nology parameters. The [ALTER_GEN_PAR] section contains the variables to be changed during corner
38
Figure 5.2: Flowchart of genNetlist script.
simulations. The nom_temp indicates the operating temperature, avddpar the supply voltage, outcap the
output load capacitance value, and t_tran the time the input signals take to rise or fall.
After the instantiation of this config file lib maker’s subscripts can run. Each subsection will describe
the functionality of each script.
5.2.1 Alter Creation - alter creator.py
HSPICE has the useful feature of running consecutive simulations, varying one or multiple parameters
each time. The so called alter statement (.ALTER) has the ability to modify parameters and after each
change, rerun the simulation saving the results to .mt files. These alter statements can be written directly
on each cell testbench, but this approach besides cluttering the testbench files, ends up being memory
hungry when dealing with a lot of cells and corners.
Submodule alter creator.py is the one responsible for alter creation. By receiving the information
contained in sections [ALTER_LIB_PAR] and [ALTER_GEN_PAR] of the configuration file, the script is able
to create all the possible parameter combinations. The alter files have a strucure similar to code 5.2.
The used approach, displayed in figure 5.3, lets the number of alter files change with the number of
39
Code 5.1: Simulation general configuration file.[DEFAULT]
simFolder = hspiceSimcellKeyword = BASICLIBmaxThreads = 1maxCores = 3genNetPath = /home/User/username/generic_netlistcadFolder = /home/User/username/simulation_folder/modelFolder = /home/User/username/tech/hspice.lib[CTE_PAR]
p_width = 50#[p_width] = ns[ALTER_LIB_PAR]
processes = mos_tt,mos_ff,mos_fnsp,mos_snfp
[ALTER_GEN_PAR]
nom_temp = -40,25,125#[nom_temp] = ◦Cavddpar = 0.88,1.62,1.8#[avddpar] = Voutcap = 0.001,0.01,0.2#[outcap] = pFt_tran = 0.0001,0.01,1#[t_tran] = ns
processors the user chooses to use and so, to ensure all corners are simulated, these alter files must
be created without repeating corner combinations in eachother. Code 5.3 reflects the alter file structure
created inside the ’execution path’ indicated when running lib maker.py. In this example, there are 81
corners for measuring propagation delay, power consumption and capacitance, 9 corners for minimum
pulse width and 27 corners for setup, hold, recovery, and removal time.
Figure 5.3: Flowchart Script.
The script can create three different types of alter files. The first type, which 5.2 exemplifies, is
used for time delay and power consumption measurements and are named, the second type is used for
minimum pulse width time violation estimation and the third type is used for setup, hold, recovery and
removal time verifications. This is necessary as each type of measurement requires different parameters
combinations to produce its corners.
Code 5.2: Alter file example.ALTER 1.LIB "/home/User/username/tech/hspice.lib" mos_tt
40
.LIB "/home/User/username/tech/hspice.lib" pre_lay_sim
.TEMP 25
.PARAM avddpar =1.62
.PARAM t_tran =0.0001n
.PARAM outcap =0.001p*******************************************************.ALTER 2.TEMP 25.PARAM avddpar =1.62.PARAM t_tran =0.0001n.PARAM outcap =0.005p*******************************************************.ALTER 3.........
5.2.2 Simulation File Preparation - nhfi thread.py
After creating the simulation folder and the different alter files, the script needs to prepare the simulation
files. A separate folder, whose name can be defined by the designer on the configuration file, is created
inside the simulation folder. This folder, for example, hspiceSim, will contain a tree structure like the
one presented in code 5.3. It’s based on the alter files with termination .inc inside the simulation folder,
created by the previous submodule alter creator.py, that this module will create the subfolders inside
each cell directory.
The alter files with name ”alter seq*” are exclusive to sequential cells, that is why, only the D flip-flop
cell contains folder with names like that.
Code 5.3: Simulation folder directory tree..|-- alter1_25.inc|-- alter26_50.inc|-- alter51_75.inc|-- alter_seq1_1_3.inc|-- alter_seq1_4_6.inc|-- alter_seq1_7_9.inc|-- alter_seq2_10_18.inc|-- alter_seq2_19_27.inc|-- alter_seq2_1_9.inc‘-- hspiceSim|-- BASICLIB_nand2| |-- alter1_25| |-- alter26_50| ‘-- alter51_75|-- BASICLIB_dffnr| |-- alter1_25| |-- alter26_50| |-- alter51_75| |-- alter_seq1_1_3| |-- alter_seq1_4_6| |-- alter_seq1_7_9| |-- alter_seq2_10_18| |-- alter_seq2_1_9| ‘-- alter_seq2_19_27|-- BASICLIB_cell3| |-- alter1_25... ... ...
41
The Python package multithreading is used to create these folders and copy the simulation files to
their respective locations. This package allows the launch of concurrent workers that execute multiple
tasks using the same memory place. The major hazard of sharing memory occurs when two or more
workers try to write data at the same time and in the same place. The global interpreter lock is a feature
of this module that solves that situation, by allowing only one worker to write data in a memory space
at any given time. This limitation implies that CPU bound tasks perform poorly and can be even slowed
down by multithreading. I/O bound tasks on the other hand can take full advantage of this module. As
the task of copying and then editing the testbenches belongs to the latter group, multithreading can make
an impact, particularly when dealing with large number of cells and/or alter files.
5.2.3 Multicore Simulation Management - hsp thread.py
HSPICE has a built-in functionality for multithreading/multicore simulations, which is optimum for com-
plex circuits where the overhead time of preparing the simulation is small compared to the time for
actually running it. Nonetheless, when dealing with small simple simulations like standard cells, this
HSPICE option ends up being extremely slow due to it’s large overhead time.
In an attempt to speed up simulation time, a custom task manager script was created, hsp thread.py.
The initial idea was to use Python’s multithreading package, however, as HSPICE simulations are es-
sentially CPU bound tasks, multithreading did not perform well in this case.
On the other hand, Python’s multiprocessing tries to avoid the limitations of the multithreading module
by using processes, i.e. each worker created runs in a separate memory location and the module is
capable of taking full advantage of multiple processors on a machine.
To illustrate the difference between Python’s multithreading and multiprocessing, figure 5.4, shows
two sets of graphs. Graphs 5.5(a) and 5.5(b) show a function that makes Python sleep for 2 seconds.
Graphs 5.5(c) and 5.5(d) shows a function that makes a large sum. Each function is run 15 times using
5 workers.
Although when idle both display a similar behaviour, when executing a task it’s clear that the multi-
processing package is faster than the multithreading. For the CPU intensive HSPICE simulations, this
substantially speeds up simulation time, but at a cost of increased memory and HSPICE license use.
With the developed task manager, each processor simulates a different alter file, and the corners are
evenly distributed across the alter files. The same cell can have multiple corners of the same LUT table
simulated by different processors.
After running the simulations, the cell’s alter directories will have .mt# files with the simulations re-
sults. These are copied one step above in the hierarchy and the .mt number is adjusted to reflect the
alter folder they were in. After this, the measures are ready to be written to a liberty file by the next script.
The hspiceSim folder from code 5.3 has now changed, to look similar to code 5.4.
.
42
Code 5.4: hspiceSim directory tree after simulations..|-- BASICLIB_and2| |-- alter1_25| | |-- ...| | |-- input.mt1| | |-- input.mt2| | |-- input.mt3| | |-- ...| | ‘-- input.mt25| |-- alter26_50| | |-- ...| | |-- input.mt26| | |-- input.mt27| | |-- input.mt28| | |-- ...| | ‘-- input.mt50| ‘-- alter51_75| |-- ...| |-- input.mt51| |-- input.mt52| |-- input.mt53| |-- ...| ‘-- input.mt75|-- BASICLIB_dffnr| |-- alter1_25| | |-- ...| | |-- input.mt1| | |-- input.mt2| | |-- input.mt3| | |-- ...| | ‘-- input.mt25... ... ...
43
(a) Idle Threads (b) Idle Processes
(c) Busy Threads (d) Busy Processes
Figure 5.4: On top graphics depicting the work time of 5 idle threads and 5 idle processes. At the bottomgraphics depicting the work time of 5 busy threads and 5 busy processes processes. Permission toreproduce these images granted by Nathan Grigg [18]
5.3 Liberty File Writing - lib designer.py
The third and last script is responsible for writing the simulation data into the liberty file. This script
needs to sort the simulation data and write them in the appropriate fields. Here, one of Python’s basic
variables is essential for the script’s functionality. Python’s dictionaries are useful data structures whose
data, although not sorted by indexes like Python’s list or other programming languages’ arrays, can be
acessed via keys and not by their position. This makes their structures especially useful for databases.
The script requires that the testbench uses a standarized variable naming scheme. This is useful to
identify the type of measure, the input pin that causes a transition and the output pin that is affected.
Facilitating the writing of the liberty file.
An interesting concept this script uses is that of empty liberty file shells. Like the general testbenches
described in chapter 4, liberty shells are created manually and can be used across similar cells of
different technologies. The shell is custom made for each cell, although they do share similarities.
Appendix B contains a liberty file shell for the D flip-flop of figure 4.5. A keyword system is used to
facilitate completion of the liberty file. Keywords that can be substituted with simulation values or cell
specific information are indicated inside < and > symbols. The script will look for keywords on the
simulation results or in a cell configuration file that contains cell specific parameters.
The following sub-sections will describe the scripts written to automize the writing process.
44
5.3.1 Mt files indexation - index creator.py and alt permuter.py
The indexation of the simulation data in a way that facilitates the creation of the liberty files, is the more
complex part of the automatic flow. The submodule index creator.py creates a dictionary where the keys
are the corner process and the values are the .mt files numbers, as in code 5.5
Code 5.5: Simulation parameter based indexation.genIndex = {...’mos -tt_0p8v_25_0p0001_0p0001 ’ : 10,’mos -tt_0p8v_25_0p0001_0p01 ’ : 11,’mos -tt_1p8v_25_0p0001_1 ’ : 12,’mos -tt_0p8v_25_0p01_0p0001 ’ : 13,’mos -tt_0p8v_25_0p01_0p01 ’ : 14,’mos -tt_0p8v_25_0p01_1 ’ : 15,’mos -tt_0p8v_25_1_0p0001 ’ : 16,’mos -tt_0p8v_25_1_0p01 ’ : 17,’mos -tt_0p8v_25_1_1 ’ : 18,’mos -tt_1p62v_25_0p0001_0p0001 ’ : ......}
Different indexing dictionaries are created for each of the three types of alter files, as they have
different parameter combinations.
As it was explained in chapter 4, the look-up tables change in accordance with the data they want
to convey, e.g. code 4.1, which is a two dimensional table, or e.g. code 4.2, an one dimensional
table. These tables can be made more easily if the data of dictionary 5.5 is grouped in more complex
dictionaries. See code 5.6.
Code 5.6: Group indexation based on look-up table construction.tabIndex ={’mos -tt_1p8v_25 ’ : [(’0 p0001_0p0001 ’, 10),(’0p0001_0p01 ’, 11),(’0p0001_1 ’, 12),(’0p01_0p0001 ’, 13),(’0p01_0p01 ’, 14),(’0p01_1 ’, 15),(’1_0p0001 ’, 16),(’1_0p01 ’, 17),(’1_1’, 18)],’mos -tt_1p62v_25 ’ : [...]... : [...]...}
The submodule tab index.py is capable of outputting a dictionary that contains, for a specific process
corner, e.g. ’mos-tt_1p8v_25’, its tables’ ”coordinates” associated with the mt file number with the right
measures.
5.3.2 Mt file data dictionary - gen dic creator.py and seq dic creator.py
After the initial indexation, the .mt files inside the cells’ alter directories, as exemplified in code 5.4 will
be moved one step above the hierarchy, but their number will change to reflect the relative position they
45
were with respect to the alter folder they were, see Code 5.7.
Code 5.7: Simulation files after being moved higher in the tree directory hierarchy.
.|-- BASICLIB_and2| |-- alter1_25| |-- alter26_50| |-- alter51_75| |-- input.mt1| |-- input.mt2| |-- input.mt3| |-- ...| ‘-- input.mt75|-- BASICLIB_dffnr| |-- alter1_25| |-- alter26_50| |-- alter51_75| |-- alter_seq1_1_3| |-- alter_seq1_4_6| |-- alter_seq1_7_9| |-- alter_seq2_10_18| |-- alter_seq2_1_9| |-- alter_seq2_19_27| |-- input.mt1| |-- input.mt2| |-- input.mt3| |-- ...| |-- input.mt75| |-- ...| ‘-- ...|-- BASICLIB_cell3| |-- ...... ... ...
Submodules gen dic creator.py and seq dic creator.py not only do that but generate a third dictio-
nary for each cell that holds the data of each .mt file. See code 5.8.
Code 5.8: Cell’s mt files data dictionary.
{’input.mt1 ’:{’t1_rise_vout1_vin2_3_n ’: ’2.95e-06’,’charge_fall_vout1_vin3_3_n ’: ’5.91e-16’,’t1_rise_vout1_vin2_1 ’: ’3.00e-07’,’t2_rise_vout1_vin2_4_n ’: ’3.05e-06’,’e_leak_llhh ’: ’-1.29e-16’,’e_leak_llhl ’: ’-5.49e-16’,’i_rise_vout1_vin2_1 ’: ’7.07e-14’,’...’:’...’,...},’input.mt2 ’:{’...’: ’...’,...}’...’ : {...}}
46
5.3.3 Liberty file Writing- lib organizer.py, concat writer.py complete writer.py
The last part of lib designer.py uses another configuration file, code 5.9. This file contains library and
cell specific information, for example, general library power pins, time units for the final liberty file, cell
logic function, cell pin names, cell input pin relation with output, among others.
Code 5.9: Library and cell configuration file.[default]<time_unit > = 1ns<voltage_unit > = 1V<current_unit > = 1mA<pull_res_unit > = 1kohm<leak_pow_unit > = 1nW<en_unit > = 1pJ<cap_load_unit > = (1.000 ,pf)lef_path = /home/Users/username/LEF/BASICLIB.lef
<power_down_function > = !DVDD + AGND<vdd > = DVDD<vdd_name > = VDD<vss > = AGND<vss_name > = VSS
[nand2]<vin1 > = a<vin2 > = b<vout1 > = y<function > = (a*b)’<timing_sense > = negative_unate<timing_type > = combinational<related_pg_pin > = dvdd
[dffnr]...
Using the dictionary in code 5.8 and the one in code 5.6, one can finally construct the look-up tables in
the empty liberty shells. The submodule lib organizer.py do this in a multithreading environment, so that
each cell folder will contain liberty files for every major process corner, e.g. Lib File mos-tt 1p62 25c.lib,
Lib File mos-tt 1p62 N40c.lib, Lib File mos-ss 0p8 125c.lib.
The liberty files for the same corner of different cells are concatenated, module concat writer.py,
generating a quasi-final file. In the end, the script complete writer.py is capable of completing any
information lacking in the final liberty file.
47
48
Chapter 6
Evaluation and Validation
In a early iteration of the methodology, a 22nm digital cell library was characterized. This digital library
included 21 standard cells:
• 9 combinational cells - AND2, DELAY, DELAYD2, INV, INVD2, MUX2,NAND2,NOR2,OR2;
• 11 sequential cells - CLKG, DFFNR, DFFNRS, DFFNS, PDLATN, RSLAT, SDFFNR, SDFFNRS,
SDFFNS, SPDFFR, SPDFFNRS;
• 1 tri-state cell - INVTRI
This initial characterization was a stepping stone to evaluate the methodology and was used to
improve the methodology’s flow and the scripts’ execution. To demonstrate a small part of the process
of characterizing this library, section 6.1 explains the process of characterizing the library’s negative edge
D flip-flop, referring difficulties and evaluating the necessary hours to execute the job, while in section
6.2, the libraries’ liberty files and standard cells are used to design a digital circuit. A comparisson of the
circuits signal delay is then made using analog HSPICE simulations and SDF file, backannotaded, logic
level simulations.
6.1 Evaluation
To evaluate the methodology created, the characterization of the negative edge D flip-flop was done of
a 22nm digital library is here exemplified. This cell was chosen due to the various type of time analysis
it requires.
The flip-flop was designed in-house by the engineers of SiliconGate, so no previous characterization
existed.
The following subsection describes the steps taken to characterize the cell and the difficulties found
during the realization of this task.
49
6.1.1 Negative edge D flip-flop characterization
First, the design of the simulation testbench on a schematic software like Cadence Virtuoso Schematic
L should be done. As explained in the beginning of chapter 4, this minimizes human error instead of
manually writing it on the SPICE netlist. The most time consuming task is designing a stimuli that permits
measurements of all the necessary cell delay combinations, power consumption and pin capacitance.
This usually takes around 9 hours, as it is necessary to write the signal input on the testbench, to
simulate, and then to verify the measures correctness. This is the cost of having a more complete
characterization, nonetheless, with the system of testbench reusability developed, this is, at most, a one
time ocurrence. The signal viewer software and the simulation .lis file are the main tools in this phase. A
designer will need to be going back and forward between the two of them, to ensure the measures are
done with the right signal edges at the right time. It is also necessary to make sure the output signals
have time to fully change its voltage value between input pin transitions. This is where the p_width
parameter, of the configuration file exemplified in code 5.1, is important. As slow corners (high load
capacitance, slow transistors and high temperature), can lead to wrongful or failed measurements.
With the testbench designed, the next step is to break it apart to form the files that constitute the
generic testbench repository. This task can be executed alongside the creation of the empty liberty
shell, as it’s based on this file that the lib designer.py can write the liberty file. These tasks, together,
need around 15 minutes to be completed.
With the testbench repository updated, the gen netlist.py script can be run anytime changes on the
cell design are made. Ensuring the characterization uses the latest cell netlist.
Next, preparation to launch the main function, lib maker.py, can start. The first necessary task to be
executed, is to change the parameters on the configuration file, code 5.1, identify the paths to the digital
library folder, the generic repository and the empty liberty folder. After, executing the script creates
the simulation folder, prepares the simulation files, the tree structure of code 5.3 and launches the
simulations. Simulation time varies with the ammount of CPU processors dedicated to the script, and
with the number of corners.
Simulations for 25 corners, which corresponds to a liberty file with 5 values of input net transition and
5 values of output load capacitance, take around 30 minutes to complete. Even though a large number
of measures and optimizations are made, the script’s multicore execution reduces simulation time.
During script development, a problem appeared in the simulation management algorithm. HSPICE
simulations can include .lib files, called library files. HSPICE library files can make high-level statements
calls, contain netlists, model parameters, test vectors, types of analysis and option macros [17]. In
characterization jobs, these files are used mainly to include transistors model types, for instance see
code 6.1. For each corner simulation, the libraries to be included can be specified, therefore, during
characterization, as the simulations progressed, parameters and libraries include statements were as-
serted with each alter, as in code 6.2. For instance, for the case of parameters, .PARAM in code 6.2,
each time the value of a parameter is changed, as is the case of t_tran, or reasserted, as is the case
avddpar, in alter cases .ALTER 1 and .ALTER 2, the values of the parameters in the computer’s memory
will remain the same or be changed, however, no more memory space will be used. This is not the case
50
Code 6.1: Hspice Library inclusion code.*************** Header File ***************
.TEMP nom_temp
.OPTION+ ARTIST =2+ INGOLD =2+ PARHIER=LOCAL+ PSF=2+ POST.LIB "/home/users/username/tech/gen /22/ models/HSPICE/hspice.lib" mainlib.LIB "/home/users/username/tech/gen /22/ models/HSPICE/hspice.lib" dio_t.LIB "/home/users/username/tech/gen /22/ models/HSPICE/hspice.lib" bip_t.LIB "/home/users/username/tech/gen /22/ models/HSPICE/hspice.lib" res_typ.LIB "/home/users/username/tech/gen /22/ models/HSPICE/hspice.lib" cap_typ.LIB "/home/users/username/tech/gen /22/ models/HSPICE/hspice.lib" mos_tt
...
with libraries, HSPICE can not identify that a library included in a previous alter case is the same library
included in the current alter case, or that they are different, but specify the same model, and hence, that
the old one should be replaced. HSPICE will actually keep in memory each library included, and so, if
libraries are instantiated in each alter statement, more and more data will clog the computers’ memory,
making each simulation gradually slower, even though HSPICE uses only the latest included model in
its simulations. The problem can be resolved if libraries are included only when models are changed in
corners, minimizing the memory used, as is examplified in code 5.2.
However, to demostrate the issue, a set of 25 corners, in other words, 25 alter statements, were
simulated. In one case we use an alter file in which, each alter statement, contains the same library
instantiation, as demonstrated in 6.2, in another case, only the first alter statement contains a library
instantiation, as exemplified in code 5.2. Tables 6.1 and 6.2 display the simulation times, of the 25
corners, for two types of standard cells, a 2-input NAND and negative edge D flip-flop. Ten simulations
were done of each situation, to gather a large enough statistical sample of different cases. In the tables,
for the 1 library instantiation case, the first line of simulation time displays cases where parameter values
were not changed between alters, while the second line shows simulation time where the parameter
values are changed between alter cases, this proves that changing the parameters does not affect the
overall simulation time, or that their effect is minimal. Meanwhile, in the case of 25 library instantiations,
one for each alter case, the first line displays simulation time, where each alter includes the same library
and the parameters values are not changed, while the second line shows simulation time, where each
alter includes a different library and the parameter values are also changed. The two situations prove
that no matter the case, if the same library is included in each alter case, of if different libraries are
included in each alter case, the simulation time will increase drastically.
Code 6.2: Alter file example.ALTER 1.LIB "/home/User/username/tech/hspice.lib" mos_ff.LIB "/home/User/username/tech/hspice.lib" pre_lay_sim.TEMP 25.PARAM avddpar =0.88.PARAM t_tran =0.0001n
51
.PARAM outcap =0.001p*******************************************************.ALTER 2.LIB "/home/User/username/tech/hspice.lib" mos_ff.LIB "/home/User/username/tech/hspice.lib" pre_lay_sim.TEMP 25.PARAM avddpar =0.88.PARAM t_tran =0.0001n.PARAM outcap =0.005p*******************************************************.ALTER 3......*******************************************************.ALTER 25.LIB "/home/User/username/tech/hspice.lib" mos_ff.LIB "/home/User/username/tech/hspice.lib" pre_lay_sim.PARAM avddpar =0.88.PARAM nom_temp =25.PARAM t_tran =0.0001n.PARAM outcap =0.001p*******************************************************
Table 6.1: Negative edge D flip-flop simulation time, using different alter files.dffnr Simulation Time (s) Average (s)
1 Inst 93.049 93.318 93.056 93.213 93.338 93.350 ± 0.12993.279 93.250 93.665 93.866 93.468
25 Inst 244.168 244.842 249.947 248.267 249.457 244.168 ± 1.105245.026 250.374 249.359 251.154 249.766
Table 6.2: NAND2 simulation time, using different alter files.nand2 Simulation Time (s) Average (s)
1 Inst 46.274 46.419 45.950 46.081 45.862 46.192 ± 0.12546.071 46.232 46.294 46.089 46.652
25 Inst 166.649 166.649 166.588 166.795 166.976 167.044 ± 0.476166.626 167.133 168.721 165.709 168.598
With the simulations finished, the last script can run. lib designer.py will compile the data and write
the liberty file. As this script deals mainly with reading and writing data on disk, its execution time is
minimal compared with creating the testbench and simulating the corners. In appendix C the complete
liberty file of the negative edge D flip-flop is exemplified.
In the end around 10 hours are needed to characterize the flip-flop. However 90 % of this time was
used to design the testbench, its now visible why testbench reusability is so important. Is also important
to notice that 25 corners is a small number of corners. On typical characterization jobs, thousands of
corners are needed to fully characterize a standard cell, requiring hours or days of simulation to generate
the necessary data to write the liberty files for an entire digital cell library.
6.2 Validation
To validate the timing characterization done, a comparison between a circuit’s analog HSPICE simulation
and the verilog model, with a SDF file backannotaded, can be used.
52
A B Y0 0 00 1 11 0 11 1 0
Table 6.3: XOR truth table.
The foundry provides very accurate transistor level models for the HSPICE simulation. Therefore,
HSPICE simulations are closely matched to reality, except the delays, caused by the circuits intercon-
nections, not being modeled in a schematic based netlist. The backannotaded verilog model on the
other hand, includes the SDF file generated after a digital circuit’s P&R , as explained in section 2.3, this
file indicates not only the circuits cell delay, provided by the liberty files, but also the cell’s interconnec-
tions delays. If we edit the file to not include the latter, a comparison can be made between the circuit’s
delay with HSPICE and the verilog model.
The first step, therefore, is to choose a circuit to be designed with the flow of section 2.3. The logic
function XOR is a simple logic function that can be designed using NANDs and NORs logic gates. Table
6.3 displays the truth table of a XOR. This function was selected as an example, because it is simple
enough to allow an easy analysis of the delays in the transitions of each logic node.
The XOR, being a very simple circuit could have been designed directly at logic level. However,
in order to follow the design flow presented in section 2.3, the RTL representation of the XOR was
designed. To synthesize the circuit, Synopsys Design Compiler is used. Design Compiler received
the verilog RTL model of the XOR, as in code 6.3, and the liberty files of a 22nm digital cell library to
generate a gate-level netlist, which is a completely structural description of the circuit using standard
cells only.
Code 6.3: XOR logic RTL description.module XOR_RTL(y ,
a ,b);
// PORTS ------------output y ;input a ;input b ;
// LOGIC ------------assign y = ( a & ~b) | ( ~a & b);
endmodule
The resulting circuit is displayed in figure 6.1. The circuit can be reextracted into a verilog model that
contains instantiations of the standard cells, code 6.4 displays the extracted model.
Code 6.4: XOR logic synthesized description.module XOR_SYNT ( a, b, y, vdd , vss );
output y ;input a ;input b ;input vdd ;
53
Figure 6.1: XOR synthesized circuit.
input vss ;
wire n5 ;wire n6 ;wire n7 ;wire n8 ;
BASICLIB_nand2 U6 ( .vdd(vdd), .vss(vss), .a(n5), .b(n6), .yz(y) );BASICLIB_nand2 U7 ( .vdd(vdd), .vss(vss), .a(b) , .b(n7), .yz(n6) );BASICLIB_inv U8 ( .vdd(vdd), .vss(vss), .y(n8), .yz(n5) );BASICLIB_nor2 U9 ( .vdd(vdd), .vss(vss), .a(n7), .b(b), .yz(n8) );BASICLIB_inv U10( .vdd(vdd), .vss(vss), .y(a) , .yz(n7) );
endmodule
The Synthesis tool used three different types of standard cells to generate the design, inverters,
NANDs and NORs. This will allow to evaluate the accuracy of the characterization done using the liberty
files of these cells.
At this step a testbench was created for the designed XOR. To simulate the XOR circuit integration
in a larger design, other XOR cells were connected to its inputs and output, this resembles the typical
driving strengths and output load capacitance the cell would receive if included in a larger circuit. In
figure 6.2 the evaluated cell is U3.
After extracting the verilog model from the testbench circuit, the next step is to run Cadence SoC
Encounter to make the P&R. To run the software, besides the synthesized verilog file and the digital
library liberty files, its also necessary two LEF files, the technology LEF file and the digital library LEF
file. The technology LEF files contains specific properties of the technology, i.e. number of metal layers
and design rules, metal capacitances and via definitions. These files are specific to each technology so
they are provided by the foundry. The digital library LEF file contains the relevant description of each
standard cell layout, including its boundary, the pins layout and blockages.
With these files, P&R of the testbench is made, as shown in figure 6.3. With the layout, RC extraction
and SDF file generation was performed.
54
Figure 6.2: XOR testbench circuit.
Figure 6.3: XOR layout after P&R in Cadence Soc Encounter.
A verilog and HSPICE testbench is created, figure 6.4 exemplifies the stimuli visualized on the pins
of XOR U3.
Figure 6.4: HSPICE and verilog stimuli.
Four corners are used to compare the analog HSPICE simulations and the backannotaded verilog
simulations. These corners correspond to combinations of two types of transitors models, typical-typical
and fast-fast and two supply voltages, 1.62 V and 1.8 V. The SDF files generated contain cell delays at
125 ◦C, so the HSPICE simulations were also run at this temperature. Tables 6.4 and 6.5 displays the
delay between input and output pin transitions of XOR U3, for the stimuli exemplified in figure 6.4, while
table 6.6 presents the relative error.
55
Generally, the backannotaded verilog model presents lower cell delays when compared with the
HSPICE simulation, with relative errors around 3.7 %. The inferior cell delay in verilog simulations, can
be a consequence of characterizing the standard cells with the black box testbench illustrated in figure
4.2. In real circuits, the drive strength on a cell pin is limited by the current the cells connected to the
pin are capable of providing, as this current needs to charge the gate and the parasitics capacitante
of the input pin. In the testbench, there is no limit to the current the Piece-Wise Linear voltage source
can provide the cell, therefore the input will rise on any specified time leading to shorter cell delay and
consequently affecting also the pin capacitance and dynamic power measures, as these are measured
when the cells’ input signals change their values. With these results, it’s possible to infer that in situations
where supply voltage is even lower, the relative error will grow, as the supply voltage directly affects the
cell output current, and therefore its drive strength capabilities.
Table 6.4: XOR input to output delay in HSPICE simulation
HSPICEDelay (ps)
cornermos-tt mos-ff
a b y 1.62 V 1.8 V 1.62 V 1.8 Vrise low rise 173 152 156 139fall low fall 182 163 167 150low rise rise 77.7 67.5 69.8 61.6low fall fall 79.2 68.9 70.8 62.6
Table 6.5: XOR input to output delay in Verilog simulation
VerilogDelay (ps)
cornermos-tt mos-ff
a b y 1.62 V 1.8 V 1.62 V 1.8 Vrise low rise 186 166 169 153fall low fall 185 168 171 155low rise rise 75.0 66.4 68.1 60.5low fall fall 79.7 69.4 71.7 64.0
Table 6.6: Relative error between the HSPICE and Verilog measures
ComparisonRelative Error (%)
cornermos-tt mos-ff
a b y 1.62 V 1.8 V 1.62 V 1.8 Vrise low rise 7.5 8.9 8.4 10.3fall low fall 1.8 3.2 2.4 3.1low rise rise 3.5 1.6 2.4 1.8low fall fall 0.6 0.7 1.3 2.2
56
Chapter 7
Conclusions
The aim of this thesis was to develop a methodology and respective software capable of facilitating the
task of characterizing standard cell libraries.
The developed method streamlined the process of library characterization as much as possible,
reducing the ammount of manual tasks and maximizing computer run phases. However, problems were
encountered during the evaluation and validation processes.
The manual creation of testbenches proved to be a laborious task to accomplish, the time and effort
needed to create a testbench for a cell’s timing arcs, power consumption and pin capacitance varies
with the cell’s logic function. Nonetheless, it takes precious time everytime a new digital cell library,
with new standard cells, needs to be characterized. Sequential cells proved to be especially difficult, as
optimization testbenches need to be designed to characterize the cells time constraints. The reusability
of the testbenches partially solves this problem, but is not a complete solution.
The HSPICE simulation launch and management script completely fulfills the objective of automati-
cally launching and managing HSPICE simulations in a multicore environment. However, it lacked tools
to detect if the simulations failed or if the data obtained was not valid. This limitation, partially hinders
the methodology’s flow, as it’s necessary to manually correct these errors.
The liberty file writing script successfully automizes every step needed to write a liberty file, being an
extremely realiable tool.
These scripts are based on a modular structure and this proved to facilitate error detection and
correction.
The methodology was successfully validated, showing an average error of 3.7% in timing analysis,
when comparing the HSPICE transistor level simulation with the logic level simulation.
A complete digital cell library designed by SiliconGate was characterized. As a consequence of being
fully characterized by the corresponding liberty file, this digital cell library was the first to be licensed for
use by one of SiliconGate’s clients. This result is an evidence that the present work fully achieved its
purposes, defining a new period in SiliconGate’s digital cell characterization capability.
57
7.1 Future Work
The general workflow suffers from limitations in the accuracy of the generated liberty files, therefore, one
of the first things to improve is the black box test model used to characterize the liberty cells.
A modification that can improve the method’s flow is the automation of testbench creation. The
ideal software has to be capable of inserting specified input signals, detecting the evaluated cell logic,
creating a custom full-fledged test table and ensure the stimuli covers all the necessary cases needed
to measure. This process becomes increasingly complex as one progress from combinational logic, to
sequential and tri-state logic. Nonetheless, full automation can only be obtained going down this path.
So future work on this area will seek to gradually automize testbench design.
The NLDM used is also not the best existing delay model to characterize standard cells. The Com-
posite Current Source (CCS) model can be the next step in improving the accuracy of the simulations,
as these models take into account physical effects, e.g. the effect of Miller capacitance on input pin ca-
pacitance and net delay, in technology sizes inferior to 90 nm. The implementation of this model would
require changes on the way the liberty files are written.
The automatic identification of failed simulations during characterization and the re-execution of these
simulations with different parameters is a feature that needs to be implemented. It’s a feature necessary
to facilitate a digital designer’s job and that can improve vastly the obtained results.
The liberty file creation script, became rather complex with the great number of measures it needed.
So simplification of this tool’s workflow is necessary.
Scripts that do a relative validation of the generated liberty files can also be designed. These scripts
would go through the look-up tables, comparing the timing data to ensure it increases with capacitance
and input net transition. This of course, does not verify if the results are exact, nonetheless it would
indicate anomalous deviations through tables, indicating wrongful indexing by the software, mishaps on
the alter file creation or unexpected cell behaviour.
Furthermore, the ability to display characterization data in other formats besides the Synopsys Lib-
erty would be an important addition.
58
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and State University, August 2000.
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content/kbase/cell_char_intro_090508.pdf. Retrieved May 15, 2017.
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Appendix A
Hspice Simulation Files
A.1 Hspice Header
*************** Header File ***************
.PARAM avddpar =0.8
.PARAM nom_temp = 25
.PARAM outcap =0.001p
.PARAM t_hold =200n
.PARAM t_margin = t_hold *0.2
.PARAM t_tran =0.0001n
.PARAM time_step = t_tran /10
.PARAM t1=0 t2=t1+t_hold t3=t2+t_tran t4=t3+t_hold t5=t4+t_tran t6=t5+t_hold
+ t7=t6+t_tran t8=t7+t_hold t9=t8+t_tran t10=t9+t_hold t11=t10+t_tran
+ t12=t11+t_hold
.PARAM start = t_hold /2
.PARAM delayv2 = t8
.PARAM non_trans = start+t12+t_hold
.PARAM end_sim = non_trans *2
.TRAN time_step end_sim START=0 UIC
.PARAM leak_llh_1 = t1+t_margin
.PARAM leak_llh_2 = t2 -t_margin
.PARAM leak_lhh_1 = t3+t_margin
.PARAM leak_lhh_2 = t4 -t_margin
.PARAM leak_hhl_1 = t5+t_margin
.PARAM leak_hhl_2 = t6 -t_margin
.PARAM leak_hlh_1 = t9+t_margin
.PARAM leak_hlh_2 = t10 -t_margin
.OP
.OPTION
+MEASDGT =6 LENNAME =16
+RUNLVL =6
+method=gear maxord =2
+delmax =20n
*+probe
+post
+ingold =1
+nomod
*************** Header File ***************
A.2 Hspice Input
** View name: tr_func
c0 vout1 agnd outcap
v2 vi agnd DC=avddpar
v3 agnd 0 DC=0
xi0 vin1 vin2 vi agnd vout1 <CELL_NAME > * cell to test
* vin1 = a
v990 vin1 net990 PWL t1 0 t2 0 t3 avddpar t4 avddpar t5 0 t6 0 t7 avddpar t8 avddpar t10 avddpar t11
avddpar t12 avddpar t13 0 td = t_hold
61
v9901 net990 agnd PWL t1 0 t2 0 t3 avddpar t4 avddpar t5 0 t6 0 td = non_trans
* vin2 = b
v991 vin2 net991 PWL t1 0 100e-12 avddpar t6 avddpar t7 0 t8 0 t9 avddpar t10 avddpar t11 0 t12 0 td =
t_hold
v9911 net991 agnd PWL t1 0 t8 0 t9 avddpar t10 avddpar t11 0 t12 0 td = non_trans
A.3 Hspice Footer
*************** Footer File ***************
* Timing arcs
* Only case vin1
*Fall delay vout1_vin1_vin2
.measure tran cell_fall_vout1_vin1_vin2 trig v(vin1) val = ’0.5*avddpar ’
+ td = start rise=1 targ v(vout1) val = ’0.5*avddpar ’ fall = 1 td=start
* Fall time vout1_vin1_vin2
.measure tran fall_transition_vout1_vin1_vin2 trig v(vout1) val = ’0.8*avddpar ’
+ td = start fall = 1 targ v(vout1) val = ’0.2*avddpar ’ fall = 1 td=trig
* Rise delay vout1_vin1_vin2
.measure tran cell_rise_vout1_vin1_vin2 trig v(vin1) val = ’0.5*avddpar ’
+ td = start fall=1 targ v(vout1) val = ’0.5*avddpar ’ rise = 1 td=trig
* Rise time vout1_vin1_vin2
.measure tran rise_transition_vout1_vin1_vin2 trig v(vout1) val = ’0.2*avddpar ’
+ td = start rise =1 targ v(vout1) val = ’0.8*avddpar ’ rise = 1 td=trig
*-------------------------------------------------------------------------------
* Only case vin2
*Fall delay vout1_vin2_vin1
.measure tran cell_fall_vout1_vin2_vin1 trig v(vin2) val = ’0.5*avddpar ’
+ td = delayv2+start rise=1 targ v(vout1) val = ’0.5*avddpar ’ fall = 1 td=delayv2+start
* Fall time vout1_vin2_vin1
.measure tran fall_transition_vout1_vin2_vin1 trig v(vout1) val = ’0.8*avddpar ’
+ td = delayv2+start fall=1 targ v(vout1) val = ’0.2*avddpar ’ fall = 1 td=trig
* Rise delay vout1_vin2_vin1
.measure tran cell_rise_vout1_vin2_vin1 trig v(vin2) val = ’0.5*avddpar ’
+ td = delayv2+start fall=1 targ v(vout1) val = ’0.5*avddpar ’ rise = 1 td=trig
* Rise time vout1_vin2_vin1
.measure tran rise_transition_vout1_vin2_vin1 trig v(vout1) val = ’0.2*avddpar ’
+ td = delayv2+start rise = 1 targ v(vout1) val = ’0.8*avddpar ’ rise = 1
*-------------------------------------------------------------------------------
* Rise time do vi
.measure tran rise_transition_vi trig v(vin1) val = ’0.2*avddpar ’ rise =1
+ targ v(vin1) val = ’0.8*avddpar ’ rise = 1
* Fall time vi
.measure tran fall_transition_vi trig v(vin1) val = ’0.8*avddpar ’ fall =1
+ targ v(vin1) val = ’0.2*avddpar ’ fall = 1
*-------------------------------------------------------------------------------
* Leakage power in each state
.measure average_i_llh INTEG i(v2)
+ from=’t1+t_margin ’ to=’t2’
.measure e_leak_llh param=’avddpar*average_i_llh ’
.measure power_leak_llh param=’e_leak_llh /(t2-t1-t_margin)’
.measure average_i_lhh INTEG i(v2)
+ from=’t3+t_margin ’ to=’t4’
.measure e_leak_lhh param=’avddpar*average_i_lhh ’
.measure power_leak_lhh param=’e_leak_lhh /(t4-t3-t_margin)’
.measure average_i_hlh INTEG i(v2)
+ from=’t9+t_margin ’ to=’t10 ’
.measure e_leak_hlh param=’avddpar*average_i_hlh ’
.measure power_leak_hlh param=’e_leak_hlh /(t10 -t9-t_margin)’
.measure average_i_hhl INTEG i(v2)
+ from=’t5+t_margin ’ to=’t6’
62
.measure e_leak_hhl param=’avddpar*average_i_hhl ’
.measure power_leak_hhl param=’e_leak_hhl /(t6-t5-t_margin)’
* Average static (leakage) power
.measure power_leak_static
+ param=’( power_leak_llh + power_leak_lhh + power_leak_hhl + power_leak_hlh)/4’
*-------------------------------------------------------------------------------
* Internal power for output pin transitions
* Only case vin1
* Fall power vout1_vin1_vin2
.measure t1_fall_vout1_vin1_1 when v(vin1) = ’0.1*avddpar ’ rise = 1
+ td = start
.measure t2_fall_vout1_vin1_1 when v(vout1) = ’0.1*avddpar ’ fall = 1
+ td = start
.measure tran charge_fall_vout1_vin1_1 INTEG i(v2)
+ from = ’t1_fall_vout1_vin1_1 ’ to = ’t2_fall_vout1_vin1_1 ’
.measure ipower_fall_vout1_vin1_vin2 param = ’charge_fall_vout1_vin1_1*avddpar ’
* Rise power vout1_vin1
.measure t1_rise_vout1_vin1_1 when v(vin1) = ’0.9*avddpar ’ fall = 1
+ td = ’start +2*t_hold ’
.measure t2_rise_vout1_vin1_1 when v(vout1) = ’0.9*avddpar ’ rise = 1
+ td = ’start +2*t_hold ’
.measure tran charge_rise_vout1_vin1_1 INTEG i(v2)
+ from = ’t1_rise_vout1_vin1_1 ’ to = ’t2_rise_vout1_vin1_1 ’
.measure ipower_rise_vout1_vin1_vin2 param = ’charge_rise_vout1_vin1_1*avddpar ’
*-------------------------------------------------------------------------------
* Only case vin2
* Fall power vout1_vin2_vin1
.measure t1_fall_vout1_vin2_1 when v(vin2) = ’0.1*avddpar ’ rise = 1
+ td = start+delayv2
.measure t2_fall_vout1_vin2_1 when v(vout1) = ’0.1*avddpar ’ fall = 1
+ td = start+delayv2
.measure tran charge_fall_vout1_vin2_1 INTEG i(v2)
+ from = ’t1_fall_vout1_vin2_1 ’ to = ’t2_fall_vout1_vin2_1 ’
.measure ipower_fall_vout1_vin2_vin1 param = ’charge_fall_vout1_vin2_1*avddpar ’
* Rise power vout1_vin2_vin1
.measure t1_rise_vout1_vin2_1 when v(vin2) = ’0.9*avddpar ’ fall = 1
+ td = ’start+delayv2+t_hold ’
.measure t2_rise_vout1_vin2_1 when v(vout1) = ’0.9*avddpar ’ rise = 1
+ td = ’start+delayv2+t_hold ’
.measure tran charge_rise_vout1_vin2_1 INTEG i(v2)
+ from = ’t1_rise_vout1_vin2_1 ’ to = ’t2_rise_vout1_vin2_1 ’
.measure ipower_rise_vout1_vin2_vin1 param = ’charge_rise_vout1_vin2_1*avddpar ’
*-------------------------------------------------------------------------------
* Internal power for non transitions
* Only case vin1
* Rise power vin1_!vin2_vout1
.measure t1_rise_vout1_vin1_1_n when v(vin1) = ’0.1*avddpar ’ rise = 1
+ td = non_trans
.measure t2_rise_vout1_vin1_1_n when v(vin1) = ’0.9*avddpar ’ rise = 1
+ td = non_trans
.measure tran charge_rise_vout1_vin1_1_n INTEG i(v2)
+ from = ’t1_rise_vout1_vin1_1_n ’ to = ’t2_rise_vout1_vin1_1_n ’
.measure ipower_rise_vin1_!vin2_vout1_1_n param = ’charge_rise_vout1_vin1_1_n*avddpar ’
* Fall power vout1_vin1_vout1
.measure t1_fall_vout1_vin1_1_n when v(vin1) = ’0.9*avddpar ’ fall = 1
+ td = non_trans
.measure t2_fall_vout1_vin1_1_n when v(vin1) = ’0.1*avddpar ’ fall = 1
+ td = non_trans
.measure tran charge_fall_vout1_vin1_1_n INTEG i(v2)
+ from = ’t1_fall_vout1_vin1_1_n ’ to = ’t2_fall_vout1_vin1_1_n ’
.measure ipower_fall_vin1_!vin2_vout1_1_n param = ’charge_fall_vout1_vin1_1_n*avddpar ’
*-------------------------------------------------------------------------------
* Only case vin2
63
* Rise power vin2_!vin1_vout1
.measure t1_rise_vout1_vin2_1_n when v(vin2) = ’0.1*avddpar ’ rise = 1
+ td = non_trans+delayv2
.measure t2_rise_vout1_vin2_1_n when v(vin2) = ’0.9*avddpar ’ rise = 1
+ td = non_trans+delayv2
.measure tran charge_rise_vout1_vin2_1_n INTEG i(v2)
+ from = ’t1_rise_vout1_vin2_1_n ’ to = ’t2_rise_vout1_vin2_1_n ’
.measure ipower_rise_vin2_!vin1_vout1_1_n param = ’charge_rise_vout1_vin2_1_n*avddpar ’
* Fall power vin2_!vin1_vout1
.measure t1_fall_vout1_vin2_1_n when v(vin2) = ’0.9*avddpar ’ fall = 1
+ td = non_trans+delayv2
.measure t2_fall_vout1_vin2_1_n when v(vin2) = ’0.1*avddpar ’ fall = 1
+ td = non_trans+delayv2
.measure tran charge_fall_vout1_vin2_1_n INTEG i(v2)
+ from = ’t1_fall_vout1_vin2_1_n ’ to = ’t2_fall_vout1_vin2_1_n ’
.measure ipower_fall_vin2_!vin1_vout1_1_n param = ’charge_fall_vout1_vin2_1_n*avddpar ’
*-------------------------------------------------------------------------------
* Input capacitance
* Pin a rise capacitance
.measure rise_cap_vin1_1 param = ’abs(charge_rise_vout1_vin1_1_n/avddpar)’
* Pin a fall capacitance
.measure fall_cap_vin1_1 param = ’abs(charge_fall_vout1_vin1_1_n/avddpar)’
* Pin b rise capacitance
.measure rise_cap_vin2_1 param = ’abs(charge_rise_vout1_vin2_1_n/avddpar)’
* Pin b fall capacitance
.measure fall_cap_vin2_1 param = ’abs(charge_fall_vout1_vin2_1_n/avddpar)’
* Pin a capacitance
.measure cap_vin1 param=’max(rise_cap_vin1_1 ,fall_cap_vin1_1)’
.measure cap_vin2 param=’max(rise_cap_vin2_1 ,fall_cap_vin2_1)’
*-------------------------------------------------------------------------------
64
Appendix B
Liberty Shell
library (<lib_name >) {
technology (cmos);
delay_model : table_lookup;
bus_naming_style : "%s[%d]";
slew_lower_threshold_pct_fall : 30.0;
slew_upper_threshold_pct_fall : 70.0;
slew_lower_threshold_pct_rise : 30.0;
slew_upper_threshold_pct_rise : 70.0;
input_threshold_pct_fall : 50.0;
input_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
slew_derate_from_library : 0.5;
time_unit : "<time_unit >";
voltage_unit : "<voltage_unit >";
current_unit : "<current_unit >";
pulling_resistance_unit : "<pull_res_unit >";
leakage_power_unit : "<leak_pow_unit >";
capacitive_load_unit <cap_load_unit >;
default_fanout_load : 1.000000;
default_inout_pin_cap : 0.100000;
default_input_pin_cap : 0.100000;
default_output_pin_cap : 0.000000;
default_max_fanout : 10;
default_max_transition : 5.0;
nom_process : 1.0 ;
nom_temperature : <nom_temp > ;
nom_voltage : <nom_voltage > ;
operating_conditions (conditions) {
process : 1.0 ;
temperature : <nom_temp > ;
voltage : <nom_voltage > ;
}
default_operating_conditions : conditions ;
cell( <cell_name > ) {
area : <area >;
pg_pin (<vdd >) {
pg_type : primary_power;
voltage_name : <vdd_name >;
}
pg_pin (<vss >) {
pg_type : primary_ground;
voltage_name : <vss_name >;
}
*< Leakage Power >*
leakage_power () {
value : <power_leak_static >;
65
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_llll >;
when : "!<vin1 > !<vin2 > !<vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_hlll >;
when : "<vin1 > !<vin2 > !<vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_lhll >;
when : "!<vin1 > <vin2 > !<vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_hhll >;
when : "<vin1 > <vin2 > !<vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_llhh >;
when : "!<vin1 > !<vin2 > <vin3 > <vout1 > !<vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_llhl >;
when : "!<vin1 > !<vin2 > <vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_hlhh >;
when : "<vin1 > !<vin2 > <vin3 > <vout1 > !<vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_hlhl >;
when : "<vin1 > !<vin2 > <vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_lhhh >;
when : "!<vin1 > <vin2 > <vin3 > <vout1 > !<vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_lhhl >;
when : "!<vin1 > <vin2 > <vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_hhhl >;
when : "<vin1 > <vin2 > <vin3 > !<vout1 > <vout2 >";
related_pg_pin : <vdd >;
}
leakage_power () {
value : <power_leak_hhhh >;
when : "<vin1 > <vin2 > <vin3 > <vout1 > !<vout2 >";
related_pg_pin : <vdd >;
}
*< Leakage Power >*
*< ff group >*
pin (<vin3 >) {
direction : input;
related_ground_pin : <vss >;
related_power_pin : <vdd >;
capacitance : <cap_vin3 >;
rise_capacitance : <rise_cap_vin3 >;
fall_capacitance : <fall_cap_vin3 >;
*< Timing Violations >*
*< Non Transition Power >*
}
pin (<vin2 >) {
direction : input;
related_ground_pin : <vss >;
related_power_pin : <vdd >;
capacitance : <cap_vin2 >;
rise_capacitance : <rise_cap_vin2 >;
66
fall_capacitance : <fall_cap_vin2 >;
*< Timing Violations >*
*< Non Transition Power >*
}
pin (<vin1 >) {
direction : input;
related_ground_pin : <vss >;
related_power_pin : <vdd >;
capacitance : <cap_vin1 >;
rise_capacitance : <rise_cap_vin1 >;
fall_capacitance : <fall_cap_vin1 >;
*< Timing Violations >*
*< Non Transition Power >*
}
pin (<vout1 >) {
direction : output;
power_down_function : <power_down_function >;
function : "<function_vout1 >";
related_ground_pin : <vss >;
related_power_pin : <vdd >;
max_capacitance : <max_capacitance >;
*< Timing Arcs >*
*< Transition Power >*
}
pin (<vout2 >) {
direction : output;
power_down_function : <power_down_function >;
function : "<function_vout2 >";
related_ground_pin : <vss >;
related_power_pin : <vdd >;
max_capacitance : <max_capacitance >;
*< Timing Arcs >*
*< Transition Power >*
}
}
}
67
68
Appendix C
Complete Negative Edge D Flip-Flop
Liberty File
library (BASICLIB_mos -ff0p88v25c) {
technology (cmos);
delay_model : table_lookup;
bus_naming_style : "%s[%d]";
slew_lower_threshold_pct_fall : 30.0;
slew_upper_threshold_pct_fall : 70.0;
slew_lower_threshold_pct_rise : 30.0;
slew_upper_threshold_pct_rise : 70.0;
input_threshold_pct_fall : 50.0;
input_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
slew_derate_from_library : 0.5;
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1mA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit (1.000 ,pf);
default_fanout_load : 1.000000;
default_inout_pin_cap : 0.100000;
default_input_pin_cap : 0.100000;
default_output_pin_cap : 0.000000;
default_max_fanout : 10;
default_max_transition : 5.0;
nom_process : 1.0 ;
nom_temperature : 25 ;
nom_voltage : 0.88 ;
voltage_map ("VDD " ,0.88);
voltage_map ("VSS",0);
operating_conditions (mos -ff0p88v25c) {
process : 1.0 ;
temperature : 25 ;
voltage : 0.88 ;
}
default_operating_conditions : mos -ff0p88v25c ;
power_lut_template (power_template_5x5) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("0.0001 ,0.001 ,0.01 ,0.1 ,1.0");
index_2 ("0.001 ,0.005 ,0.01 ,0.1 ,0.2");
}
power_lut_template (passive_power_template_5x1) {
variable_1 : input_transition_time;
index_1 ("0.0001 ,0.001 ,0.01 ,0.1 ,1.0");
}
69
lu_table_template (delay_template_5x5) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.0001 ,0.001 ,0.01 ,0.1 ,1.0");
index_2 ("0.001 ,0.005 ,0.01 ,0.1 ,0.2");
}
lu_table_template (constraint_template_3x3) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("0.0001 ,0.01 ,1.0");
index_2 ("0.0001 ,0.01 ,1.0");
}
lu_table_template (mpw_constraint_template_3x1) {
variable_1 : related_pin_transition;
index_1 ("0.0001 ,0.01 ,1.0");
}
cell( BASICLIB_dffnrhv ) {
area : 185.76;
pg_pin (DVDD) {
pg_type : primary_power;
voltage_name : VDD;
}
pg_pin (AGND) {
pg_type : primary_ground;
voltage_name : VSS;
}
leakage_power () {
value : 1.20156e+02;
related_pg_pin : DVDD;
}
leakage_power () {
value : 5.11920e+00;
when : "!D !CLKZ !RSTZ !Q QZ";
related_pg_pin : DVDD;
}
leakage_power () {
value : 5.07268e+00;
when : "D !CLKZ !RSTZ !Q QZ";
related_pg_pin : DVDD;
}
...
leakage_power () {
value : 7.07799e+00;
when : "D CLKZ RSTZ Q !QZ";
related_pg_pin : DVDD;
}
ff (Q,QZ) {
clear : "(! RSTZ)";
clocked_on : "(! CLKZ)";
next_state : "D";
}
pin (Q) {
direction : output;
power_down_function : !DVDD + AGND;
function : "IQ";
related_ground_pin : AGND;
related_power_pin : DVDD;
max_capacitance : 0.2;
timing () {
related_pin : "CLKZ";
timing_sense : non_unate;
timing_type : falling_edge;
cell_fall (delay_template_5x5) {
values( " 9.96742e-01, 1.02424e+00, 1.05653e+00, 1.58831e+00, 2.16578e+00",\
" 9.96567e-01, 1.02394e+00, 1.05647e+00, 1.58808e+00, 2.16604e+00",\
" 9.99196e-01, 1.02739e+00, 1.05870e+00, 1.58857e+00, 2.16837e+00",\
" 1.03241e+00, 1.05982e+00, 1.09205e+00, 1.62179e+00, 2.19744e+00",\
" 1.37469e+00, 1.40195e+00, 1.43445e+00, 1.96515e+00, 2.54195e+00");
}
fall_transition (delay_template_5x5) {
values( " 3.39592e-02, 4.64322e-02, 6.19788e-02, 3.42012e-01, 6.52363e-01",\
" 3.37935e-02, 4.63998e-02, 6.20358e-02, 3.41537e-01, 6.52338e-01",\
" 3.38877e-02, 4.66603e-02, 6.26413e-02, 3.45793e-01, 6.57311e-01",\
" 3.43641e-02, 4.67571e-02, 6.20729e-02, 3.46277e-01, 6.69103e-01",\
" 3.39200e-02, 4.60364e-02, 6.13318e-02, 3.41586e-01, 6.55493e -01");
}
70
cell_rise (delay_template_5x5) {
values( " 8.15756e-01, 8.43362e-01, 8.75149e-01, 1.37635e+00, 1.91705e+00",\
" 8.15732e-01, 8.43108e-01, 8.74906e-01, 1.37649e+00, 1.91740e+00",\
" 8.19207e-01, 8.46840e-01, 8.78317e-01, 1.37907e+00, 1.92156e+00",\
" 8.51773e-01, 8.79293e-01, 9.10951e-01, 1.41285e+00, 1.95391e+00",\
" 1.19363e+00, 1.22100e+00, 1.25246e+00, 1.75422e+00, 2.29534e+00");
}
rise_transition (delay_template_5x5) {
values( " 4.49581e-02, 6.23783e-02, 8.41825e-02, 4.82051e-01, 9.23764e-01",\
" 4.49141e-02, 6.29748e-02, 8.48591e-02, 4.80882e-01, 9.24398e-01",\
" 4.49406e-02, 6.24372e-02, 8.50655e-02, 4.82555e-01, 9.27669e-01",\
" 4.50464e-02, 6.23861e-02, 8.43517e-02, 4.83073e-01, 9.26092e-01",\
" 4.48496e-02, 6.21321e-02, 8.40317e-02, 4.80886e-01, 9.24298e -01");
}
}
timing () {
related_pin : "RSTZ";
timing_sense : positive_unate;
timing_type : clear;
sdf_cond : "D == 1’b0 && CLKZ == 1’b0";
when : "!D&!CLKZ";
cell_fall (delay_template_5x5) {
values( " 5.48461e-01, 5.75698e-01, 6.08196e-01, 1.13900e+00, 1.71377e+00",\
" 5.48514e-01, 5.75761e-01, 6.08107e-01, 1.13905e+00, 1.71390e+00",\
" 5.52280e-01, 5.79634e-01, 6.11953e-01, 1.14282e+00, 1.71595e+00",\
" 5.84255e-01, 6.11562e-01, 6.43868e-01, 1.17544e+00, 1.74951e+00",\
" 9.25367e-01, 9.52899e-01, 9.85137e-01, 1.51592e+00, 2.09058e+00");
}
fall_transition (delay_template_5x5) {
values( " 3.42434e-02, 4.64409e-02, 6.22083e-02, 3.39222e-01, 6.49589e-01",\
" 3.40517e-02, 4.64204e-02, 6.18958e-02, 3.39347e-01, 6.49641e-01",\
" 3.42943e-02, 4.66202e-02, 6.22980e-02, 3.40910e-01, 6.54696e-01",\
" 3.43263e-02, 4.65386e-02, 6.24148e-02, 3.39800e-01, 6.57920e-01",\
" 3.37841e-02, 4.59517e-02, 6.13625e-02, 3.37273e-01, 6.50395e -01");
}
}
timing () {
related_pin : "RSTZ";
timing_sense : positive_unate;
timing_type : clear;
sdf_cond : "D == 1’b0 && CLKZ == 1’b1";
when : "!D&CLKZ";
cell_fall (delay_template_5x5) {
values( " 5.20077e-01, 5.47903e-01, 5.80723e-01, 1.11451e+00, 1.68952e+00",\
" 5.19972e-01, 5.47890e-01, 5.80838e-01, 1.11454e+00, 1.68939e+00",\
" 5.22684e-01, 5.50769e-01, 5.83221e-01, 1.11774e+00, 1.69075e+00",\
" 5.54891e-01, 5.82715e-01, 6.15274e-01, 1.14993e+00, 1.72540e+00",\
" 8.95765e-01, 9.24178e-01, 9.57054e-01, 1.49084e+00, 2.06571e+00");
}
fall_transition (delay_template_5x5) {
values( " 3.47919e-02, 4.72635e-02, 6.25438e-02, 3.39918e-01, 6.50032e-01",\
" 3.42660e-02, 4.65152e-02, 6.26801e-02, 3.37974e-01, 6.50646e-01",\
" 3.43187e-02, 4.70923e-02, 6.25028e-02, 3.40467e-01, 6.55087e-01",\
" 3.47008e-02, 4.70772e-02, 6.27003e-02, 3.40697e-01, 6.58577e-01",\
" 3.42826e-02, 4.64654e-02, 6.19296e-02, 3.37994e-01, 6.50508e -01");
}
}
timing () {
related_pin : "RSTZ";
timing_sense : positive_unate;
timing_type : clear;
sdf_cond : "D == 1’b1 && CLKZ == 1’b0";
when : "D&!CLKZ";
cell_fall (delay_template_5x5) {
values( " 5.48503e-01, 5.75900e-01, 6.08197e-01, 1.13897e+00, 1.71375e+00",\
" 5.48802e-01, 5.75805e-01, 6.08341e-01, 1.13898e+00, 1.71377e+00",\
" 5.52138e-01, 5.79775e-01, 6.10720e-01, 1.14154e+00, 1.71596e+00",\
" 5.84111e-01, 6.11823e-01, 6.43917e-01, 1.17531e+00, 1.75018e+00",\
" 9.24686e-01, 9.52135e-01, 9.85262e-01, 1.51597e+00, 2.09089e+00");
}
fall_transition (delay_template_5x5) {
values( " 3.42762e-02, 4.67372e-02, 6.22626e-02, 3.39194e-01, 6.49390e-01",\
" 3.38627e-02, 4.64326e-02, 6.20917e-02, 3.37943e-01, 6.48692e-01",\
" 3.37764e-02, 4.66875e-02, 6.19387e-02, 3.40590e-01, 6.54666e-01",\
" 3.42936e-02, 4.65664e-02, 6.24072e-02, 3.39930e-01, 6.58008e-01",\
" 3.37903e-02, 4.59421e-02, 6.13685e-02, 3.37599e-01, 6.50199e -01");
}
}
timing () {
related_pin : "RSTZ";
timing_sense : positive_unate;
timing_type : clear;
sdf_cond : "D == 1’b1 && CLKZ == 1’b1";
71
when : "D&CLKZ";
cell_fall (delay_template_5x5) {
values( " 5.56502e-01, 5.84418e-01, 6.17372e-01, 1.15105e+00, 1.72613e+00",\
" 5.56653e-01, 5.84619e-01, 6.17726e-01, 1.15138e+00, 1.72631e+00",\
" 5.59429e-01, 5.87613e-01, 6.20701e-01, 1.15528e+00, 1.72929e+00",\
" 5.92132e-01, 6.20134e-01, 6.53250e-01, 1.18773e+00, 1.76208e+00",\
" 9.33223e-01, 9.61490e-01, 9.93679e-01, 1.52748e+00, 2.10238e+00");
}
fall_transition (delay_template_5x5) {
values( " 3.46084e-02, 4.73527e-02, 6.28401e-02, 3.39934e-01, 6.50031e-01",\
" 3.44436e-02, 4.68671e-02, 6.22936e-02, 3.38827e-01, 6.50631e-01",\
" 3.43686e-02, 4.72094e-02, 6.27168e-02, 3.40570e-01, 6.54492e-01",\
" 3.49134e-02, 4.72603e-02, 6.24857e-02, 3.41905e-01, 6.56600e-01",\
" 3.43153e-02, 4.65571e-02, 6.19419e-02, 3.37945e-01, 6.50320e -01");
}
}
internal_power () {
related_pin : "RSTZ";
related_pg_pin : DVDD;
when : "D&&CLKZ";
fall_power (power_template_5x5) {
values( " 5.87441e-02, 6.32854e-02, 6.86162e-02, 1.43661e-01, 2.21104e-01",\
" 5.84463e-02, 6.29291e-02, 6.82812e-02, 1.43371e-01, 2.20863e-01",\
" 5.86279e-02, 6.31919e-02, 6.81713e-02, 1.43436e-01, 2.21053e-01",\
" 5.85653e-02, 6.30734e-02, 6.83896e-02, 1.43534e-01, 2.21197e-01",\
" 5.76672e-02, 6.21792e-02, 6.74968e-02, 1.42592e-01, 2.20142e -01");
}
}
internal_power () {
related_pin : "RSTZ";
related_pg_pin : DVDD;
when : "!D&&CLKZ";
fall_power (power_template_5x5) {
values( " 4.16237e-02, 4.60019e-02, 5.12553e-02, 1.26611e-01, 2.04040e-01",\
" 4.12059e-02, 4.55885e-02, 5.09123e-02, 1.26253e-01, 2.03734e-01",\
" 4.14094e-02, 4.58746e-02, 5.10980e-02, 1.26632e-01, 2.04186e-01",\
" 4.13173e-02, 4.57253e-02, 5.09587e-02, 1.26411e-01, 2.04027e-01",\
" 4.05749e-02, 4.49682e-02, 5.02359e-02, 1.25617e-01, 2.03154e -01");
}
}
internal_power () {
related_pin : "RSTZ";
related_pg_pin : DVDD;
when : "D&&! CLKZ";
fall_power (power_template_5x5) {
values( " 6.14190e-02, 6.65789e-02, 7.27233e-02, 1.52564e-01, 2.30031e-01",\
" 6.10931e-02, 6.62196e-02, 7.23999e-02, 1.52230e-01, 2.29748e-01",\
" 6.09519e-02, 6.61648e-02, 7.25750e-02, 1.52561e-01, 2.29823e-01",\
" 6.12227e-02, 6.63773e-02, 7.25243e-02, 1.52390e-01, 2.30018e-01",\
" 6.02841e-02, 6.54348e-02, 7.15984e-02, 1.51479e-01, 2.29046e -01");
}
}
internal_power () {
related_pin : "CLKZ";
related_pg_pin : DVDD;
rise_power (power_template_5x5) {
values( " 6.22179e-02, 6.59911e-02, 7.02273e-02, 1.35158e-01, 2.05289e-01",\
" 6.18622e-02, 6.56622e-02, 6.98940e-02, 1.34691e-01, 2.04914e-01",\
" 6.17091e-02, 6.55119e-02, 6.97633e-02, 1.34999e-01, 2.05178e-01",\
" 6.19457e-02, 6.57134e-02, 6.99429e-02, 1.34902e-01, 2.05429e-01",\
" 6.14515e-02, 6.52153e-02, 6.94016e-02, 1.34337e-01, 2.04580e -01");
}
fall_power (power_template_5x5) {
values( " 6.11903e-02, 6.48889e-02, 6.92019e-02, 1.40503e-01, 2.18049e-01",\
" 6.08406e-02, 6.45196e-02, 6.88489e-02, 1.40209e-01, 2.17714e-01",\
" 6.10857e-02, 6.43960e-02, 6.90274e-02, 1.40622e-01, 2.17822e-01",\
" 6.09684e-02, 6.46081e-02, 6.89219e-02, 1.40377e-01, 2.18212e-01",\
" 6.05660e-02, 6.42000e-02, 6.85144e-02, 1.39864e-01, 2.17522e -01");
}
}
internal_power () {
related_pin : "RSTZ";
related_pg_pin : DVDD;
when : "!D&&! CLKZ";
fall_power (power_template_5x5) {
values( " 6.14619e-02, 6.65695e-02, 7.27304e-02, 1.52657e-01, 2.30127e-01",\
" 6.10810e-02, 6.62511e-02, 7.23795e-02, 1.52343e-01, 2.29868e-01",\
" 6.10393e-02, 6.61763e-02, 7.23107e-02, 1.52349e-01, 2.29868e-01",\
" 6.12467e-02, 6.64038e-02, 7.25280e-02, 1.52490e-01, 2.30076e-01",\
" 6.03471e-02, 6.54906e-02, 7.16106e-02, 1.51590e-01, 2.29121e -01");
}
}
}
72
pin (QZ) {
direction : output;
power_down_function : !DVDD + AGND;
function : "IQ";
related_ground_pin : AGND;
related_power_pin : DVDD;
max_capacitance : 0.2;
timing () {
related_pin : "CLKZ";
timing_sense : non_unate;
timing_type : falling_edge;
cell_fall (delay_template_5x5) {
values( " 7.38739e-01, 7.49217e-01, 7.60676e-01, 9.08794e-01, 1.05274e+00",\
" 7.38690e-01, 7.49151e-01, 7.60647e-01, 9.08890e-01, 1.05290e+00",\
" 7.42207e-01, 7.52852e-01, 7.63958e-01, 9.11174e-01, 1.05661e+00",\
" 7.74744e-01, 7.85083e-01, 7.96576e-01, 9.44981e-01, 1.08906e+00",\
" 1.11674e+00, 1.12698e+00, 1.13833e+00, 1.28662e+00, 1.43068e+00");
}
fall_transition (delay_template_5x5) {
values( " 8.88454e-02, 9.92220e-02, 1.12147e-01, 3.31993e-01, 5.80523e-01",\
" 8.87506e-02, 9.91609e-02, 1.12285e-01, 3.30979e-01, 5.80886e-01",\
" 8.87653e-02, 9.92704e-02, 1.12215e-01, 3.31741e-01, 5.81354e-01",\
" 8.89917e-02, 9.94192e-02, 1.12142e-01, 3.32153e-01, 5.82049e-01",\
" 8.86375e-02, 9.90488e-02, 1.11901e-01, 3.31340e-01, 5.80043e -01");
}
cell_rise (delay_template_5x5) {
values( " 9.35359e-01, 9.48737e-01, 9.63989e-01, 1.19370e+00, 1.43785e+00",\
" 9.35019e-01, 9.48550e-01, 9.63834e-01, 1.19396e+00, 1.43770e+00",\
" 9.37455e-01, 9.51738e-01, 9.66364e-01, 1.19632e+00, 1.44123e+00",\
" 9.70873e-01, 9.84340e-01, 9.99508e-01, 1.22885e+00, 1.47444e+00",\
" 1.31299e+00, 1.32628e+00, 1.34166e+00, 1.57132e+00, 1.81640e+00");
}
rise_transition (delay_template_5x5) {
values( " 1.39797e-01, 1.44991e-01, 1.59960e-01, 5.29510e-01, 9.54151e-01",\
" 1.39760e-01, 1.45187e-01, 1.59534e-01, 5.30247e-01, 9.54093e-01",\
" 1.39804e-01, 1.44862e-01, 1.59716e-01, 5.30814e-01, 9.56080e-01",\
" 1.39626e-01, 1.44996e-01, 1.60005e-01, 5.30956e-01, 9.58668e-01",\
" 1.39704e-01, 1.44998e-01, 1.59238e-01, 5.29608e-01, 9.54993e -01");
}
}
timing () {
related_pin : "RSTZ";
timing_sense : negative_unate;
timing_type : preset;
sdf_cond : "D == 1’b0 && CLKZ == 1’b0";
when : "!D&!CLKZ";
cell_rise (delay_template_5x5) {
values( " 4.87190e-01, 5.00424e-01, 5.15517e-01, 7.46908e-01, 9.89058e-01",\
" 4.87312e-01, 5.00600e-01, 5.15791e-01, 7.47014e-01, 9.89239e-01",\
" 4.90958e-01, 5.04250e-01, 5.19316e-01, 7.50430e-01, 9.92668e-01",\
" 5.23086e-01, 5.36054e-01, 5.51137e-01, 7.82481e-01, 1.02379e+00",\
" 8.64012e-01, 8.77425e-01, 8.92406e-01, 1.12372e+00, 1.36567e+00");
}
rise_transition (delay_template_5x5) {
values( " 1.36210e-01, 1.41905e-01, 1.56679e-01, 5.25537e-01, 9.48208e-01",\
" 1.36473e-01, 1.42337e-01, 1.56860e-01, 5.26286e-01, 9.47712e-01",\
" 1.36207e-01, 1.41666e-01, 1.56713e-01, 5.26138e-01, 9.49231e-01",\
" 1.36096e-01, 1.41824e-01, 1.56735e-01, 5.26330e-01, 9.49932e-01",\
" 1.36206e-01, 1.41559e-01, 1.56349e-01, 5.25405e-01, 9.48210e -01");
}
}
timing () {
related_pin : "RSTZ";
timing_sense : negative_unate;
timing_type : preset;
sdf_cond : "D == 1’b0 && CLKZ == 1’b1";
when : "!D&CLKZ";
cell_rise (delay_template_5x5) {
values( " 4.57820e-01, 4.71661e-01, 4.87248e-01, 7.22043e-01, 9.64998e-01",\
" 4.57718e-01, 4.71643e-01, 4.87334e-01, 7.22005e-01, 9.64991e-01",\
" 4.60466e-01, 4.74305e-01, 4.89899e-01, 7.24712e-01, 9.67665e-01",\
" 4.92673e-01, 5.06301e-01, 5.21954e-01, 7.56644e-01, 1.00014e+00",\
" 8.33406e-01, 8.47834e-01, 8.63449e-01, 1.09814e+00, 1.34113e+00");
}
rise_transition (delay_template_5x5) {
values( " 1.41885e-01, 1.48031e-01, 1.63237e-01, 5.30797e-01, 9.51460e-01",\
" 1.42096e-01, 1.48431e-01, 1.62958e-01, 5.30169e-01, 9.50758e-01",\
" 1.41883e-01, 1.48278e-01, 1.63264e-01, 5.31190e-01, 9.53032e-01",\
" 1.41848e-01, 1.48140e-01, 1.63437e-01, 5.30919e-01, 9.53340e-01",\
" 1.41981e-01, 1.48135e-01, 1.62767e-01, 5.30309e-01, 9.51480e -01");
}
}
73
timing () {
related_pin : "RSTZ";
timing_sense : negative_unate;
timing_type : preset;
sdf_cond : "D == 1’b1 && CLKZ == 1’b0";
when : "D&!CLKZ";
cell_rise (delay_template_5x5) {
values( " 4.87175e-01, 5.00433e-01, 5.15574e-01, 7.46897e-01, 9.89023e-01",\
" 4.87283e-01, 5.00596e-01, 5.15744e-01, 7.46972e-01, 9.89166e-01",\
" 4.90837e-01, 5.04229e-01, 5.18439e-01, 7.49681e-01, 9.92582e-01",\
" 5.22787e-01, 5.36308e-01, 5.51227e-01, 7.82430e-01, 1.02448e+00",\
" 8.63439e-01, 8.76686e-01, 8.92590e-01, 1.12370e+00, 1.36597e+00");
}
rise_transition (delay_template_5x5) {
values( " 1.36215e-01, 1.42106e-01, 1.56698e-01, 5.25258e-01, 9.48119e-01",\
" 1.36589e-01, 1.42362e-01, 1.56790e-01, 5.26130e-01, 9.48166e-01",\
" 1.36523e-01, 1.41696e-01, 1.57098e-01, 5.26286e-01, 9.49539e-01",\
" 1.36201e-01, 1.41850e-01, 1.56712e-01, 5.26308e-01, 9.50025e-01",\
" 1.36275e-01, 1.41691e-01, 1.56400e-01, 5.25430e-01, 9.48126e -01");
}
}
timing () {
related_pin : "RSTZ";
timing_sense : negative_unate;
timing_type : preset;
sdf_cond : "D == 1’b1 && CLKZ == 1’b1";
when : "D&CLKZ";
cell_rise (delay_template_5x5) {
values( " 4.93928e-01, 5.07868e-01, 5.23590e-01, 7.58640e-01, 1.00161e+00",\
" 4.94065e-01, 5.08126e-01, 5.23852e-01, 7.58917e-01, 1.00190e+00",\
" 4.96857e-01, 5.10917e-01, 5.27213e-01, 7.62311e-01, 1.00531e+00",\
" 5.29714e-01, 5.43668e-01, 5.59404e-01, 7.94447e-01, 1.03714e+00",\
" 8.70753e-01, 8.84894e-01, 8.99749e-01, 1.13485e+00, 1.37778e+00");
}
rise_transition (delay_template_5x5) {
values( " 1.43522e-01, 1.49899e-01, 1.64296e-01, 5.31234e-01, 9.51589e-01",\
" 1.43540e-01, 1.49798e-01, 1.64244e-01, 5.30618e-01, 9.50898e-01",\
" 1.43423e-01, 1.49848e-01, 1.64768e-01, 5.31555e-01, 9.53240e-01",\
" 1.43387e-01, 1.49567e-01, 1.64373e-01, 5.31715e-01, 9.54051e-01",\
" 1.43326e-01, 1.49680e-01, 1.64090e-01, 5.30670e-01, 9.51812e -01");
}
}
}
pin (RSTZ) {
direction : input;
related_ground_pin : AGND;
related_power_pin : DVDD;
capacitance : 5.86744e-03;
rise_capacitance : 5.86744e-03;
fall_capacitance : 4.27833e-03;
timing () {
related_pin : "CLKZ";
timing_type : recovery_falling;
sdf_cond : "D_SDFCHK ";
when : "D";
rise_constraint (constraint_template_3x3) {
values( " 2.72365e-01, 2.74992e-01, 6.49742e-01" ,\
" 2.69279e-01, 2.72764e-01, 6.47085e-01" ,\
" 2.94540e-02, 2.72557e-02, 3.47923e-01");
}
}
timing () {
related_pin : "CLKZ";
timing_type : removal_falling;
sdf_cond : "D_SDFCHK ";
when : "D";
rise_constraint (constraint_template_3x3) {
values( " 2.72365e-01, 2.74992e-01, 6.49742e-01" ,\
" 2.69279e-01, 2.72764e-01, 6.47085e-01" ,\
" 2.94540e-02, 2.72557e-02, 3.47923e-01");
}
}
timing () {
related_pin : "RSTZ";
timing_type : min_pulse_width;
sdf_cond : "nCLKZ_SDFCHK ";
when : "!CLKZ";
fall_constraint (mpw_constraint_template_3x1) {
values( " 3.82356e-01, 3.82379e-01, 3.81846e-01");
}
}
timing () {
74
related_pin : "RSTZ";
timing_type : min_pulse_width;
sdf_cond : "CLKZ_SDFCHK ";
when : "CLKZ";
fall_constraint (mpw_constraint_template_3x1) {
values( " 3.52879e-01, 3.52932e-01, 3.54878e-01");
}
}
timing () {
related_pin : "RSTZ";
timing_type : min_pulse_width;
sdf_cond : "nCLKZ_SDFCHK ";
when : "!CLKZ";
fall_constraint (mpw_constraint_template_3x1) {
values( " 4.00972e-01, 4.01879e-01, 4.02756e-01");
}
}
timing () {
related_pin : "RSTZ";
timing_type : min_pulse_width;
sdf_cond : "CLKZ_SDFCHK ";
when : "CLKZ";
fall_constraint (mpw_constraint_template_3x1) {
values( " 3.89175e-01, 3.89120e-01, 3.93248e-01");
}
}
internal_power () {
when : "D&&CLKZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.30312e-04, 1.66100e-03, 2.23401e-03, 1.36325e-03, 4.54374e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.17475e-04, 1.34940e-03, 1.66961e-03, 2.20543e-03, 3.00145e -03");
}
}
internal_power () {
when : "!D&&! CLKZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.30039e-04, 1.65579e-03, 1.74664e-03, 1.38427e-03, 3.33778e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.18067e-04, 1.36672e-03, 2.06957e-03, 2.03019e-03, 3.31074e -03");
}
}
internal_power () {
when : "D&&! CLKZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.30033e-04, 1.65571e-03, 1.74615e-03, 1.39254e-03, 3.34144e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.18064e-04, 1.36671e-03, 1.71819e-03, 2.00790e-03, 3.31042e -03");
}
}
internal_power () {
when : "!D&&CLKZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.29985e-04, 1.65764e-03, 1.64511e-03, 1.35389e-03, 3.45771e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.18002e-04, 1.36715e-03, 2.04638e-03, 2.03635e-03, 3.31314e -03");
}
}
}
pin (CLKZ) {
direction : input;
related_ground_pin : AGND;
related_power_pin : DVDD;
capacitance : 8.43161e-03;
rise_capacitance : 8.43161e-03;
fall_capacitance : 4.28295e-03;
timing () {
related_pin : "CLKZ";
timing_type : min_pulse_width;
sdf_cond : "RSTZ_SDFCHK ";
when : "RSTZ";
rise_constraint (mpw_constraint_template_3x1) {
values( " 3.10317e-01, 3.11284e-01, 0.00000e+00");
}
75
fall_constraint (mpw_constraint_template_3x1) {
values( " 4.62515e-01, 4.61870e-01, 0.00000e+00");
}
}
timing () {
related_pin : "CLKZ";
timing_type : min_pulse_width;
sdf_cond : "RSTZ_SDFCHK ";
when : "RSTZ";
fall_constraint (mpw_constraint_template_3x1) {
values( " 3.75186e-01, 3.75917e-01, 0.00000e+00");
}
rise_constraint (mpw_constraint_template_3x1) {
values( " 3.70301e-01, 3.70350e-01, 0.00000e+00");
}
}
internal_power () {
when : "!D&&! RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.39644e-04, 1.69639e-03, 1.72471e-03, 1.53329e-03, 6.50858e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.29024e-04, 1.39325e-03, 2.10464e-03, 2.36695e-03, 2.68840e -03");
}
}
internal_power () {
when : "D&&RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.39638e-04, 1.70242e-03, 1.72348e-03, 1.46557e-03, 6.08983e -03");
}
}
internal_power () {
when : "D&&! RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.39662e-04, 1.70276e-03, 2.28185e-03, 1.51687e-03, 6.10530e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.28740e-04, 1.40156e-03, 1.73976e-03, 2.25431e-03, 2.92578e -03");
}
}
internal_power () {
when : "!D&&RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.39654e-04, 1.69793e-03, 1.73591e-03, 1.47540e-03, 6.52944e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.29024e-04, 1.39473e-03, 2.12356e-03, 2.37709e-03, 2.68631e -03");
}
}
internal_power () {
when : "!D&&RSTZ&&Q&&!QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.41216e-04, 1.70263e-03, 1.64980e-03, 1.32288e-03, 3.64495e -03");
}
}
internal_power () {
when : "D&&RSTZ&&Q&&!QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.41136e-04, 1.70756e-03, 1.63928e-03, 1.29488e-03, 3.26608e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.27837e-04, 1.39323e-03, 1.67781e-03, 2.08697e-03, 3.31671e -03");
}
}
}
pin (D) {
direction : input;
related_ground_pin : AGND;
related_power_pin : DVDD;
capacitance : 8.82012e-03;
rise_capacitance : 8.27858e-03;
fall_capacitance : 8.82012e-03;
timing () {
related_pin : "CLKZ";
timing_type : setup_falling;
sdf_cond : "RSTZ_SDFCHK ";
76
when : "RSTZ";
fall_constraint (constraint_template_3x3) {
values( " 2.56348e-01, 2.69563e-01, 6.51680e-02" ,\
" 2.43133e-01, 2.56348e-01, 5.19531e-02" ,\
" 6.30633e-01, 5.82812e-01, 4.39453e-01");
}
rise_constraint (constraint_template_3x3) {
values( " 1.95312e-01, 2.69563e-01, 1.66766e-01" ,\
" 2.06512e-01, 1.95313e-01, 1.55566e-01" ,\
" 4.71941e-01, 4.60742e-01, 1.09863e-01");
}
}
timing () {
related_pin : "CLKZ";
timing_type : hold_falling;
sdf_cond : "RSTZ_SDFCHK ";
when : "RSTZ";
fall_constraint (constraint_template_3x3) {
values( " 1.56348e-01, 1.57821e-01, 1.571568 -02" ,\
" 1.54868e-01, 2.56348e-01, 4.19531e-02" ,\
" 5.42158e-01, 5.84270e-01, 5.98125e-01");
}
rise_constraint (constraint_template_3x3) {
values( " 1.46484e-01, 1.35285e-01, 1.30145e-01" ,\
" 1.57684e-01, 1.46484e-01, 1.18945e-01" ,\
" 5.08562e-01, 4.97363e-01, 2.31934e-01");
}
}
internal_power () {
when : "!CLKZ&&RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.14162e-04, 2.43611e-03, 3.48287e-03, 4.42437e-03, 4.63723e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.00483e-04, 1.98471e-03, 3.80777e-03, 4.08375e-03, 4.58779e -03");
}
}
internal_power () {
when : "CLKZ &&! RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.11440e-04, 2.48136e-03, 3.39925e-03, 3.61762e-03, 6.41094e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.07910e-04, 2.07754e-03, 3.25180e-03, 4.27759e-03, 6.62561e -03");
}
}
internal_power () {
when : "!CLKZ&&RSTZ&&Q&&!QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.10245e-04, 2.43800e-03, 3.46061e-03, 4.49253e-03, 4.63295e -03");
}
fall_power (passive_power_template_5x1) {
values (" 4.98310e-04, 1.97562e-03, 2.99561e-03, 3.97018e-03, 4.55540e -03");
}
}
internal_power () {
when : "!CLKZ &&! RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.14206e-04, 2.43576e-03, 4.54585e-03, 4.52552e-03, 4.64820e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.00530e-04, 1.98438e-03, 3.00823e-03, 4.08073e-03, 4.58666e -03");
}
}
internal_power () {
when : "CLKZ&&RSTZ &&!Q&&QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
values (" 5.11705e-04, 2.48327e-03, 3.40253e-03, 3.58453e-03, 6.37407e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.07813e-04, 2.07400e-03, 3.21688e-03, 4.26208e-03, 6.68208e -03");
}
}
internal_power () {
when : "CLKZ&&RSTZ&&Q&&!QZ";
related_pg_pin : DVDD;
rise_power (passive_power_template_5x1) {
77
values (" 5.11647e-04, 2.48068e-03, 4.54681e-03, 3.54124e-03, 6.01854e -03");
}
fall_power (passive_power_template_5x1) {
values (" 5.07875e-04, 2.07345e-03, 3.92005e-03, 4.18012e-03, 6.83030e -03");
}
}
}
}
}
78
