Digital Circuit Wear-out due to Electromigration in

Semiconductor Metal Lines

A Thesis Presented to the

Electrical Engineering Department Faculty of

California Polytechnic State University, San Luis Obispo

In Partial Fulfillment

Of the Requirements for the

Master of Science Degree in Electrical Engineering

By

Gregory Ross Wilkinson

November 2009

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© 2009 Gregory Ross Wilkinson

ALL RIGHTS RESERVED

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COMMITTEE MEMBERSHIP

TITLE: Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines AUTHOR: Gregory Ross Wilkinson DATE SUBMITTED: November 2009 COMMITTEE CHAIR: Dr. John Oliver, Assistant Professor Electrical Engineering

COMMITTEE MEMBER: Dr. James Harris, Professor Emeritus Electrical Engineering

COMMITTEE MEMBER: Dr. Alberto Jimenez, Professor Mathematics

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ABSTRACT

Title: Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines Author: Gregory Ross Wilkinson

With the constant scaling of semiconductor devices, reliability of these devices is a huge

concern. One of the biggest reliability issues is a phenomenon known as electromigration (EM)

[1] [2]. Electromigration is the transport of material caused by the gradual movement of

the ions in a conductor due to the momentum transfer between conducting electrons and

diffusing metal atoms [27]. The damage induced by electromigration appears as the formation of

voids and hillocks, resulting in electrical discontinuity.

Based on previous Electromigration research [15], I have created a tool chain that

identifies where electromigration is likely to occur in large-scale integrated circuits. Using this

tool chain, it is possible to identify the mean-time to failure (MTTF) of several common and high

priority circuits such as complex adders and memories. Furthermore, this tool chain allows

designers to isolate weak-points in these circuits to improve the overall MTTF of the circuit. The

result is that with a few simple changes, circuits can be redesigned to increase the MTTF, at

minimal cost to the system.

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ACKNOWLEDGEMENTS

First of all, I would like to express my gratitude towards Dr. John Oliver for giving me the

privilege to work on this research project. I fully appreciate the time, effort, and guidance he

provided me.

I would like to give special thanks to Emanuel Tarog for being a great partner on this project and

being so patient along the way. His knowledge and constant advice have helped me in

completing such a great project.

I would like to thank Dr. James Harris for being an excellent committee member and constantly

motivating me towards success.

I would like to thank Dr. Alberto Jimenez for giving me great advice on my educational and

career goals throughout the past five years.

Finally, I would like to thank my family and friends for their love and support throughout my

educational career.

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TABLE OF CONTENTS

LIST OF FIGURES ............................................................................................................................................... VIII

LIST OF TABLES .................................................................................................................................................... IX

CHAPTER 1. INTRODUCTION ........................................................................................................................... 1

CHAPTER 2. BACKGROUND ............................................................................................................................. 4

2.1 FAILURE MECHANISMS OF ELECTROMIGRATION ................................................................................................. 5 2.1.1 Metallurgical Statistical Properties of the Conducting Film ...................................................................... 5 2.1.2 Thermal Acceleration Process .................................................................................................................... 7 2.1.3 Healing Effects ............................................................................................................................................ 8

2.2 PAST RESEARCH .................................................................................................................................................. 8 2.2.1 Black’s Equation ......................................................................................................................................... 9 2.2.2 Numerical Simulation .................................................................................................................................. 9 2.2.3 Atomic Flux Divergence ............................................................................................................................ 10

2.3 CREATION OF A MATHEMATICAL MODEL .......................................................................................................... 10 2.3.1 Calibration ................................................................................................................................................ 10 2.3.2 How is the Model Used ............................................................................................................................. 17

CHAPTER 3. SYSTEM DESCRIPTION............................................................................................................ 19

3.1 GENERAL DESCRIPTION ..................................................................................................................................... 19 3.2 SYSTEM OVERVIEW AND REQUIREMENTS .......................................................................................................... 20

3.2.1 Design Tools Used in the System .............................................................................................................. 22 3.2.2 Software Tools I’ve Created ...................................................................................................................... 23

3.3 CIRCUIT LAYOUT AND CREATION ...................................................................................................................... 24 3.3.1 Choice of Circuit Fabrication Technology ............................................................................................... 25 3.3.2 Choice of Circuits ..................................................................................................................................... 26 3.3.3 Layout Preferences.................................................................................................................................... 28 3.3.4 Creation of Spice Netlists .......................................................................................................................... 28

3.4 CREATION OF INTERMEDIATE FILES ................................................................................................................... 29 3.4.1 Floorplan file ............................................................................................................................................ 29 3.4.2 Relationship File ....................................................................................................................................... 30 3.4.3 Manual creation of floorplans and relationship files ................................................................................ 30 3.4.4 Power Trace File....................................................................................................................................... 32 3.4.5 Raw current/voltage data from spice ........................................................................................................ 32

3.5 SOFTWARE TOOLS/THE PROGRAM ..................................................................................................................... 33 3.5.1 Extracting Runtime Information ................................................................................................................ 34 3.5.2 Creating a catalog..................................................................................................................................... 35 3.5.3 Assigning MOSFETs to regions ................................................................................................................ 36 3.5.3 Monitoring of circuit usage ....................................................................................................................... 37 3.5.4 Creation of the Power Trace File ............................................................................................................. 39 3.5.5 Calling HotSpot ......................................................................................................................................... 39 3.5.6 Changing Metal Widths ............................................................................................................................. 39 3.5.6 Calculating MTTF ..................................................................................................................................... 40

3.6 ADDITION TOOLS ............................................................................................................................................... 40 3.6.3 Converting the LTSpice Utility data file .................................................................................................... 41 3.6.4 Calculating Average Power for each Region ............................................................................................ 41 3.6.5 The Speed Tester ....................................................................................................................................... 42 3.6.6 Gathering the Results ................................................................................................................................ 44

CHAPTER 4. CIRCUIT EVALUATION ........................................................................................................... 46

4.1 TESTING THE CIRCUITS ...................................................................................................................................... 46 4.2 VERIFYING THE MODELS ................................................................................................................................... 47

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4.3 THE INVERTER ................................................................................................................................................... 48 4.3.1 The effects of Input and Rail Voltage ........................................................................................................ 49 4.3.2 The effects of Temperature ........................................................................................................................ 50 4.3.3 The effects of Input Frequency .................................................................................................................. 53

4.4 COMPLEX CIRCUITS ........................................................................................................................................... 55 4.4.1 Adders ....................................................................................................................................................... 55 4.4.2 Ripple-Carry Adders ................................................................................................................................. 55 4.4.3 Kogge-Stone Adders .................................................................................................................................. 57 4.4.4 8x8 Register File ....................................................................................................................................... 59

4.5 FAILURES, ASSOCIATED PERFORMANCE FLAWS AND POTENTIAL FIXES ........................................................... 61 4.5.1 Input Frequency ........................................................................................................................................ 62 4.5.2 Skin Effect ................................................................................................................................................. 62 4.5.3 Ideal Current Density ................................................................................................................................ 63 4.5.4 Interconnect Sizing .................................................................................................................................... 66 4.5.5 Temperature and Resistivity ...................................................................................................................... 67

CHAPTER 5. IMPROVING DESIGN AND WAYS TO MINIMIZE FAILURE ...... ..................................... 72

5.1 IMPROVING MTTF OF THE XOR GATE .............................................................................................................. 73 5.1.1 Increasing Interconnect Width .................................................................................................................. 73 5.1.2 Decreasing Size of Weak Link ................................................................................................................... 74 5.1.3 Improving Circuit Speed ........................................................................................................................... 74 5.1.4 Failure Time Improvements ...................................................................................................................... 75 5.1.5 Affects On Power and Delay ..................................................................................................................... 76

5.2 RESULTS ON LARGER CIRCUITS ..................................................................................................................... 77 5.2.1 Kogge-Stone Adder ................................................................................................................................... 77 5.2.2 Register File .............................................................................................................................................. 82

CHAPTER 6. CONCLUSIONS ........................................................................................................................... 87

CHAPTER 7. WORKS CITED ............................................................................................................................ 90

APPENDICES 93

APPENDIX A: BACKGROUND INFORMATION ............................................................................................................ 93 Layout Process ................................................................................................................................................... 93 Layout Diagrams for Small Circuits .................................................................................................................. 95 Circuit Diagrams for Small Circuits .................................................................................................................. 97 CMOS Kogge-Stone ........................................................................................................................................... 99

APPENDIX B: SMALL CIRCUIT EVALUATION ......................................................................................................... 104 The NAND and NOR Gates .............................................................................................................................. 104 The XOR-gate ................................................................................................................................................... 105 The AND and OR Gates ................................................................................................................................... 107 Multiplexer (MUX) ........................................................................................................................................... 108 Full Adder ........................................................................................................................................................ 109 Decoder ............................................................................................................................................................ 110 Summary .......................................................................................................................................................... 110

APPENDIX C: RESULTS FOR SMALL CIRCUITS ....................................................................................................... 112 Improving the MUX ......................................................................................................................................... 114 Improving a Full Adder .................................................................................................................................... 116 Maximum Improvement .................................................................................................................................... 117 Summary for Simple Circuits ........................................................................................................................... 119

APPENDIX D: L IST OF ACRONYMS ......................................................................................................................... 120 APPENDIX E: LIST OF EQUATIONS ......................................................................................................................... 121

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LIST OF FIGURES

Figure 2.1: Void and Hillock in metal lines [25]. ........................................................................... 5

Figure 2.2: Schematic illustration of grains, grain boundaries, ...................................................... 6

Figure 2.3: Thermal acceleration loop during electromigration. .................................................... 7

Figure 2.4: Temperature/Current Density Relationship................................................................ 12

Figure 2.5: Current Density/MTTF Relationship ......................................................................... 12

Figure 2.6: Recreated Temperature/Current Density Relationship ............................................... 13

Figure 2.7: Recreated Current Density/MTTF Relationship ........................................................ 14

Figure 2.8: Reworked Current Density/MTTF Relationship for Varying Temperatures ............. 16

Figure 3.1: Overall System Block Diagram of proposed system. ................................................. 21

Figure 3.2: Block diagram for 16-bit Kogge-Stone prefix adder network ................................... 27

Figure 3.3: Kogge-Stone critical path of 8 logic stages for 16-bits (not all gate inputs shown) .. 27

Figure 3.4: Floorplan Representation for Hotspot ........................................................................ 31

Figure 3.5: Use of Toggle tool to create floorplan files ................................................................ 31

Figure 3.6: Data as it appears in the file ....................................................................................... 38

Figure 3.7: The left Riemann sum of the data .............................................................................. 38

Figure 3.8: Showing method for manually finding delay ............................................................. 42

Figure 3.9: Error possibility in Delay calculations ....................................................................... 44

Figure 4.1: MTTF Improvement vs. Current Density Plot Using Created Model ........................ 48

Figure 4.2: Effects of Increased Rail Voltage on MTTF .............................................................. 49

Figure 4.3: Effects of Increased Rail Voltage on Current Density ............................................... 50

Figure 4.4: Effects of Temperature on MTTF for Inverter ........................................................... 51

Figure 4.5: Power vs. MTTF plot for Inverter .............................................................................. 52

Figure 4.6: Effects of Input Frequency on Power for Inverter ..................................................... 53

Figure 4.7: MTTF vs. Input Speed for Various Interconnect Sizing ............................................ 54

Figure 4.8: Comparison of 8-Bit, 16-Bit, and 32-Bit Adders ....................................................... 57

Figure 4.9: Critical Path of the KS Adder..................................................................................... 58

Figure 4.10: Effects of Starting Ambient Temperature, Rail Voltage and Input speed for Kogge Stone Adder .................................................................................................................................. 59

Figure 4.11: Input Frequnecy vs. MTTF when Temperature = 373K .......................................... 64

Figure 4.12: Input Frequency vs. MTTF when Temperature = 423K .......................................... 65

Figure 4.13: Representation of Varying Interconnect Sizing ....................................................... 66

Figure 4.14: RC time delay for 8 Bit RCA ( Delay is 1.43ns temp = 200) .................................. 68

Figure 4.15: RC time delay for 8 Bit RCA (Delay is 1.32 ns Temp = 100) ................................. 68

Figure 4.16: MTTF vs. Input speed at Simulated and Constant Temperature (weak link XOR of Kogge-Stone) ................................................................................................................................ 70

Figure 4.17: Graph Showing MTTF for Constant Current Density at Varying Starting Ambient Temperatures................................................................................................................................. 71

Figure 5.1: MTTF Improvement of XOR Gate for Various Changes .......................................... 76

Figure 5.2: Improvements for Subcircuits of Kogge-Stone Adder ............................................... 78

Figure 5.3: Results on Kogge-Stone Adder for Various Fixes @ 25MHz ................................... 79

Figure 5.4: Results on Kogge-Stone Adder for Various Fixes @ 400MHz ................................. 80

Figure 5.5: MTTF Results on Register File MUX for Various Fixes ........................................... 82

Figure 5.6: MTTF Results on Register File Decoder for Various Fixes ...................................... 83

Figure 5.7: Results on Register File for Various Fixes @ 25MHz ............................................... 84

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Figure 5.8: Results on Register File for Various Fixes @ 400MHz ............................................. 85

Figure A.1: Basic Layout of 2-input XOR gate, showing key components. ................................ 93

Figure A.2: Inverter with S/D Metal ............................................................................................. 95

Line Width of 75 nm ..................................................................................................................... 95

Figure A.3: Inverter with S/D Metal Line Width of 150 nm ........................................................ 95

Figure A.4: The layout for a 2-1 MUX ......................................................................................... 96

Figure A.5: The layout for a Full Adder ....................................................................................... 96

Figure A.6: Layout of the 3-to-8 Decoder. ................................................................................... 96

Figure A.7: Layout of a 12 Transistor SRAM Cell ...................................................................... 97

Figure A.8: The Circuit for a NAND-gate (left), and a NOR-gate (right).................................... 97

Figure A.9: Transistor Network that Creates an Exclusive-OR function. .................................... 98

Figure A.10: 2-1 MUX Circuit Diagram ...................................................................................... 98

Figure A.11: Full Adder Circuit Diagram..................................................................................... 99

Figure A.12: 12 Transistor SRAM Circuit Diagram .................................................................... 99

Figure A.13: Even layer tiled CMOS PPA circuit (inverted inputs, non-inverted outputs) ....... 100 Figure A.14: Even layer tiled CMOS-OPL PPA circuit layout cell ........................................... 100

Figure A.15: Odd Layer Tiled CMOS PPA circuit (non-inverted inputs, inverted outputs) ...... 101 Figure A.16: Odd Layer Tiled CMOS-OPL PPA circuit cell ..................................................... 101

Figure A.17: CMOS OPL layout circuits for AND (left) and XOR (right) gates used for the Pi and Gi signals .............................................................................................................................. 102

Figure A.18: Complete 16-bit Kogge-Stone Adder layout ......................................................... 103

Figure B.1: NMOS1 Source Current for 25MHz........................................................................ 106

Figure B.2: NMOS1 Source Current for 400MHz...................................................................... 106

Figure C.1: Delay for Various Changes to Small Circuits @ 25 MHz ....................................... 112

Figure C.2: Delay for Various Changes to Small Circuits @ 400 MH ...................................... 113

Figure C.3: Power Consumption for Various Changes to Small Circuits at 25 MHz ................ 113 Figure C.4: Power Consumption for Various Changes to Small Circuits at 400 MHz .............. 114

Figure C.5: MTTF Improvement of the MUX for various changes ........................................... 115

Figure C.6: MTTF Improvement of the Full Adder for various changes ................................... 116

Figure C.7: Overall MTTF Improvement for MUX and Full Adder .......................................... 117

Figure C.8: Delay for the fixed MUX and Full Adder ............................................................... 118

Figure C.9: Power Consumption for fixed MUX and Full Adder .............................................. 118

LIST OF TABLES

Table 5.1: Comparison of Kogge-Stone fixes ............................................................................... 81

Table 5.2: Comparison of Register File Fixes .............................................................................. 86

Table D.1: List of Acronyms ...................................................................................................... 120

1

Chapter 1. INTRODUCTION

This paper will specifically address the failures in metal lines caused by electromigration,

specifically the formation of voids and hillocks responsible for the destruction of the

interconnect material yielding electrical discontinuity [1]. Electromigration is the transport of

material caused by the gradual movement of the ions in a conductor due to

the momentum transfer between conducting electrons and diffusing metal atoms.

Electromigration’s effects are found directly in the metal lines and are a dominating cause of

digital circuit failure.

With the scaling down process of microcircuits, the effects of electromigration have

become increasingly severe. Many of the subcircuits for a microprocessor are used much more

than others and there are especially important subcircuits that are absolutely necessary for

functionality. Binary adders and high speed memory are both an absolute necessity for

microprocessors and are the most frequently used subcircuits within a microprocessor and if

those fail, then the instrument that it controls fails as well.

I have researched one prominent mechanism of failure and have modified existing

mathematical models that will allow me to predict the mean time to failure for these subcircuits.

Upon obtaining a failure time, I will also be able to pinpoint the likely failure locations. This will

give designers, device physics engineers and others valuable information early on in the design

phase of complex digital circuits.

I will construct these circuits in Electric (an open-source layout tool) and PSpice and try

to determine the sites of failure. I will be using HotSpot (thermal monitoring tool) for all thermal

measurements and have also developed a small set of software tools that allow me to collect and

massage necessary data and obtain results.

2

This thesis presents a method for determining and monitoring the failure of complex

digital circuits caused by electromigration. Furthermore, this thesis specifically addresses the

electromigration failure type and shows the development of a system that can estimate the failure

time and likely failure locations due to electromigration, ideally down to the transistor level.

Overall system architecture and test methodology will be discussed.

Chapter two of this thesis presents additional background material about electromigration

and its effects. Section 2.1 describes the three predominant failure mechanisms associated with

electromigration, those being the metallurgical statistical properties of the conducting film, the

thermal acceleration process and the healing effects. Section 2.2 discusses past research on

electromigration and the associated methods for estimating failure time. Finally, section 2.3

concerns the creation of a mathematical model to predict circuit lifetime.

Chapter three outlines the actual system implementation and the requirements for the

system. Section 3.1 provides a general description of the tool chain and the goals it seeks to

achieve. Section 3.2 goes over the system requirements and the necessary tools the system needs

to be successful. Section 3.3 gives an overview of the layout process, and also describes the

various circuits used in the tool chain. Section 3.4 concerns the creation of various intermediate

files for the system. Section 3.5 describes “the program”, which joins all system components

together, and finally, section 3.6 discusses the few additional tools needed before the system can

be implemented.

Chapter four contains all the circuit evaluation work, discusses exactly what happens and

why and then pinpoints failure locations for the various circuits. Section 4.1 describes the testing

process, while section 4.2 verifies the created failure model. Section 4.3 shows initial test results

3

for an inverter, and section 4.4 shows that for complex circuits. Section 4.5 goes into detail on

the actual performance flaws of the circuits and outlines areas of improvement.

Chapter five addresses ways to improve design and minimize failure time. Section 5.1

shows improvement techniques for the XOR gate, and section 5.2 shows improvement

techniques for larger circuits, like the Kogge-Stone adder and 8x8 register file.

Chapter six summarizes the project, briefly restating the causes for electromigration and

the methods to minimize its effects based on the findings within the paper. The set of

Appendices include background information, a list of terms and equation, and circuit and layout

diagrams. Also, small circuit evaluations and results can be seen here.

4

Chapter 2. BACKGROUND

Prior to discussing the mathematical models created, and the implementation of my

method for locating failures, this chapter will provide some basic definitions and theory related

to electromigration and the system’s operation. As mentioned earlier, these tools attempt to

diagnose both simple and complex circuits in detail, predict failure times and pinpoint the

locations of those failures. This background will specifically discuss the definition of

electromigration and associated failure mechanisms, past research in the area, and finally the

creation of the mathematical model used for determining failure time.

As microcircuits are scaled down, the density of electric current in interconnecting metal

lines increases, as does the temperature of the actual device. Electromigration is generally

considered to be the result of momentum transfer from the electrons, which move in the applied

electric field, to the ions which make up the lattice of the interconnect material [3][4]. The

metallic atoms constructing the line are transported by an electron wind. Under these conditions,

electromigration can lead to the electrical failure of interconnects in relatively short times,

reducing the circuit lifetime to an unacceptable level. It is therefore of great technological

importance to understand and control electromigration failure in thin film interconnects.

The damage induced by electromigration appears as the formation of voids (which occur

along the length of the line) and hillocks (electrons “push” the metal atoms in direction of

current). With the growth of these voids in the metal lines, electrical discontinuity arises [5][6].

Recent research has shown that both of these failure modes are strongly affected by the

microstructure of the line and can, therefore be delayed or overcome by metallurgical changes

that alter the microstructure.

5

Figure 2.1: Void and Hillock in metal lines [25].

Above is a picture under a microscope showing both a void and hillock inside a metal

line. Both are effects of electromigration. Because of high current densities in the metal

interconnects, the electrons 'push' the metal atoms in the direction of the current. Voids at one

end of the metal line, and bumps (Hillocks) at the other end are the result of this electron wind.

2.1 Failure Mechanisms of Electromigration

There are three predominant failure mechanisms in the electromigration process. They

are (a) the metallurgical statistical properties of the conducting film, (b) the thermal acceleration

process and (c) the healing effects. Here, they will be explained in more detail.

2.1.1 Metallurgical Statistical Properties of the Conducting Film

The metallurgical properties of a conductor film refer to the microstructure parameters of

the actual conductor material, including grain size distribution, and the distribution of grain

6

boundary misorientation angles, and the inclinations of grain boundaries with respect to electron

flow [1][9].

Figure 2.2: Schematic illustration of grains, grain boundaries, grain boundary misorientation angles, and inclination angles.

Aftger Nikawa Kiyoshi, IEEE Int. Reliab. Phys. Symp., CH1619-6, 175 (1981). © IEEE 1981.

Because these parameters appear to be random, they can only be dealt with statistically. As

illustrated in the figure, the misorientation angle, θ, between the two grains defining the grain

boundary determine the mobility of atoms in that boundary.

It is also important to look at the grain boundary inclination with respect to electron flow,

φ, partially determined by grain size variation, for what ϕ determines the effectiveness of the

applied field for that grain boundary; finally, the grain size variation determines the change in the

number of atomic paths across a cross section of the conductor line. The variation of above

parameters over a film leads to a nonuniform distribution of atomic flow rate. As a result, a

nonzero atomic flux divergence exists at the places where the number of atoms flowing into the

area is not equal to the number of atoms flowing out (6). If divergence is greater than zero, there

is mass depletion, and if the divergence is less than zero, there is mass accumulation, which leads

to voids or hillocks [1] [10].

7

2.1.2 Thermal Acceleration Process

The second failure mechanism is the thermal acceleration process, which refers to the

acceleration process of electromigration damage due to the local temperature rising. It is only

possible to have a uniform temperature distribution before electromigration damage occurs.

Immediately following the formation of a void, the current density increases (current crowding)

in its vicinity as it reduces the cross sectional area of the conductor. Joule heating is proportional

to the square of current density, which as a result, leads to a local temperature increase around

the void, accelerating the voids growth. This process goes on until the void is large enough to

break the line [3] [6]. The thermal acceleration loop is shown in the figure below.

Figure 2.3: Thermal acceleration loop during electromigration. Aftger Nikawa Kiyoshi, IEEE Int. Reliab. Phys . Symp., CH1619-6, 175 (1981). © IEEE 1981.

When the heat dissipation through the film substrate is poor, the thermal run-away process often

becomes the domination electromigration failure mechanism. Also, because of the lack of control

on temperature uniformity, a temperature gradient may exist along a conductor line even before

8

the formation of damage. This temperature gradient itself can lead to a nonuniform flux

divergence (mobility of atoms depends on this), thus in order to model electromigration failure

properly I must have an accurate temperature determination along the conductor film.

2.1.3 Healing Effects

The last of the failure mechanisms is the healing effects, specifically those caused by the

atomic flow of electrons opposite in direction to the electron wind [6]. This backflow of mass is

caused by things such as temperature and/or concentration gradients that result from

electromigration damage. The system is essentially aggravated from its stable state. It is initiated

once a redistribution of mass has begun to form. This helps in reducing the failure rate during

electromigration and somewhat heals the damage after the current is removed. Because of this

mass backflow, there exists a threshold density for electromigration to become effective. This

value corresponds to a minimum energy barrier that the atoms have to overcome to balance off

the backflow driving forces. It is important to understand these failure mechanisms so one can

possibly reduce electromigration effects.

2.2 Past Research

The sections below briefly describe some past research and techniques used in estimating

the effects of electromigration. The first is known as Black’s equation and dates all the way back

to 1969. The second method is known as numerical simulation, while the last method dives into

extreme detail on the actual physics behind electromigration. All are good methods for obtaining

realistic data pertaining to electromigration and its effects.

My method however, creates a new model for calculating MTTF and pinpointing metal

failures while being very user friendly. From a user standpoint, any catalog of laid-out circuits

9

can be used. There is a bit of manual labor that must be done in creating what’s known as a

floorplan, but this will all be discussed in chapter three. The software tools do most of the work

and keep track of the majority of data. The user must make some minor tweaks to circuits while

testing for improvements, but they are done easily and then dumped back into software.

2.2.1 Black’s Equation

J.R Black was the first to develop an empirical formula for calculating the MTTF (mean

time to failure) of a semiconductor circuit due to electromigration. The equation is as follows

(J.R Black – electromigration) [14][15]:

������� . �

Here, A is a constant, j is the current density, n is a model parameter, Q is the activation energy

in eV (electron volts), k is Boltzmann constant, T is the absolute temperature in K, and w is the

width of the metal wire. The model is abstract, not based on a specific physical model, but

flexibly describes the failure rate dependence on the temperature, the electrical stress, and the

specific technology and materials. The values for A, n, and Q are found by fitting the model to

experimental data. This is not a universal method for determining the lifetime of a circuit, as

many long term experiments are necessary for the respective line shapes, despite the fact that the

lines are made of the same metallic film.

2.2.2 Numerical Simulation

The conventional method in determining failure location is Numerical Simulation [16]. The

main purpose of this is to clarify the damage mechanisms. There was also a way in which to

10

evaluate threshold current density, j th, yet this assumed that the product of threshold and line

length was constant [16]. This is simple and easy, however the effect of line shape on j th is not

considered (Application is limited to only straight line). The constant is also temperature

dependent.

2.2.3 Atomic Flux Divergence

More recently, there was a unified approach to dealing with electromigration based on atomic

flux divergence (AFD). The AFD-based simulation of failure process [2][9] is universal. Once

the film characteristic constants are obtained, the failure prediction of any shaped line is possible

under arbitrary operating conditions. This allows for an accurate prediction for not only lifetime

but also failure site. Second, the AFD-based simulation of electromigration behavior [2] shows

that AFD corresponds with actual amount of damage. Film characteristic constants can be

derived by simple experiments to measure the amount of damage. Finally, there is the AFD-

based simulation for building-up process of atomic density distribution or what is called the

incubation period. This too is universal and accurate, as once the film characteristic constants are

obtained, the evaluation of the threshold in any shaped line is possible under arbitrary

temperature [2].

2.3 Creation of a Mathematical Model

2.3.1 Calibration

Because circuits were not fabricated for this project, Black’s equation as well as the

numerical simulation and AFD methods for determining failures time can only be used as

guidelines. The constraints and variables cannot be determined experimentally, and require more

11

of a device physics approach to implement. Thus, the creation of my own mathematical model

was necessary. Using past research as a guideline, and combining this research with data from a

variety of papers, a legitimate model was formed. The two biggest factors in obtaining an

accurate MTTF model are temperature and current density of the circuit. However, there is no

direct correlation between MTTF, temperature and current density. A variety of papers show

relationships between any two of these.

Data points from these papers were plotted in Microsoft Excel and an exponential relationship

between them was found using some extrapolation. For example, one paper [25] shows the

relationship between current density and temperature, while another [26] shows the relationship

between current density and MTTF. Because of the ongoing debate as to which model is the

most accurate, this method is just as valid, and the created model can be used.

Again, one major drawback to this is that there is not a purely mathematical relationship between

failure time, temperature and current density. In figure 2.4 [25] the data represents a graphical

relationship between temperature and current density. Notice that in the figure, the temperature

range is between 200 and 230 degrees Celsius. For this project, high temperature is assumed, as

electromigration does not take affect at low temperature values. As can be seen, the relationship

is clearly exponential and temperature sharply increases with the higher current densities. For

example, the difference in temperature between current densities of 1.1 x 106 and 2.1 x 106 is

only a few degrees. Yet the difference between 3.1 x 106 and 4.1 x 106 is much more significant.

This relationship is found in a variety of papers, yet none of the basis use it the basis for a model.

12

Figure 2.4: Temperature/Current Density Relationship

Figure 2.5 [26] shows a plot of normalized MTTF vs current density. In this graph, the MTTF is

adjusted to a logorithmic scale to show a more exponential relationship. Again, the MTTF is not

greatly affected until the higher densities, which in turn, yield an increase in temperature.

Figure 2.5: Current Density/MTTF Relationship

The data represented in this paper concerns different interconnect types. For my purposes, I will

focus on the Cu/low k dielectrics. Both papers show the authors’ findings for a single MOSFET.

13

In order to formulate a model that included a relationship between all three variables, the data

from both papers was combined. I first recreated each of the plots in Microsoft Excel and found

the individual exponential relationships for each. Figure 2.6 below shows the plot and resulting

equation.

Figure 2.6: Recreated Temperature/Current Density Relationship For purposes of this paper, current density will be known as J and temperature as T. The

resulting equation is thus T = 200e3.867E-08J. Several extra data points not shown in the paper were

added to create a more accurate equation. Figure 2.7 below shows the resulting plot and

equation.

y = 200.00000000000e0.00000003867x

190

210

230

250

270

290

310

1 100 10000 1000000

Tem

per

atu

re (

ºC)

Current Density (A/cm2)

Current Density vs. Temperature

Series1

Expon. (Series1)

14

Figure 2.7: Recreated Current Density/MTTF Relationship

Here, the relationship between MTTF and J is MTTF = 216.39e-1.814E-06J. Now I have two clear

relationships between the various factors affecting failure time. I still do not have an equation

however that considers all three variables. With some simple algebra, I can add the two

equations together, and the result is an MTTF equation dependant on J and T.

��� � 200 � ���.���������� � 216.39 � ���$.�$%������� & �

������� .

Although this equation expresses MTTF as a function of current density and temperature, it is

not entirely finished. When T becomes very large, the resulting MTTF is negative, which poses a

y = 216.393231925e-0.000001814x

1E-08

1E-07

1E-06

1E-05

0.0001

0.001

0.01

0.1

1

10

100

1000

100000 1000000 10000000

No

rmal

ized

MT

TF

Current Density (A/cm2)

Current Density vs Normalized MTTF

Series1

Expon. (Series1)

15

problem. To address this issue, the equation was recreated for four fixed temperatures. Because I

decided to simulate my circuits at high temperatures, the equation uses 100, 150, 200, and 250

degrees Celsius for the fixed T values. The equations are shown below:

��� � 200 � ���.���������� � 216.39 � ���$.�$%������� & 100

������� . '

��� � 200 � ���.���������� � 216.39 � ���$.�$%������� & 150

������� . )

��� � 200 � ���.���������� � 216.39 � ���$.�$%������� & 200

������� . *

��� � 200 � ���.���������� � 216.39 � ���$.�$%������� & 250

������� . +

From these four equations, I can vary current density for each of the fixed T values. Only high

current density values were used as low values of J have little effect on T, thus minimal effect on

MTTF. This will then give me new data with four different relationships between MTTF and

current density at the four chosen T values. These equations are shown below:

�,- � � 100: ��� � 308.3401���.�����$��1�

������� . 2

�,- � � 150: ��� � 260.6282���.�����$��3�

������� . 4

�,- � � 200: ��� � 215.0316���.�����$1���

������� . 5

�,- � � 250: ��� � 177.1201���.�����711��

������� . �8

16

Figure 2.8: Reworked Current Density/MTTF Relationship for Varying Temperatures I can now modify these equations a bit in order to get any of the three equations from any single

equation. To make this easier to see, below is an algebraic method of how it’s done.

For example, to get any of the other 3 equations from that at T = 100, I can use the following

model,

�308.3401 � 9�100 & �:�����$.��1���� ; <�$���=>���

������� . ��

where Ts is the temperature for the desired equation. So, if I wish to get the equation for T = 150

from the above model, my method for solving for N and M is as follows:

y = 215.0316e-0.000001906x

y = 177.1201e-0.000002996x

y = 260.6282e-0.000001385x

y = 308.3401e-0.000001089x

0

50

100

150

200

250

300

0 50000 100000 150000 200000 250000 300000 350000 400000 450000

No

rma

lize

d M

TT

F

Current Density (A/cm2)

Relationship Between Normalized MTTF and Current

Density

200

250

150

100

Expon. (200)

Expon. (250)

Expon. (150)

Expon. (100)

17

�308.3401 � 9�100 & 150�����$.��1���� ; <�$���$3���� � 260.6282���.�����$��3�

������� . �

For T = 200, my method is as follows:

�308.3401 � 9�100 & 200�����$.��1���� ; <�$���7����� � 215.0316���.�����$1���

������� . �'

And for T = 250, my method is as follows:

�308.3401 � 9�100 & 250�����$.��1���� ; <�$���73���� � 177.1201���.�����711��

������� . �)

Now I have three equations and two unknowns, and with a bit of algebra, N ≈ 0.9207 and M ≈

8.9344E-09. Using these values, I can obtain a generic equation for MTTF at any temperature.

This will allow me to now model my circuits and find some interesting relationships between

MTTF, current density, and temperature. My model is to be used in the circuit test infrastructure

and the wear-out model is very simple to update when appropriate. Like all models, there are

some drawbacks. This model is great for estimating failure time, but cannot be used for exact

measurements. The model was created to simply show a distinct relationship between failure

time, current density, and temperature with the capability of estimating failure times with known

parameters.

2.3.2 How is the Model Used

Now that I have established a useful model for obtaining the MTTF of a given circuit, I can

explain how the exactly the software uses the model. The model relies on fixed values for both

current density and temperature. As you will see in the following chapter, I have created a

monitoring program needed to handle all the data outputted from LTSpice. One of the

18

monitoring program’s duties is to track all gate, source, and drain current for each transistor in

any given circuit. Attached to each source and drain are metal lines through which the current

travels. Current density can be calculated using the following equation:

? �@

A � B

������� . �*

Where A is the total current through a particular metal line, and w * h refers to the cross

sectional area of the metal wire, w being the width of the line and h being the height. Current

density will be measured as Amps/cm^2.

Temperature is handled through Hotspot. Hotspot is an accurate and fast thermal model suitable

for use in architectural studies. Given power dissipation with displacement information, HotSpot

can calculate the steady state temperature of a region within a circuit and calculate the affect of a

particular region’s temperature on other regions.

Current density and temperature for all circuits are now taken care of. The model for MTTF can

thus be used to find an accurate failure time for a given circuit, beginning with the basic inverter

and expanding to more complex circuits.

19

Chapter 3. SYSTEM DESCRIPTION

This chapter addresses the implementation/system architecture, choice of circuits, and the

software tools, both readily available and created, to handle failure calculations. The system

requirements and overall system goals are also discussed.

3.1 General Description

My overall goal is to find the MTTF impact of EM on digital circuits. The mathematical

model used for estimating failure times was done by pulling information and data from a variety

of technical papers. The data was then recreated in MS Excel, and an equation was formed by

joining together the various data collections. The key variables in the equation are essentially

MTTF, current density, and temperature. Their definitions and relationships are explained in

chapter two. Finding relationships between all three of these variables was essential before

forming an accurate equation.

The tool chain I designed required a general model for MTTF, VLSI plots, SPICE models

and several operating conditions as inputs. The chain returns a file that shows the MTTF of

various circuit nodes for a given input. I will test both simple and complex circuits. Starting with

the very basic transistor, inverter and simple gates, and then creating more complicated high-

priority circuits. I will create a few of the important pieces to any microprocessor, including

decoders, adders and some memories.

After creating a decent size catalog of digital subcircuits to test, I designed and

implemented a program that monitors the relative usage of metal lines and transistors, pinpoints

the weakest links in the circuit, and ultimately estimates failure time. My program needs a UNIX

as well as a MS Windows environment in order to take advantage of the many tools needed for

my failure analysis.

20

After the program is up and running, the circuits are ready for testing. The circuits will be

evaluated and the program will dump the results into a spreadsheet for analysis. The spreadsheet

contains failure time calculations, current density measurements, etc. Once I have located the

weakest links in the design, I will be able to alter the design and see if it can be improved.

Assumptions:

• Perfect fabrication of circuits. Errors in fabrication will lead to quicker MTTF for

MOSFETS.

• The circuits are isolated from the outside world. Thermal transfer is valid within the

given circuit and does not assume outside heat sources except ambient temperature

• Most of the power dissipated in a circuit is from the MOSFETs and not the metal lines, so

when choosing a region, originally, a region of a floor plan was based solely on the gate

of the MOSFETs, but because of HotSpot’s minimum size limits for a region, gates (i.e.

NAND/NOR/etc) rather than individual FETs became the regions of the floor plan.

3.2 System Overview and Requirements

The project contains a mix of theory, hardware and software. As a general

implementation strategy, the system adheres to the block diagram in Figure 3.1.

21

Figure 3.1: Overall System Block Diagram of proposed system. This top-level diagram depicts the hardware/software implementation strategy of my method for evaluating

wear-out. The system consists of 4 major sections, which comprise of the circuit layout/creation, the program, various intermediate files, and HotSpot.

The proposed system consists of 4 major sections. They are circuit layout/creation, the

program, various intermediate files, and Hotspot. The following subsections contain a general

22

description, and theory, of operation for the 4 major sections. Also, the readily available design

tools used in the system, as well as those I created are briefly explained.

The basic equation for mean time to failure is 308.3401+0.9207*(100-Ts) * e^((-1.089E-

06 + 8.9344E-09*(100-Ts))*J). With that in mind the two main things that the monitoring

program has to extract from a circuit are current density and a temperature. Unfortunately these

values cannot readily be determined from looking at a schematic or layout of a circuit. Many

tools are needed to discover those quantities, some of which are readily available and others that

must be created. The tools used for this project are:

3.2.1 Design Tools Used in the System

Electric VLSI

Electric is a VLSI program that creates circuits that has the information of both the

placement of specific components such as wires and MOSFETs as well as the realistic

capacitance of a circuit. This program is important because the placement of a component can

determine the amount of heat transfer to other components as well as the capacitance added by

wires can help to create a more realistic circuit. It is open source and is a very powerful layout

utility.

LTSpice

LTSpice is a high performance Spice III simulator. LTSpice is used to simulate the

circuit and provide the appropriate voltage and current data necessary to calculate a proportional

electric field as well as the power necessary to calculate temperature.

23

LTSpice Utility

This is a utility for LTSpice that has many functions, but for the purposes of this project,

it is used to convert the raw binary data files that LTSpice outputs to an ASCII format that can be

used by the monitoring program.

HotSpot

Hotspot is an accurate and fast thermal model suitable for use in architectural studies.

Given power dissipation with displacement information, HotSpot can calculate the steady state

temperature of a region within a circuit and calculate the effect of a particular region’s

temperature on other regions.

3.2.2 Software Tools I’ve Created

Monitoring program

A program is necessary to monitor all the data output from LTSpice. The program also

needs to know the various regions within the circuit as well as where each individual MOSFET

is located. Also the program calls HotSpot and once all the data is correlated, it determines a

relative mean time to failure for Electromigration. In the later sections this will be known as “the

program.”

Simple scripts

In order to more efficiently run the necessary program, scripts were created to format

information, modify files, or test for speed. These tasks could be done by hand, but doing so

would be too tedious and would waste time.

24

The entire tool chain runs in a Linux/Unix environment, specifically Ubuntu. The main

reason for this is because the Unix environment is ideal for creating, compiling, and running C

programs and Perl scripts. One of the main reasons for use of Ubuntu is unfamiliarity with

programming in a Windows environment.Also in order to make the program easier to use for the

user, some of the capabilities of Unix programming such as the ability to call other programs and

redirect its output back to the calling program are used.

3.3 Circuit Layout and Creation

The section below describes the first major piece of my system. This section discusses

the choice of circuits used, the technology used to create them, layout preferences, and the

generation of spice netlists. I wanted to create a wide range of circuits, some being as basic as

individual gates, while adders and memories remain more complex. Although electromigration

failures are only likely to be seen in the larger more complicated circuits, the mathematical

models and software developed must cater to any size circuit. Regardless of the complexity in a

design, failure times and locations for any size circuit can then be found. Although the smaller

circuits are far less prone to the higher current densities and electromigration effects, it is still

beneficial to know the circuit’s lifetime. Also, when looking at ways to improve design and

minimize the effects of electromigration and other types of wear-out, it is the smaller circuits that

need the alterations, as they are the key pieces to subcircuits and larger digital devices.

Due to limited funding for this project, I decided to use a layout tool known as Electric.

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA)

system that can handle many forms of circuit design, including: Custom IC layout, Schematic

Capture (digital and analog), Textual Languages such as VHDL and Verilog, and much more.

This software designs MOS and bipolar integrated circuits, printed-circuit-boards (PCBs), or any

25

type of circuit you choose. It has many editing styles including layout, schematics, artwork, and

architectural specifications. A large set of tools is available, including design-rule-checkers

(DRCs), simulators, routers, layout generators, and more. Not only does Electric interface with

the most popular CAD specifications (EDIF, LEF/DEF, VHDL, etc), it provides an excellent

layout-constraint system. This enables top-down design by enforcing consistency of connections

and is an efficient and effective way to create and layout a large number of different circuits

without having to fabricate a single one. This chapter will describe not only the choice of

circuits, but the choice of layout technology.

After circuit creation and layout, I needed to find a method to generate spice netlists for

each of the circuits designed. These netlists contain a ton of valuable information that the

program needs to work properly. The netlist contains mosfet names, connections, nodes, parasitic

capacitances and resistances, and all raw current/voltage data. Luckily for me, Electric not only

has two built-in simulators (IRSIM and ALS), but can also generate decks for many other

simulators (PAL, Verilog, FastHenry, Spice, and more). I am obviously only concerned with the

spice deck. Spice decks can be written for all designs, and then any Spice simulator can be used

to handle the netlists. I chose LTSpice, a high performance Spice III simulator, to handle design

simulations and more importantly to pull the majority of information and data needed for the

program.

3.3.1 Choice of Circuit Fabrication Technology

Electric VLSI has almost any choice of design technology available. To keep me with

today’s fast paced technology along with the scaling down process of digital electronics, I

decided to design all of my circuits using 0.025um CMOS process technology using MOSIS

(Metal Oxide Semiconductor Implementation Service) design rules. Electric represents all

26

distances in dimensionless units. So, with my scale choice of 0.025um (25nm) process

technology, a transistor that is 2x3 in size is actually 50 x 75 nanometers (or 0.05 x 0.075

microns). The MOSIS CMOS technology describes a scalable CMOS process that is fabricated

by the MOSIS project of the University of Southern California.

3.3.2 Choice of Circuits

This project is designed to handle any catalog of circuits. Thus, I started with the layout

of very simple circuits, such as AND gates, XOR gates, inverters, and simple gate chains

(circuits containing a series of gates, but no more than 3 or 4).

Having discussed the basics of how circuit layout works, the catalog of fabricated circuits

can be defined. As stated above, I started off with some very simple circuits, mostly gate level

(AND, OR, XOR) and then moved on to simple gate chains, having a few logic gates tied

together. I then looked at slightly bigger but still simple circuits, such as a MUX, and a full adder

block. After creating a variety of smaller subcircuits, I was able to use these to generate larger

more complex designs. For this thesis, I looked at an 8, 16, and 32 bit RCA (Ripple Carry

Adder), a 16 bit Kogge-Stone adder, and an 8x8 register file. Below you will find descriptions of

the Kogge Stone adder and the register file.

CMOS Kogge-Stone

The Kogge-Stone adder is one of the fastest single architectures for binary addition in

parallel stages. It does however use a large amount of area and power The standard Kogge-

Stone adder design for 16-bits is shown in Figure 3,2. The basic tiling block sub-circuit of the

K-S adder is a partial prefix adder cell (PPA). My design uses two types of tiles: an even tile for

even rows (with row numbering starting at zero), and an odd tile for odd rows. Each tile

compresses two prior propagate and generate signal sets into a single propagate and gener

signal set for the column.

Figure 3.2: Block diagram for

The critical path for the Kogge-Ston

for the 16-bit adder. Because the CMOS logic blocks are all built with OPL

Logic) pre-charging transistors the timing of the entire adder is constrained to the clock.

Figure 3.3: Kogge-Stone critical path of 8 logic stages for 16 8x8 Register File

The 8x8 register file designed for this project is fairly simple, just very large.

eight 8-bit words, two read lines, and one

12 transistor SRAM cells.

27

compresses two prior propagate and generate signal sets into a single propagate and gener

Block diagram for 16-bit Kogge-Stone prefix adder network

Stone Adder is shown in Figure 3.3 consisting of 8 logic s

cause the CMOS logic blocks are all built with OPL (Output Prediction

charging transistors the timing of the entire adder is constrained to the clock.

Stone critical path of 8 logic stages for 16-bits (not all gate inputs shown)

for this project is fairly simple, just very large. It is comprised of

bit words, two read lines, and one write line. Each 8-bit word was formed from 8 single

compresses two prior propagate and generate signal sets into a single propagate and generate

Stone prefix adder network

consisting of 8 logic stages

(Output Prediction

charging transistors the timing of the entire adder is constrained to the clock.

bits (not all gate inputs shown)

It is comprised of

bit word was formed from 8 single

1

There was nothing ground breaking about the design of the register file. Two pairs of eight

MUXs are used to separate the various outputs, as it is a two-read register file, and three

decoders are used to control the data flow (2 reads, 1 write). After all the individual words were

created, all bit 0s (8 in total) were tied to an 8:1 MUX. The same is true for all bit 1s, 2s, and so

on. Eight MUXES are used for the first read line, and another 8 for the second. The first eight

share the same select lines, and the same goes for the second set. Three 3:8 decoders are used to

control the two read and one write line operations. Thus, the eights bits outputted from the

decoders are the register bits chosen to be written to or read from a given register. The circuit is

not complex, it is just incredibly large.

3.3.3 Layout Preferences

Circuits were created incorporating parasitic resistance and capacitance. This becomes an issue

when using good amounts of metal, especially when changing the interconnect sizing. Up to 6

metal layers were used in a given design, yet keeping them down to a minimum was always a

design concern. As far as metal sizing, there is really no concrete way of keeping this consistent.

Almost all metal lines have a width of 3 other than the power and ground rails, which are

sometimes slightly wider. Silicon is set to have a width of 2. The program assumes all metal

sizes to be of width 3 unless otherwise stated in the “met” file.

3.3.4 Creation of Spice Netlists

Spice decks were automatically generated for each of the laid out designs, incorporating all

layout preferences earlier mentioned. The spiceMultiply script was then used to create various

versions of a given circuit (combination of input voltage, speed, and temperature adjustments).

The netlists can then be easily simulated using LTSpice.

29

3.4 Creation of Intermediate files

The program needs extra files in order to perform an analysis of a circuit. As stated in

section 3.2, I am using a lot of tools. To get the information the other tools need, four major files

are needed. They are the floorplan file, relationship file, power trace file, and lastly, the raw

current and voltage data collected in Spice.

3.4.1 Floorplan file

One of the most important files needed for the system is the floorplan file. This file is for

HotSpot. The floorplan simply divides the circuit into small “blocks” and inside each block, its

contents (FETs, subcircuits, etc) are specified. For example, if one of my blocks was an inverter,

I would specify the contents of the block as a PMOS and NMOS transistor. The floorplan only

needs to keep track of immediate IC components, in my case transistors or subcircuits containing

large numbers of them. Metal lines will be dealt with later on.

An example floorplan for a 10mmx5mm rectangle will look as follows:

---------- | | | b1 | |----------| | | | b0 |

----------

where b1 and b2 are functional blocks. The floorplan file corresponding to this example would

be something like below:

<unit-name> <width> <height> <left-x> <bottom-y> b0 0.010 0.0025 0 0 b1 0.010 0.0025 0 0.0025

The power dissipation data, which HotSpot refers to as a power trace, would correspond to this

floor plan typically as follows:

30

b0 b1 7 2 5 1 7 2 5 1 ...

where the numbers under b0 and b1 are Watts per calling interval [24]. For the purposes of the project, a region of MOSFETs or subcircuits are grouped together into

functional blocks and the program keeps track of the power consumption of each individual. But

that information is not readily available either.

3.4.2 Relationship File

A file must also be made that relates each MOSFET or subcircuit or group of MOSFETs

or subcircuits to a predetermined region. For this, a relationship file must be created that is

specific to the program and is independent to HotSpot.

3.4.3 Manual creation of floorplans and relationship files

The circuits that are created for testing purposes are created in Electric, but it does not

have an option to create a floor plan that is compatible with HotSpot. Floorplans were created

visually in Electric; a simple Perl script was written to take the two opposite end points of a

rectangular region as input and translate that to a compatible format. The input file for the Perl

script also contained information on which subcircuits or MOSFETs are contained in each

region. The format is as show:

scale name x1, y1 x1, y2 subckt1 subckt2... mosfet1 mosfet2... n 0 1 2... p 0 1 2... name x1, y1 x1, y2 subckt1 subckt2... mosfet1 mosfet2... n 0 1 2... p 0 1 2... ...

The ‘scale’ represents the actual measurable length of each unit. For example, the distance from

(x1 = 0, y1 = 0) to (x2 = 1, y2 = 0) would be equal to the value represented by ‘scale.’ The

coordinate can be entered without regard to which two corners since a simple if statement can

31

determine the two different cases, the case where the first coordinate represents the upper left

corner and the second pair represents the lower right or if the first pair represents the lower left

corner and the second pair represents the upper right corner.

Figure 3.4: Floorplan Representation for Hotspot Being able to have the freedom to choose where the coordinates is ideal because in Electric, the

toggle measurement tool can show multiple continuous measurements as shown in figure 3.5. As

can be seen in a ring oscillator, several inverters are grouped together. The colored rectangular

boxes represent which subcircuits are grouped together.

Figure 3.5: Use of Toggle tool to create floorplan files

The parameters after the coordinates are for the relationship file. The name that Electric gives

each subcircuit and MOSFET instantiation, follows the coordinates. The ‘n’ and ‘p’ statements

32

are used as a shortcut since Electric provides a default MOSFET name of “mnmos@0” or

mpmos@0.” The numbers following the ‘n’ and the ‘p’ will generate the appropriate name.

The floor planning script will read each line and create two files: the floorplan which HotSpot

needs, and the relationship, which the program needs.

3.4.4 Power Trace File

The power trace file is created in the main program using the LTSpice data. This file is

created by the program. HotSpot needs the power trace file to run a temperature analysis for each

functional block defined in the floorplans. In order to create the power trace file, the program

needs both the relationship file and the raw current and voltage data from LTSpice. With the data

file, the program calculates the power dissipated by each MOSFET for every half period as

defined in the transient response. Once each power value is calculated and saved, the power

dissipated from MOSFET in each region is added together and outputted to a power trace file

that is compatible with HotSpot.

3.4.5 Raw current/voltage data from spice

The final file needed for the program to run is the raw current and voltage data outputted

from LTSPice. This is done by running a simulation in LTSpice given a spice file with inputs

and a transient analysis statement and exporting the data. This will produce a file with the

currents output from every voltage or current source and the currents that flow in and out of the

various terminal of each MOSFET and the voltages of every node. Ideally the inputs are to stress

the circuit as it would be stressed in real life as the program assumes that the inputs are repeated

for all time. For example, if an inverter was tested with a square wave input that switches every

33

1ns, the program will determine a mean time to failure assuming that the input stays the same for

all time. So the inputs have to be chosen intelligently in order to get an accurate MTTF

calculation. The only problem with this approach is the amount of processing time and memory

needed to produce the files. For slow computers simulations of large circuits could take a long

time and the files can be well over 100megabytes.

3.5 Software Tools/The Program

The program is written in C in a Unix environment because of my familiarity with the

programming language and also because it can execute other Unix based programs which makes

running the program for the user much simpler. The program is divided into 6 major functions:

processConfig() – this function processes the configuration file for each simulation of the

circuit. This file is crucial to the program as it provides the details of all the important paths and

files needed for the program to run and other necessary information.

create()- this function reads the pspice file and catalogs all MOSFET and connections.

assignRegions()– once each MOSFET is cataloged the relationship file is read and assigns the

regions to each individual MOSFET.

monitor()- this function monitors the voltage at the gate of each mosfet and then current in

each connection.

printPower()- this function creates the power trace file.

34

getTemperature()- this function calls HotSpot and reads its output(temperature) and assigns

the appropriate temperature to the appropriate MOSFET.

changeMetal() - this function reads in a file and changes the line widths between transistors to

the widths specified in the file. The metal heights are assumed to be the same throughout the

circuit.

dMTTF()- given an average gate voltage and a steady state temperature, a mean time to failure is

calculated.

When the program runs its course it will output an excel file with the name of each MOSFET as

named by LTSpice, a mean time to failure, a temperature in Kelvin, an average electric field, a

gate width, the total power dissipated by the MOSFET, and for the whole transient analysis.

3.5.1 Extracting Runtime Information

The program needs multiple pieces of information to run and the configuration file that it reads

in provides that information. The information includes the location of the HotSpot program, the

name of the circuit file to test, the name of the relationship, floorplan, raw data, and the metal

width file. The other information it extracts is used to modify the MTTF equation: A*

308.3401+0.9207*(100-Ts) * e^(B* (-1.089E-06 + 8.9344E-09*(100-Ts))*J) + C. Three

constants can be set that represent the constant in front of the equation, the multiplier inside the

exponential term and an offset. The rest of the data is information used to produce the excel

spreadsheet that has the MTTF data.

35

3.5.2 Creating a catalog

In order to catalog each MOSFET, the program needs to read the PSpice file. It goes

through the file line by line looking at the first word of each line. Resistors and capacitors are

ignored but subcircuit definition, MOSFET and subcircuit declarations, and the .TRAN

statement are each treated in a special way.

When the program reads in a MOSFET, it creates a MOSFET object recording its name

and whether it is a PMOS or NMOS FET. Three connection objects are created representing the

metal line between the gate, drain, or source to a node. The objects are “attached” to the

MOSFET terminals. Next the nodes that the gate, drain, and source are connected to are checked

to see whether or not those nodes are already created by previously MOSFETs. If the node or

nodes exists then the connections object are connected to the appropriate nodes. If the node does

not exist, the node is created and named as declared in the PSpice file. So with each line with a

MOSFET declaration, a MOSFET is created and is connected to three nodes.

When the program reads a subcircuit definition, the program behaves as if it is creating a

separate circuit. It first creates the appropriate number of interface nodes or outer nodes and then

as it reads a MOSFET line it creates the MOSFETs and the nodes if necessary. The names of

each MOSFET and node reflect that it is part of a subcircuit. The resulting circuit is saved into a

catalog.

If a subcircuit declaration is encountered, all the MOSFETs and nodes are copied and if a

declaration was encountered inside a subcircuit then the MOSFETs and nodes are renamed to

reflect the fact that they are inside a subcircuit and connected with the rest of the main circuit.

36

Luckily, Electric creates a spice file with the inner most subcircuits appearing closer to the top of

the file before the subcircuit that contain further subcircuits appear.

When the program encounters the .TRAN statement, the first argument is saved and is

interpreted as half the period of the fastest input. This is because the monitor() function will

record several power readings and each individual power reading will be the power over that

interval. The second argument is saved as the entire length of the transient analysis. Ultimately

all the nodes and MOSFETs are saved into a circuit object which makes accessing each

individual circuit element easier.

The main job of the create() function is to record the names of each node and MOSFET

as LTSpice knows it as because the LTSpice output file contains the specific names and if the

names aren’t recorded exactly, then the various currents and voltages cannot be monitored.

3.5.3 Assigning MOSFETs to regions

Once the MOSFETs are named appropriately, they must be assigned to a region. In order to do

this the relationship file is read in. The format for this file is:

REGION mosfetName mosfetName ... subcircuitName sub circuitName ...

In order to assign the regions, the words after the ‘REGION’ are compared with the name of

each MOSFET in the circuit object. If a match is found the ‘REGION’ is saved into the

MOSFET. If there is an error in the relationship file, for example if a MOSFET is not assigned a

region, the program stops execution. A list of the regions is also saved into the circuit object in

order to quickly access the information for creating the power trace file.

37

Because of the complexities of the metal lines that connect each MOSFET, the metal lines that

connect the MOSFET to each node are assumed to be inside the region of the MOSFET even

though they may not be in Electric.

3.5.3 Monitoring of circuit usage

After everything has been cataloged, monitoring can be done via processing the LTSpice data

file. The top line of the data file contains the traces so the first line is processed element by

element; for example, an element may be Id(MOSFET) or V(node) and the information in the

same column represents the value at a certain time. The point in time is the first element

displayed on each line. If the name inside the parenthesis matches the name of one of the

MOSFETs or nodes, then its position or index is saved in the node or connection object. This is

done to quickly access information within the file. The indices that are saved are nodes

connected to the gate, drain, and source, and the Id, Ig, and Is parameters which represent the

drain, gate, and source current from the MOSFET. If a node or connection is not defined by an

index number, the value is assumed to be zero for all time.

After the indices are saved the file is processed line by line. Power, voltage, and current averages

are calculated using a left Riemann Sum. This is done because the information provided by the

data file is expressed like in figure 3.6. At a certain specific point in time the voltage or current

can be a certain value. Because it would be too difficult to get the remaining points and

interpolate the data in an equation so the left Riemann Sum is a lot simpler to program. Great

error is avoided however because each time step is not set, LTSpice makes the time steps as

small or as big as necessary with large steps having data that is mostly constant. The average

38

calculated in the program has been compared to the average calculated by LTSpice and the value

is equivalent.

Figure 3.6: Data as it appears in the file

Figure 3.7: The left Riemann sum of the data So order to calculate the average power in an interval the program goes through each MOSFET

and gets the voltage at the drain, source, and gate as well as the currents into and out of the

MOSFET and calculates the instantaneous power and multiplies that by the difference between

the current time and the time at the next iteration. Once the time goes past an iteration of half of

the period of the fastest input, the average power is saved into the MOSFET object. So if the

39

fastest signal switches every 1ns and the transient analysis is 10ns long, each MOSFET object

will have 10 power values each representing the average power in each interval.

The average gate voltage and the average current of each connection is calculated the exact same

way except that the value is calculated as an average for the entire transient analysis instead of

for each half period. Once the end of the data file is reached, monitoring is complete and the

function returns to main.

3.5.4 Creation of the Power Trace File

When the power has been calculated, the power trace file can be created. The program goes

through the list of regions saved in the circuit object and again the program uses a linear search

to find out which MOSFETs are in the region being searched for. The average power for the

interval for every MOSFET “in” the region are added together and ultimately outputted to the

power trace file. This procedure is done for every region and every interval, one hundred times in

order to give HotSpot the data necessary to determine a steady state temperature.

3.5.5 Calling HotSpot

Once the power trace file is created, the program executes HotSpot and provides the appropriate

arguments that would allow the temperature in each region to be calculated. The output of

HotSpot is redirected to the program and the data is parsed and the temperature is saved to each

individual MOSFET in a particular region.

3.5.6 Changing Metal Widths

For cases when metal lines need to be adjusted from their default widths, the program reads in a

file and adjusts the appropriate lines. Because of the limitations of the program and the lack of

geographical and dimensional information from the layout tool, the connection between the

40

various terminals of the MOSFET are assumed to be straight lines that do not turn and have the

same dimensions even though they may not.

3.5.6 Calculating MTTF

After all the important information has been calculated and saved, a mean time to failure for each

MOSFET can be calculated. The equation created from the work mentioned in section 2.5 is

used with the inputs being temperature and voltage values. As mentioned in 3.5, the program

outputs a spreadsheet file with additional information, which is done in the MTTF() function.

The total power for each MOSFET for the entire transient analysis is also calculated.

3.6 Addition Tools

C’s primary function is not to be a text processor, for that Perl scripts were written to set up the

test environment and also to calculate extra pieces of information that could be important when

trying to find a correlation between anything else and mean time to failure.

3.6.1 Setting up Multiple Tests One script was written to create spice files, configuration files, and shell scripts that would test a

circuit under various conditions. More specifically, the spiceMultiply script takes in a single

Pspice file, a configuration for the program, and a parameters list, and creates multiple copies of

the spice file under different conditions and shell scripts to simulate the circuit and calculate its

MTTF.

The parameters list allows the user to vary the conditions under which the circuit is simulated;

the input speed, the temperature at which the circuit is run and the rail voltage can be changed.

Also multiple constants can be entered which will modify the MTTF equations. The script will

produce a circuit file for every combination of speed, temperature, and VDD. It will also create a

41

shell script to run the appropriate pre and post scripts and simulate each version of the circuit and

calculates its MTTF. As each of the individual files are created, a larger shell script file is created

that will invoke each of the individual shell scripts effectively running the entire simulation and

take the lowest MTTF for EM and write its information to an excel file.

3.6.2 Changing the Temperature HotSpot can calculate temperature at a different started temperature as the temperature at which

the PSpice file is simulated under. In order to avoid this and ultimately producing erroneous

results, a script was created to consolidate, the two files. The script reads the argument of the

.TEMP parameter in the PSpice file and alters the initial temperature in configuration file of

HotSpot.

3.6.3 Converting the LTSpice Utility data file

The format of the raw data file that the program can process is different than that which LTSpice

and the LTSpice Utility produces. In order to make the file compatible a script was written to

convert those files to a compatible format.

3.6.4 Calculating Average Power for each Region

The other important information that could be used is the average power of each region. This is

done by simply adding up all the values for each region in the power trace file and dividing by

the number of iterations. The average power is appended to the end of the spreadsheet created by

the program.

42

3.6.5 The Speed Tester

One script was written to test the delay for a circuit given the data file and the rail voltage. This

can be done manually by looking at the when a signal reaches 10% or 90% of its maximum

depending on if the signal should be high or low. This is too tedious and not efficient especially

if, a circuit has multiple outputs and the transient analysis is very long compared to the period of

the fastest input. For example, trying to find the delay for every possible output of a 4 bit ripple-

carry adder would require looking at 5 different signals 512 times.

Figure 3.8: Showing method for manually finding delay The alternative is to use the data file again to determine delay. So a script was written. The script

needs three pieces of information, the nodes to monitor, the rail voltage, and the value of half the

period of the fastest input. As was done with the monitoring section of the program, given the

nodes to watch, an index can be assigned to the location of the particular node. With the rail

43

voltage the script can calculate the 10/90% values. And finally the half period value is needed to

tell the script when to start timing the delay.

Assuming a circuit is working properly, or it is not driven faster than it can function, the script

can determine if that particular iteration of the output should be a high or a low. This is done by

checking the value of the node right before the start of the next iteration. That is if an inverter has

an input signal that switches every 1ns, in order to tell if the output should be high or low, the

script checks the value of the output node at 0.999ns since the output will not switch before the

input is changed.

Once that information if acquired the next thing to do is measure the delay. Because LTSpice

does not usually have a value at exactly the 10/90% point, the script gets the two points around

the 10/90% point and calculates the equation for the line connecting those two points as a

function of voltage. Once that is done the script plugs in either the 10% or 90% value to get a

delay estimate. As seen in figure 3.9, this can create some error because the signal will not be

linear, but this is as accurate as measuring the delay by hand because as seen in figure 3.10,

LTSpice has line segments connecting the points.

44

Figure 3.9: Error possibility in Delay calculations Another potential problem is glitches. This is accounted for by keeping track of which nodes

cross the 10/90% value twice in one interval. With that information the first crossing can be

ignored and the data from the second crossing can be used to calculate delay.

The script calculates the delay for each iteration for every node and keeps track of the largest

delay and appends that value to the end of the spreadsheet created by the program.

3.6.6 Gathering the Results

If a spice file is created for every combination of three temperatures, three input speeds, and

three rail voltages, 27 different analyses would be done by the entire tool chain. In order to

combine all of the results, a script was written. The script goes through every excel spreadsheet

that was created, locates the one with the lowest MTTF and copies its information to a larger

excel spreadsheet. The final result is a spread sheet organized by the different constants,

temperature, rail voltage, and input speed having the data of all 27 analyses.

45

A sensitivity analysis was done as well. But this was done through an excel spreadsheet. The

equations from the models were simply put into the spreadsheet and the effects of the current

density or temperature were amplified. That data will prove useful when analyzing a circuit

where the effects of temperature are too great to counteract any sizeable reduction in current

density. The data added to the spread sheet was the MTTF when the circuit does not add any heat

to the ambient temperature, the MTTF when current density is at a value that maximizes the life

of the circuit, and the MTTF for when the effect of the temperature is increased.

46

Chapter 4. Circuit Evaluation

This chapter deals with the actual model usage for determining the failure times of

various circuits. I have created a catalog of circuits to test, some very simple and others quite

complex. I will now evaluate the circuits and discover just how and when they fail. I have a

method for monitoring temperature and current density and now the equation can do the rest,

verifying that the model created is in fact accurate. All circuits described in Chapter 3 were

simulated at a variety of temperatures. High temperatures were used as the ICs used in industry

operate at such conditions [28]. Hotspot is keeping record of temperature for the various designs,

and if discrepancies are found between HotSpot and the temperatures specified in the spice files,

designs were adjusted and simulations were once again performed.

4.1 Testing the Circuits

The circuits were tested under various conditions. By default, metal lines have a thickness of 3

units, or 75nm. Three different variables were changed, the rail voltage, and consequently the

input voltage, the starting ambient temperature of the circuit, and the switching frequency of the

inputs. The rail voltages chosen were 1v, 1.25v and 1.5v. The starting ambient temperatures

chosen were 100 degrees Celsius (373 Kelvin), 150 degrees Celsius, and 200 degrees Celsius.

The input frequencies chosen to simulate a circuit are 400MHz, 100MHz, and 25MHz.

Originally 25MHz, 50MHz, 100MHz, 200MHz, and 400MHz were chosen, but having 5

different values for switching frequency would have increased simulation time by over 50%. For

most cases, such as with the gate and the smaller circuits, the inputs were selected so as to get

every possible input output pair effectively testing out an entire circuit, but for larger circuits, a

certain input was chosen to test a certain part of a circuit.

47

All the data for each of the cases were collaborated and the date for the “weakest link” or the

MOSFET that had the lowest MTTF was collected and placed into a single spread sheet. Using

this spreadsheet, a variety of graphs was created.

The circuits were tested in an environment where connections between terminals of a

MOSFET are wires which have both parasitic capacitance and resistance. This adds to the delay

of a circuit as well as acts as a load that each gate or subcircuit must drive. More power is

consumed and temperatures become higher, yielding a lower MTTF. Simulating with parasitics

in mind is important, as any changes to increase overall lifetime may change parasitics in ways

that increase power and disperse more heat. For example, reducing interconnect sizing can

increase MTTF but also increases parasitic resistance causing an increase in power consumption

and temperature.

4.2 Verifying the Models

To verify the model created, a ramp test was performed on a single inverter similar to that

done is various papers. The input of the inverter was changed from 1V to 1.5V in increments of

0.25V at three different temperatures, 373, 423, and 473 Kelvin. The program was run and the

MTTF data points were compared to the original paper’s data. The results from the constructed

tool chain pretty closely match the data found in papers [25] and [26]. The papers looked at a

single FET, so there are subtle differences. There is a slight bit of error, but this comes as a result

of manually recreating the paper’s data in excel. Also, the equation must be more generalized to

handle all current densities and temperatures. For purposes of this paper, all graphs showing

MTTF relationships were normalized to the lowest value, and show the percent difference

between that value and all other values in the set.

48

Figure 4.1: MTTF Improvement vs. Current Density Plot Using Created Model

4.3 The Inverter

The inverter is the most basic gate in a digital system. Using the findings for an inverter, I

can get a general idea of wear-out behavior for larger circuits and use the tool chain to estimate

failures. Also improvements can be made to larger circuits in order to increase lifetime with

minimal to no decrease in performance. In order to study the relationship of various factors

against mean time to failure, inverters were simulated at 3 different starting ambient

temperatures and 3 different rail voltages. Widths of metals at source and drain locations ranged

from 6 units to 27 units (150 nm to 675 nm). The input to the inverter was a square wave of

varying frequency with a 50% duty cycle.

0

5

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50

55

0 5000 10000 15000 20000 25000

MT

TF

Im

pro

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Current Density (A/cm2)

MTTF Improvement vs Current Density for

Various Temperatures

Vdd = 1V Temp = 373K

Vdd = 1V Temp = 423K

Vdd = 1V Temp = 473K

1

4.3.1 The effects of Input and Rail Voltage

With an increase in input/rail voltage comes an increase in current. Because this means more

current through the same size interconnect, a higher current density is expected. Thus, with input

voltage being proportional to current density, an increase input voltage yields a reduced MTTF.

This was seen in section 4.2. However, because current densities for the inverter are so small

(<106), the increased current densities as a result of increased input voltage yield only a very

small change in MTTF. When the rail voltage is increased however, the delay decreases, giving a

performance increase. The data in figures 4.2 and 4.3 show the effects of increasing the rail

voltage.

Figure 4.2: Effects of Increased Rail Voltage on MTTF

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

0 50 100 150 200 250 300 350 400 450

MT

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(%)

Input Frequency (MHz)

MTTF Improvement for Changing Rail VoltageTemp = 100°C

Vdd = 1V

Vdd = 1.25V

Vdd = 1.5V

50

Figure 4.3: Effects of Increased Rail Voltage on Current Density

As you can see from figure 4.4, MTTF does in fact change with a change in input voltage, but

the changes are minimal. It is safe to assume then that at lower current densities (found in the

small circuits/basic gates), ambient temperature of the device has a much greater effect on

MTTF. I can also see from the above figure that as current densities become greater, they have a

larger effect on MTTF of the device.

4.3.2 The effects of Temperature

Temperature is the second biggest factor affecting MTTF other than current density. For very

small circuits, temperature outweighs the effects of current density. However, this paper focuses

on larger circuits. With temperature also comes an increase in current density, but the increase in

not nearly as much as that with an increased input voltage. However, because I am running these

10000

11000

12000

13000

14000

15000

16000

17000

18000

1 1.1 1.2 1.3 1.4 1.5

Cu

rre

nt

De

nsi

ty (

A/c

m2)

Rail Voltage (V)

Average Current Density for Changing Rail Voltage

Average

Current

Density

51

circuits at high temperatures by default, any slight increase in ambient temperature of the device

is sure to decrease its lifetime.

Figure 4.4: Effects of Temperature on MTTF for Inverter

As can be seen in figure 4.4, the relationship between current density and MTTF for the inverter

is fairly linear. This is probably due to the lower current densities associated with the small

inverter. However, the change in MTTF with change in temperature is quite large. I only ran my

circuits to 473K (200 Degrees Celsius), however, it can be easily seen that at extremely high

temperatures, the circuits will indeed fail very quickly. As the circuit is dissipating more heat, it

in turn will use more power and its lifetime decreases. The amount of power the inverter

dissipates greatly affects the lifetime of the inverter. This is because the power used by the

inverter creates heat, heat that HotSpot calculates based on power data. Obviously a smaller

circuit that uses a certain amount of power will become hotter than a larger circuit that uses the

same amount of power. As can be seen in figure 4.5, the power usage is directly proportional to

0.00

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50.00

60.00

70.00

0 10000 20000 30000 40000 50000 60000 70000

MT

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(%)

Current Density (A/cm2)

MTTF Improvement for Varying Temperatures

Temp = 373K

Temp = 423K

Temp = 473K

52

the MTTF of a circuit regardless of the size and configuration of the inverter. The data shown is

the MTTF plots for five different inverters. Each point represents the power usage of the inverter

using a different metal interconnect size for source and drain metals.

Figure 4.5: Power vs. MTTF plot for Inverter The amount of power a CMOS circuit consumes is proportional to the frequency times the load it

is driving times the square of the rail voltage as seen in equation 4.1. The above tests (other than

the input voltage section) assume a constant input of 1V with a variation in interconnect width

for source and drain metal lines. Clearly, the more power the inverter consumes, the faster it will

fail. On the larger circuits to be discussed in later chapters, changing interconnect size will have

strong affect on the MTTF, because again I will be dealing with much larger, higher current

density devices, all that consume more power.

������� ). �

0.00

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Power (nW)

MTTF Improvement vs Power(compared to width = 75 nm)

Width = 6 units

Width = 9 units

Width = 12 units

Width = 18 units

Width = 27 units

53

4.3.3 The effects of Input Frequency

Many high speed electronics consume large amounts of power. With CMOS technology, most of

the power consumption is due to the MOSFETS transitioning through the linear region to either

saturation or off. Because I am talking about an inverter, no matter whether the input is a logic 1

or 0, either the PMOS or NMOS will be off. No current flows into the gate terminal, and there is

no dc current path from Vdd to GND, yielding a steady-state current of zero. This means zero

static power. Sometimes I will get little amounts of static power due to reverse-bias leakage

between diffused regions and the substrate, but for my purposes, I will ignore static power. The

majority of power consumed is dynamic and is caused by switching logic states. Dynamic supply

current is dominant in CMOS circuits because most of the power is consumed in moving charges

in the parasitic capacitor in the CMOS gates. As mentioned in section 4.3.2 power contributes to

the thermal effects that can lower the MTTF. Figure 4.6 shows the power consumption of the

inverter for input frequencies of 25MHz to 800MHz.

Figure 4.6: Effects of Input Frequency on Power for Inverter

0

500

1000

1500

2000

2500

0 100 200 300 400 500 600 700 800 900

Po

we

r (n

W)

Input Frequency (MHz)

Effect of Input Frequency on Power

Width = 6 units

Width = 9 units

Width = 12 units

Width = 18 units

Width = 27 units

54

So the faster the input frequency, the more average power the inverter consumes, which yields a

higher temperature and thus a lower MTTF. Figure 4.7 shows the relationship between input

frequency and MTTF for different interconnect sizes. As expected, the inverter with the largest

interconnect size dissipated the most power, which in turn increases temperature. This leads to a

lower MTTF. However, the increase in interconnect size reduces current density, which should

increase my MTTF. Again, because I am dealing with smaller circuits with lower current

densities, the power consumption and temperature increase greatly outweigh the reduction in

current density. At very low input frequencies the MTTF is less affected by switching frequency,

and more by changes in temperature and current density. Yet, at much higher frequencies, the

switching frequencies tend to take over the increased temperature and current density reductions.

Figure 4.7: MTTF vs. Input Speed for Various Interconnect Sizing

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

-50 50 150 250 350 450 550 650 750 850

MT

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(%)

Input Frequency (MHz)

MTTF Improvement vs Input Frequency

Width = 6 units

Width = 9 units

Width = 12 units

Width = 18 units

Width = 27 units

55

4.4 Complex Circuits

4.4.1 Adders

For this section, I tested two different adder types, Ripple Carry and Kogge-Stone. The

adders were much more complicated and required a somewhat different test method. There are

naturally such a large number of input/output combination pairs for each of the adders, thus

testing them all would be cumbersome. Thus, inputs were carefully chosen in order to stress the

various areas of the circuits equally. The ripple carry adder is one of the simplest adder types,

and seeing as how all gate voltages were close to their nominal values, analyzing the data was

straightforward. However, the Kogge-Stone adder is much more complex and there are several

areas of the circuit that are relatively inactive compared to other. Current was sometimes highly

concentrated in these spots and led to the failure of the device.

4.4.2 Ripple-Carry Adders

Three Ripple Carry Adders (RCAs) were designed for this section. They were 8, 16, and 32

bits in size. All three adders were constructed using the full adder block discussed in Appendix

B. To effectively test the set of adders, the inputs were chosen so that the A and Carry-in

signals were switching twice as fast as the B signals. This input method was able to equally

stress all of the MOSFETs so that there was no inactivity throughout the circuit. The average

current density found at the failure locations of the circuit match the behavior of circuits

analyzed before; the faster the input speed, the higher the average current density, and the lower

the MTTF.

As mentioned in prior sections, self heating is often a factor in the determining the failure

time for the larger circuits. For the RCAs, they are all large enough allowing HotSpot to

56

correctly calculate temperatures of a given block. The smallest subcircuit used for the RCA was

the full adder. Using the input combination described above, all MOSFETs have close to the

optimal average gate voltage and are stressed pretty much the same amount as one another. This

makes it much harder to analyze, as one can’t just say that a certain FET is on far more than

others thus it fails first. Temperature then becomes a large factor in determining the adder’s

MTTF. The temperature of a particular region may not necessarily be the ambient temperature

specified in the spice netlist. Naturally, the faster the circuit is run, the higher the temperature.

Also, temperature increases can be seen with increasing adder size (in terms of total bits). Speed

is also a huge issue primarily when it is too fast for the circuit to handle. At high input

frequencies, the rise and fall times of a signal are often too quick and do not allow the voltage

enough time to stabilize. As a result, pieces of the circuit remain inactive and cause the circuit to

fail. There are also times where both NMOS and PMOS FETs will be try to turn on at the same

time due to the instability of the gate voltages, which increases power consumption and

ultimately temperature.

To make analyzing the RCAs more thorough and realistic, the frequency of the inputs was

limited to 25MHz, the highest frequency at which the output stabilizes before the next clock

cycle. Any faster and inactivity skews the results. Figure 4.8 shows the MTTF against the

different size RCA adders. For the 8 and 16 bit adders, the MTTF is virtually the same, as self

heating is not yet evident. The very slight differences between the MTTFs of the two adder types

are a result of increased current density in the 16 bit. However, the 32-Bit adder has a

significantly lower MTTF because of the self heating affects. The is a very small temperature

increase (< 1 degree Kelvin) in the 8 and 16 bit RCAs, but the temperature of the 32-Bit RCA

57

raised over 5 degrees Kelvin. The self heating effects are even more apparent with increased rail

voltage.

Figure 4.8: Comparison of 8-Bit, 16-Bit, and 32-Bit Adders

4.4.3 Kogge-Stone Adders

The Kogge-Stone adder is one of the more complex adders used today. Its operation and

functionality is discussed in Chapter 3. I analyzed a 16-bit Kogge-Stone adder for this portion of

the project using a similar test method as demonstrated with the RCAs. However, because of the

added complexity in design, the input combination used for testing did not ensure that all FETs

were stressed equally. Several areas of the circuit showed significantly more activity than others.

This drastically reduced the MTTF of the entire circuit, making some failure times lower than

their ideal value.

-10

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Size of RCA (bits)

MTTF Improvement for Various Size RCAs

Vdd = 1V

Vdd = 1.25V

Vdd = 1.5V

Before getting into the analysis of the circuit, it is important to address a few points.

the lifetime of the circuit all of the elements would have 50% activity

trends for other circuits would apply to this KS adder;

first due to the delay contribution of all previous stages. The

Figure 4.9 tells me that the last XOR

specifically to focus on the last stage: each of XOR

Figure 4.9

Unlike any of the other circuits previously analyzed, the Kogge

higher current densities at the failure locations due to the constant activity of certa

especially when run at higher frequencies

temperature and makes self heating

higher current density and temperature, thus the MTTF decreases tremendously.

purposes, each subcircuit of the adder will be analyzed individually, and then the entire circuit

will be looked at as a whole.

The Kogge-Stone consumed a

to 11 Kelvin depending on the rail voltage. If you look at Figure

starting ambient temperature, rail voltage, and

improvement while the x-axis is the average power consumed by

values are obtained from simulating the circuit with different switching frequencies.

earlier, twenty-seven (27) differe

58

Before getting into the analysis of the circuit, it is important to address a few points.

the lifetime of the circuit all of the elements would have 50% activity (ideally) and that the same

trends for other circuits would apply to this KS adder; one of the last stages will ultimately fail

first due to the delay contribution of all previous stages. The critical path of the adder shown in

XOR-gate will be the most likely to fail. Code was written

specifically to focus on the last stage: each of XOR-gates for each of the sums.

Figure 4.9: Critical Path of the KS Adder

Unlike any of the other circuits previously analyzed, the Kogge-Stone adder shows much

higher current densities at the failure locations due to the constant activity of certa

higher frequencies. The increased current density causes an increase in

temperature and makes self heating much more apparent. Power consumption is greater with the

higher current density and temperature, thus the MTTF decreases tremendously.

purposes, each subcircuit of the adder will be analyzed individually, and then the entire circuit

consumed a great deal of power, which increased internal temperature up

11 Kelvin depending on the rail voltage. If you look at Figure 4.10 you will see the affects of

starting ambient temperature, rail voltage, and input speed. The y-axis is the MTTF

axis is the average power consumed by the circuit. The different power

values are obtained from simulating the circuit with different switching frequencies.

seven (27) different tests were run. In the graph, nine (9) lines are plotted and

Before getting into the analysis of the circuit, it is important to address a few points. First, for

and that the same

one of the last stages will ultimately fail

critical path of the adder shown in

gate will be the most likely to fail. Code was written

ne adder shows much

higher current densities at the failure locations due to the constant activity of certain component,

. The increased current density causes an increase in

. Power consumption is greater with the

higher current density and temperature, thus the MTTF decreases tremendously. For my

purposes, each subcircuit of the adder will be analyzed individually, and then the entire circuit

great deal of power, which increased internal temperature up

you will see the affects of

axis is the MTTF

The different power

values are obtained from simulating the circuit with different switching frequencies. As stated

nt tests were run. In the graph, nine (9) lines are plotted and

59

each line contains three points. Each line represents the lifetime improvement of the circuit at

three different input frequencies. Temperature and voltage for each line is held constant as can be

seen from the graph below. As the rail voltage is increased the MTTF further decreases with

increased current density. The higher the rail voltage, the more power the circuit is able to

consume which is shown by the last point in each line being plotted further to the right. As with

all the other circuits, the higher the input frequency, the lower the MTTF, as input frequency

increases temperature and associated current density. In Chapter 5, current density and

temperature will be analyzed separately using this data.

Figure 4.10: Effects of Starting Ambient Temperature, Rail Voltage and Input speed for Kogge Stone Adder 4.4.4 8x8 Register File

The register file was the largest of the circuits implemented for this project. Although the

design is fairly simple, the analysis is not so easy. Rather than focus on an input scheme that

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Vdd = 1 Temp = 100

Vdd = 1.25 Temp = 100

Vdd = 1.5 Temp = 100

Vdd = 1 Temp = 150

Vdd = 1.25 Temp = 150

Vdd = 1.5 Temp = 150

Vdd = 1 Temp = 200

Vdd = 1.25 Temp = 200

Vdd = 1.5 Temp = 200

60

equally stressed each piece of the circuit (becomes a lot harder to do as the circuits get bigger), I

decided to go with a more basic input scheme that is geared more towards the functionality of the

device. Because it was impossible to test all input combinations, some of the data is slightly

skewed, however this does not deem it as useless. In fact, the data collected for this register file

is very useful, as it allows me to verify my results found for the smaller circuits, as they are the

building blocks for any current semiconductor device. The circuit elements that have very low

MTTF due to inactivity will be ignored for the analysis and my focus will be on the areas of the

circuit that better allow me to verify previously seen trends, as well as discover new ones.

Due to the excessively large size of the register file, there was temperature variation throughout

the device. Some areas will be much hotter than others, and in turn most likely to fail first. Data

shows that the hottest areas of the register file were the SRAM cells, the inverters around these

cells, the decoders, and the MUXs respectively. The individual bit cells cannot really be

redesigned as they hold static data, however, the design of the 3:8 decoders and 8:1 MUXs can

be re-evaluated to improve the circuit’s overall failure time.

Although the bit cells are essentially “holding” the data, it is the MUXs and the decoders

that are really doing the most work. They not only have to specify correct address lines, but are

responsible for all output data. Current density in these regions is very high, and this along with

the increased internal temperatures, causes these regions to fail. Also, the majority of the metal

lines are distributed throughout these areas. My analysis will focus on the 8:1 MUXs and the 3:8

decoders found throughout the register file. The weakest MUX is found at the end of the circuit,

near the output. The MUX used for the register file was created by feeding two 4 to 1 MUXs into

a 2 to 1 MUX. For the analysis, the output pMOSFETs for the MUX subcircuits will be looked

at. The decoders used for the register file were designed using a combination of AND gates and

61

inverters. The failure locations for the decoders are the inverters at the output of the AND gates;

given the ideal input, the output of an AND gate is low 75% of the time. One can conclude that

the PMOS of the output inverter is the weak link.

The register file is a fairly simple design and is entirely made up of various subcircuits.

The complexity only comes into play when the many subcircuits are tied together and operate as

a function of one another. By analyzing the subcircuits that make up the register file, the reasons

for the circuit’s failure become clearer. Again, this is the largest of the circuits analyzed for this

project. All factors affecting MTTF must be considered. There is a temperature gradient across

the entire circuit, where self heating is more apparent than in any other circuit I have analyzed.

Although a portion of the circuit may tend to operate at a rather cool temperature, there is often

an element close by that does not. The high temperature of the associated area contributes to the

heat found in other locations. It is the hotter areas in the circuit that I care about, as they consume

large amounts of power and ultimately lead to a low MTTF. On the contrary, the cooler circuit

elements help keep the overall temperature of the device down by distributing the heat,

increasing the MTTF.

4.5 Failures, Associated Performance Flaws and Potential Fixes

Electromigration is an issue for two main reasons: high temperature and high current density,

or in my case, high average current density. Sometimes, the effects on MTTF due to one factor

may outweigh the effects seen by the other. Yet, almost all of the time, these two factors go hand

in hand, as a higher current density usually means a higher temperature. The increased

temperature means more power consumption, bringing down the MTTF for the entire circuit.

62

4.5.1 Input Frequency

Input frequency is defined as the switching frequency of the fastest input for a given

circuit. This greatly affects the MTTF of a device. Often times, the input is too fast and does not

give the voltage enough time to stabilize and reach its full potential. The average gate or “turn-

on” voltage for a FET is always half the rail voltage. If the input frequency fails to allow the

voltages to reach their ideal values, the circuit will not behave properly. As the circuit goes

through its critical path, the later stages may not even function and the device is useless. Or the

device may somewhat function but will fail quicker than it should.

4.5.2 Skin Effect

The skin effect is the tendency of an alternating electric current (AC) to distribute itself

within a conductor so that the current density near the surface of the conductor is greater than

that at its core. That is, the electric current tends to flow at the "skin" of the conductor. The skin

effect causes the effective resistance of the conductor to increase with the frequency of the

current [28]. At higher frequencies, current density greatly increases which causes the MTTF of

a device to decrease. As mentioned in previous sections, high current densities have many

undesirable consequences. Most metal lines have a positive, finite resistance, causing them to

dissipate power in the form of heat. I already know that temperature greatly effects the lifetime

of a circuit. At higher temperatures, the metal lines can melt or burn-up. Thus, keeping the

current density sufficiently low is very important as it minimizes the amount the material

forming the interconnect moves, which is electromigration. In today’s technology,

semiconductor devices are constantly being reduced in size, and although they demand less

current, there is trend toward higher current densities to achieve higher device numbers in ever

smaller chip areas. Moore’s Law has continued to show this for several years.

63

4.5.3 Ideal Current Density

In a perfect world, semiconductor devices would be designed to achieve zero current density.

All elements of a device would function just as they should, turning on only when they need to,

and turning off when not in use. Current would be held to an absolute minimum throughout the

entire device. With this, the metal lines associated with each FET would also be optimized. Area

would not be a concern and cross sectional area for interconnect material would have no sizing

limits. However, this is impossible for any designer to achieve and thus it is important to simply

focus on minimizing current density. This also becomes harder to do as the complexity of the

circuit increases. To see just how much this affects failure time, I can look at the Kogge Stone

adder. Figure 4.11 shows the MTTF improvement versus the input frequency of the circuit if the

average current density of the interconnect material were at its optimal value of zero as

compared to simulated data. The data assumed a starting ambient temperature of 373 K. All

three rail voltages were plotted to better show these trends. For the simulated case, high current

densities tremendously affect circuit performance and bring down the MTTF by several years.

With the high current density comes an increase in temperature, and the affects of self heating

become more obvious. However, in the ideal case where current density is zero, the only limiting

factor on MTTF is temperature. Temperature is naturally lower with smaller current densities,

and self heating is less apparent. With the ideal case, MTTF is almost the same for all 3 rail

voltages. However, using the simulated data, the rail voltages naturally increase current and in

turn current density, so MTTF changes significantly.

64

Figure 4.11: Input Frequnecy vs. MTTF when Temperature = 373K

As ambient temperature is increased, self heating becomes more of an issue. However, the

effects of self heating are still not enough to outweigh the effects of high current densities.

Figure 4.12 below is a similar graph to the one above, but assumes a starting ambient

temperature of 423K.

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MTTF Improvement Compared to Simulated DataTemp = 373K

Vdd = 1V (ideal

current density)

Vdd = 1.25V

(ideal current

density)

Vdd = 1.5V

(ideal current

density)

65

Figure 4.12: Input Frequency vs. MTTF when Temperature = 423K

This graph looks remarkably similar to the corresponding one for 373K, however there are some

notable differences. As temperature is increased, self heating has a greater impact on the circuit’s

lifetime. This, combined with the much higher current densities, drastically reduces the MTTF of

the device. Looking carefully at the two graphs, one can see that the effects of increased rail

voltages are less severe at the higher temperatures. Current density and temperature take over

and control the circuit’s lifetime. For the ideal case, the changes in MTTF are minimal, as

current density is zero. I still have self heating to worry about, yet its affect is at most 14K on the

internal device temperature, not enough to really decrease MTTF by more than a few years.

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MTTF Improvement Compared to Simulated DataTemp = 423K

Vdd = 1V (ideal

current density)

Vdd = 1.25V (ideal

current density)

Vdd = 1.5V (ideal

current density)

66

4.5.4 Interconnect Sizing

The width of a given interconnect directly affects the current density through it. Increased

interconnect width allows for a reduction of current density through the metal lines. Although

current through the MOSFET is the same, the wider metal width reduces its density. With the

reduction in current density comes a slight decrease in power consumption yet a higher MTTF.

At high current densities (>106 A/cm2), essentially doubling the interconnect width halves the

current density. There is now a wider area for electrons to flow, and this helps prevent the

formation of voids and hillocks that eventually crowd the line and cause it to break. It is

important to note that increasing or decreasing the interconnect width does not change the

current, ONLY the density of that current. Below is a graph showing the MTTF of an inverter

driving a load, with different interconnect sizing at source and drain metal lines. Simulations

were run with an input frequency of 25MHz and rail voltage of 1V and at 373K.

Figure 4.13: Representation of Varying Interconnect Sizing

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Interconnect Width (nm)

MTTF Improvement for Varying Interconnect

Width(compared to width = 75 nm)

MTTF Improvement

67

As you can see, changing interconnect sizing for such a small circuit doesn’t really affect the

MTTF. Yes, the MTTF does increase a bit but it’s a negligible amount. Also, for the model

created to calculate MTTF, there is a constant in front of the equation whose value is 308.64; this

being multiplied by the exponential relationships current density and temperature has on MTTF.

Again, electromigration will not occur unless current density is ultimately high enough to break

the metal line. In larger circuits, current density can approach values >10^7 and electromigration

effects greatly damage a device. How you design the smaller circuits that make up the more

complicated designs is crucial in prolonging the lifetime of the device.

4.5.5 Temperature and Resistivity

Temperature greatly affects the lifetime of a circuit. Increased temperature can lead to

higher current densities and increased resistivity of the metal lines. With today’s scaling down

process, the thickness of metal lines is often reduced, which also adds to the increased resistivity

of the interconnect material. The higher temperature and associated increase in resistivity

exacerbates problems with power consumption and signal delay. Circuit’s run much slower than

they should. Clearly, decreasing the resistance and resistivity of circuit materials may reduce

power consumption and increase the speed at which a circuit switches. Below are figures 4.14

and 4.15 showing the RC time delay between the input and output of an 8 bit RCA. The first has

a starting ambient temperature of 373K while the second runs at 473K.

68

Figure 4.14: RC time delay for 8 Bit RCA ( Delay is 1.43ns temp = 200)

Figure 4.15: RC time delay for 8 Bit RCA (Delay is 1.32 ns Temp = 100)

69

The changes in delay are a bit hard to see, but the numbers show that with the increased

temperature there is an added 110ps of delay. The increased resistivity at the higher temperature

slows down the circuit and consumes more power, causing a decrease in MTTF.

Switching frequency is also a large factor impacting temperature, as the faster a circuit is ran,

the hotter is gets. More power is required and overall failure time decreases. Clearly, decreasing

the clock frequency of a circuit reduces power consumption and temperature, prolonging the

lifetime of the device. I also have to consider the idea of self heating. A temperature increase as a

result of self heating can be detrimental to a circuit’s lifetime. Self heating tends to be more

apparent at much higher temperatures and can often offset a section’s ambient temperature by up

to 25 degrees [26].

As done in earlier sections, I can look more directly at temperature’s impact on MTTF.

Figure 4.16 below shows MTTF vs Input speed for the weak link XOR gate of the Kogge-Stone

adder at 373K. The graph illustrates simulated temperature and also constant temperature (no self

heating). As can be seen, the effects of temperature on MTTF are noticeable, but the change in

MTTF due to temperature is not nearly as significant as that with current density. It can also be

seen that at higher rail voltages the changes to MTTF are more severe, as the circuit consumes

more power.

70

Figure 4.16: MTTF vs. Input speed at Simulated and Constant Temperature (weak link XOR of Kogge-Stone)

Increased temperature does have its drawbacks; however, on the smaller circuits that act

as building blocks for the more complicated designs, the effects are not that severe. Also, the

changes in current density as a result of increased temperature are not large enough to really drop

the MTTF. Figure 4.17 shows the MTTF for the weak link XOR gate for the Kogge-Stone adder

when compared to simulated data. The graph assumes constant current density (same value for

all 373, 423, and 473 Kelvin) with increased temperature. There are no huge differences in the

MTTF of this XOR gate for each of the starting ambient temperatures. As a result, the

improvements made to designs in Chapter 5 will not focus on running the circuits at higher

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MTTF Improvement Compared to Simulated DataTemp = 373K

Vdd = 1V

(constant

temperature)

Vdd = 1.25V

(constant

temperature)

Vdd = 1.5V

(constant

temperature)

71

starting ambient temperatures, but more on the results on increasing temperature as a result of

self heating.

Figure 4.17: Graph Showing MTTF for Constant Current Density at Varying Starting Ambient Temperatures

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72

Chapter 5. Improving Design and Ways to Minimize Failure

The previous chapters show me a very detailed overview of electromigration and also

examine the detrimental effects it can have on a circuit’s lifetime. It is known that the failures

associated with electromigration occur inside the interconnect material and are a result of

electron crowding in various areas within the metal lines. This chapter examines ways to

improve these failures and prolong the lifetime of any given circuit.

Temperature and current density are the two biggest factors to analyze when dealing with

electromigration. Although temperature can be somewhat regulated, for the most part its actions

are out of the designer’s control. Current density can however be greatly reduced with careful

design considerations. Increasing metal line widths at locations where current density is highest

can yield a large reduction in current density (at high current densities, doubling interconnect

width halves current density). For my first improvement, I will look at increasing the metal of the

power rails. It is often the metal lines here that experience the highest current densities, as

current flows from power to GND, and is strongest at the source. This method may or may not

work, depending on the circuit’s behavior. Current distributes itself across a device based on the

operation of that device, and simply increasing the width of the power rails may not be enough.

Thus for my next improvement, I will look at increasing the metal lines at the outputs of a

given circuit. With any design, there are always stages driving other stages. Current must have a

clear path from the output of one device to the input of the next in order operate efficiently and

effectively.

The above changes primarily change the current density component of the MTTF model.

With any alteration to a device comes tradeoffs, be it power consumption, temperature increase,

73

higher delay etc. Low power is of utmost importance in today’s technology, and methods like

lowering the rail voltage and decreasing the clock frequency can help minimize power, but both

of those changes will drastically affect performance.

However, some changes must be made to improve the overall lifetime of the circuit. Again,

with the continued scaling down process of semiconductor devices, all improvement methods

must be carefully examined. They become harder and harder to analyze, but as with any device,

a careful design process is always beneficial to the lifetime of the circuit.

5.1 Improving MTTF of the XOR Gate

The XOR gate is the simplest “complete” circuit in the catalog of circuits tested. A complete

circuit in context of this project will be any circuit having at least two stages, with the first stage

affecting the second, etc. The improvement methods above will first be tested on the XOR gate

to see in fact if MTTF is increased, and also examine the tradeoffs are a result of these

improvements. Once again the weak link was N1.

5.1.1 Increasing Interconnect Width

One improvement technique was to double the interconnect sizing at the source/drain

locations of the weak link. Doing so halves the current density and should thus improve device

failure time. With the XOR gate, current densities are still fairly small due to the simplicity of

the gate type. Current density did decrease by 50% and there was a slight increase in MTTF.

Current densities are in the low thousands and electromigration is not really an issue, hence the

only slight increase in failure time. There is a more noticeable increase in MTTF at faster input

frequencies due to the accompanying higher current densities. Also, the gate was only run at

373K and self heating is not a huge issue. Parasitic capacitance is also slightly reduced; however

74

the small changes have little effect on MTTF; larger circuits may show stronger improvements

with the lower capacitance. There were no performance drawbacks with the increased metal

sizing. Again, I was only targeting the weak links of the smaller circuits. In larger designs, where

more substantial changes are made, performance tradeoffs may become an issue.

Another technique involved increasing the metal width of power and ground lines. This

technique had the same effectiveness as increasing the interconnect width at the source/drain of

the weak link, but only proved effective if power and ground rails were in fact the sources/drains

of the weak links. If not, there was no change to MTTF or to the overall performance of the

circuit.

5.1.2 Decreasing Size of Weak Link

Another improvement technique was to decrease the gate size of the weak link by ½.

Doing so not only reduces capacitance at the gate but also lowers the rise/fall times. Decreasing

the width of the gate weakens the FET and slightly lowers current density (more so at faster

input speeds). MTTF changes very slightly, but it is an increase. There are some noticeable

performance tradeoffs as well. The smaller gate size slows down the circuit and actually

consumes slightly more power. Typically slowing down the circuit would reduce power

consumption, but the single change may not be all that beneficial.

5.1.3 Improving Circuit Speed

The last improvement technique was to increase the speed of the circuit by increasing the P

and N MOSFETs of the stage driving the weak link. The FETs were increased to 2x in size and

there are some very noticeable improvements. The XOR gate is not affected by this change as

the weak link was the first stage in the circuit. In general, this increases the current going through

75

the driving gates but decreases the amount of current through the weak link. This allows for a

lower current density and improved MTTF. This modification however comes at the cost of

power consumption. Although the delay of the circuit decreases, there is a significant increase in

power usage. All of the mentioned changes however focus on designing the circuit around the

weak link. The weak link characteristics are improved, but a new weak link is then found. In

larger designs, changes will focus more on the performance of the entire circuit, now that weak

links and associated improvements can be made.

5.1.4 Failure Time Improvements

Figure 5.1 shows the MTTF improvement of the XOR for various changes. Changing the

source/drain metal line sizes at the weak link proved to be the most effective, as this change

provides the largest reduction in current density. Decreasing the size of the weak link was also

beneficial to the circuit’s lifetime. You can also see that changing the size of power and ground

metal lines had no effect on the MTTF for the gate. As mentioned earlier, this particular change

is only beneficial if either the source/drain of the weak link is in fact VDD/GND, in which case

the change is essentially the same as that mentioned above. The improvements are seen more at

the slower circuit speeds as well. The bar graph clearly shows the improvements on failure time

with the increase of S/D metals and reduction in gate size of the weak link. More importantly,

one can see that the increased sizing of power/ground lines had no further improvement on

MTTF than what was seen with the changes to S/D locations.

76

Figure 5.1: MTTF Improvement of XOR Gate for Various Changes 5.1.5 Affects On Power and Delay

Figures C.1-C.4 in Appendix C show the effects on delay and power consumption for various

changes to the XOR gate, MUX, and Full Adder, again for the two different input frequencies of

25MHz and 400MHz. They will be referred to several times in the next few sections. For the

XOR, delay stays the same for the majority of the changes, increasing slightly with the decreased

gate size of the weak link. Power consumption also remains the same for the majority of the

changes, again increasing slightly with the reduced gate size. Ideally, power should decrease a

bit as the circuit is running slower. However, the input to the failing FET is one of the two inputs

to the XOR gate; it is a perfect square wave at 50% duty cycle and has no internal logic to

change its operation. With that said the current running through the FET doesn’t change that

much, decreasing only slightly. This yields a slightly smaller current density, but essentially

applies more stress to the FET, causing it to use more power. All changes do increase the MTTF.

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5.2 Results on Larger Circuits

The following sections examine modifications to much larger circuits, such as the Kogge

Stone adder and Register File. For the larger circuits, changes will be made to improve the

overall lifetime of the circuits, and not just the weak links.

5.2.1 Kogge-Stone Adder

The changes made to the Kogge-Stone Adder were geared towards improving the lifetime of

the entire device. Thus the changes weren’t nearly as specific as the smaller circuits. The

majority of weak links for the Kogge-Stone Adder were the AND and XOR gates. These gates

are responsible for driving the majority of prefix logic the adder requires. Thus, for FIX1, the

AND and XOR gates were doubled in size, and the prefix logic was reduced to half its original

size. Also, all source/drain metal lines were doubled in width. This only yielded a small increase

on MTTF and caused the circuit to consume more power along with an increase in delay. FIX2

doubled metal size, kept the PPA blocks their original size and decreased the size of the XOR

and AND gates by about 30%. This fix showed a significant increase in MTTF without changing

the delay much, but did consume more power. FIX3 again doubled metal size, increased the size

of the PPA blocks, XOR and AND gates. This led to a similar rise in MTTF as seen for FIX1,

used more power but made the adder faster. The last and final fix was very specific to the weak

link of the adder. It involved increased metal size, and only decreasing the size of the weakest

XOR gate. This show the largest improvement to MTTF, used much less power and kept delay

the same as it was before the fixes. Figure 5.2 below shows the individual subcircuits with and

without FIX1, just to give you an idea of what I were trying to achieve.

78

Figure 5.2: Improvements for Subcircuits of Kogge-Stone Adder

The above graphs only show the effects on FIX1 for the subcircuits, just to give you an idea of

how I seek to increase MTTF. There are a variety of ways to do this; it’s just a matter of

discovering which method is the most effective. Figures 5.3 and 5.4 show the effects on MTTF,

power, and delay for the entire adder using the fixes mentioned above.

0.070.39 0.36

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Figure 5.3: Results on Kogge-Stone Adder for Various Fixes @ 25MHz

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-20

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60

80

100

MTTF Improvement (%)

Delay Increase (%)Power Increase (%)

Kogge-Stone Improvements(Input Frequency = 25MHz)

No Fix Fix 1 Fix 2 Fix 3 Fix 4

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Figure 5.4: Results on Kogge-Stone Adder for Various Fixes @ 400MHz

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MTTF Improvement (%)

Delay Increase (%)Power Increase (%)

Kogge-Stone Improvements(Input Frequency = 400MHz)

No Fix Fix 1 Fix 2 Fix 3 Fix 4

81

Table 5.1: Comparison of Kogge-Stone fixes (Top rows for each fix are for input frequency of 25MHz and bottom rows are for 400MHz.

Fix 4 is most effective at increasing lifetime and decreasing power consumption with only a slight increase in delay. It focuses more on the weak link and doesn’t require increased gate sizing which can increase power and delay. The weak link

remained the same for the first three fixes, yet for fix 4, decreasing the gate size of the weak link XOR allows for a large MTTF improvement)

As you can see from table 5.1, FIX4 proved to be the most effective. The MTTF for both input

frequencies showed the greatest increase, and the circuit even uses less power without sacrificing

delay. The other fixes are also beneficial to the device, yet they don’t have the same amount of

improvement on MTTF and either slow the circuit down or use much more power. For purposes

of this thesis, I really only care about prolonging the lifetime of the circuit, and at a minimum,

doing so without drastically affecting performance. The increased metal sizing does require more

area, but this is the single most effective way to significantly lower current density and reduce

the likelihood of electromigration.

12.98 41.46 1.29

3.12 87.20 46.25

-1.39

0.3130.71 -29.71

2.40 87.12

1.59 97.18 -4.57

24.26 -37.06 0.21

1.70 97.00 40.96

9.90 46.19 0.54

Doubled source/drain metal width, decreased the size of the weakest XOR gate by 30%

1

2

3

4

AND and XOR gates doubled in size, prefix logic reduced to half its original size, source/drain metal Doubled source/drain metal width, kept PPA blocks original size, decreased the size of the XOR and AND Doubled source/drain metal width, increased the size of the PPA blocks, XOR and AND gates by 30%

MTTF Increase (%)

Power Increase (%)

Delay Increase (%)Fix Description

82

5.2.2 Register File

The Register file was comprised of three different subcircuits: the MUXs, the decoders, the

dynamic memory cells. I focused on three areas of the register file, specifically the MUXs, the

decoders, and the inverter before the decoder output. Two potential fixes were tried, and the

overall changes were similar to those done for the Kogge Stone adder. FIX 1 involved doubling

the source/drain metal widths only. This allowed for a large reduction in current density yielding

an increase in MTTF. Power and delay remain very much the same. FIX 2 involved increasing

the metal lines and scaling down the gates for the MUXs and DECODERs by 25%. MTTF

increases, and there is a large reduction in power consumption with only a small increase in

delay. Figures 5.6 and 5.7 show the improvements on MTTF for both fixes on the MUXs and

Decoders.

Figure 5.5: MTTF Results on Register File MUX for Various Fixes

0.29 0.23

3.70

3.10

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

Fix 1 Fix 2

MT

TF

Im

pro

ve

me

nt

(%)

MTTF Improvement for MUX

25MHz

400MHz

Input Frequency

83

Figure 5.6: MTTF Results on Register File Decoder for Various Fixes

For both subcircuits, the fixes are more noticeable at faster input frequencies. MTTF

improvement is roughly the same for both fixes, so both fixes will be applied to the entire

register file. Figures 5.8 and 5.9 show the overall performance for the register file.

0.89 0.84

12.4611.68

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

Fix 1 Fix 2

MT

TF

Im

pro

ve

me

nt

(%)

MTTF Improvement for Decoder

25MHz

400MHz

84

Figure 5.7: Results on Register File for Various Fixes @ 25MHz

-40

-20

0

20

40

60

80

100

MTTF Increase (%)

Delay Increase (%)Power Increase (%)

Register File Improvements(Input Frequency = 25MHz)

No Fix Fix 1 Fix 2

85

Figure 5.8: Results on Register File for Various Fixes @ 400MHz

As can be seen from the table 5.2, FIX 2 has the greatest impact on MTTF, increasing the overall

lifetime over 15%. As with the Kogge Stone adder, the reduced gate size consumes less power,

about 30% less. The delay of the circuit remains roughly the same. There is a slight increase in

delay with FIX 2, but it is only about a 6% increase. This is well worth the large power reduction

and prolonged lifetime of the device. Again, the most effective way to improve MTTF is to

increase interconnect sizing, reducing current crowding inside the metal lines.

-40

-20

0

20

40

60

80

100

MTTF Increase (%)

Delay Increase (%)Power Increase (%)

Register File Improvements(Input Frequency = 400MHz)

No Fix Fix 1 Fix 2

86

Table 5.2: Comparison of Register File Fixes (Top rows for each fix are for input frequency of 25MHz and bottom rows are for 400MHz .

Fix 2 is most effective here. Although the smaller MUX/Decoder gate sizes Slow down the circuit slightly, they consume much less power and overall lifetime

Of the register file is significantly increased)

2

Doubling source/drain metal width and scaling down the gates for the MUXs and DECODERs by 25%

16.41 -39.36 6.60

14.91 -18.97 2.54

1Doubling the source/drain metal line widths only

11.04 0.85 0.12

9.70 0.22 0.00

Fix DescriptionMTTF

Increase (%)Power

Increase (%)Delay

Increase (%)

87

Chapter 6. Conclusions

Electromigration will be a large problem in semiconductor devices if not addressed soon.

With the ongoing scaling down process of microprocessors and other complex devices, the issue

is becoming more and more of a reality. This paper shows the development of a tool chain that

makes it possible to identify the mean-time to failure (MTTF) of several common and high

priority circuits such as complex adders and memories. This tool chain allows designers to

isolate weak-points in these circuits to improve the overall MTTF of the circuit. The result is that

with a few simple changes, circuits can be redesigned to increase the MTTF, at minimal cost to

the system. The tool chain is modular enough to update it with different MTTF models and

therefore this is a platform that can be used in the future as EM becomes well understood.

With the current scaling down process, power consumption and temperature can drastically

increase, as will current density. This causes an overflow of electron crowding in the metal lines

connecting to source and drain locations of MOSFETS, and ultimately destroys the metal lines,

causing the device to fail. Using the developed tool chain, these weak links can be pinpointed

and a variety of simple and smart modifications to any circuit can lead to a drastic increase in

Mean Time to Failure. Some of these potential fixes were explained in chapter 5, and included

decreasing gate widths, increasing metal line widths, and in some cases, increasing gate size of

driving stages. Designers must be more and more careful and keep these modification techniques

in mind to ensure a greater lifetime for these devices. Unfortunately, this is only one time of

wear-out seen in semiconductor devices, and although there are ways to address it, there are

other potential areas of wear-out that can also decrease device lifetime. Luckily for me, the

changes involved in increasing MTTF caused very little or no decrease in performance and only

a slight increase if any in power consumption. Many times the power consumption was also

88

reduced. In summary, one can see that just like there are design methods for maximizing speed

and minimizing delay, there are also those to maximize circuit lifetime. that can improve MTTF;

just as there are many ways to design a circuit for a specific purpose, there are also many ways to

design a circuit for a maximum MTTF.

In completing this thesis, I have learned that there is no simple way to increase failure time.

However, with the aid of the tool chain, weak links can be found and simple modifications can

be made to maximize MTTF. There are certainly many design considerations one must consider,

and if the discussed techniques are kept in mind, then circuit lifetime can definitely increase.

However, as semiconductors continue to grow more complex and reduce in size, these

techniques become harder to implement. Eventually, designers must be willing to sacrifice some

performance in order to really see a great improvement in the lifetime of a device.

89

90

Chapter 7. Works Cited

[1] Hauschildt, M., M. Gall, and S. Thrasher. "Analysis of Electromigration Statistics for Cu Interconnects." Applied Physics Letters 88 (2006). [2] Hiroyuki, Abe, Sasagawa Kazuhiko, and Saka Masumi. "Electromigration Failure of Metal Lines." International Journal of Fracture (2006): 219-240. [3] Computer Simulation Laboratory. 2005. <http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm>. [4] Yamanaka, Kimihiro, Yutaka Tsukada, and Katsuaki Suganuma. "Solder Electromigration in Cu/in/Cu Flip Chip Joint System." Journal of Alloys and Compounds 437 (2007): 186-190. [5] Gras, R., and L.G. Gosset. "Integration and Characterization of Gas Cluster Processing." Microelectronic Engineering 84 (2007): 2675-2680. [6] Tang, Pin F. "Simulation and Computer Models for Electromigration." Electromigration and Electronic Device Degradation. John Wiley & Sons, Inc, 1994. 27-77. [7] Zeghbroeck, B. Van. "Chapter 7: MOS Field-Effect-Transistors." Principles of Semiconductor Devices. 2004. <http://ece-www.colorado.edu/~bart/book/book/chapter7/ch7_7.htm>. [8] Subramoniam, R. A Statistical Model of Oxide Breakdown Based on a Physical Description of Wearout. Proceedings of IEEE International Electron Devices Meeting, 13 Dec. 1992, Electron Devices Soc. IEEE. [9] Pecht, Michael, and Pradeep Lall. "Temperature Dependencies on Electromigration." Electromigration and Electronic Device Degradation. John Wiley & Sons, Inc, 1994. 79-104. [10] Hu, C.-K., L. Gignac, and R. Rosenberg. "Electromigration of Cu/Low Dielectric Constant Interconnects." Microelectronics Reliability 46 (2006): 213-231. [11] Lee, J.C., Chen Ih-Chin, and Hu Chenming. "Modeling and Characterization of Gate Oxide Reliability." IEEE Transactions on Electron Devices 35 (1998). [12] Henderson, Christopher L. "Time Dependent Dielectric Breakdown." Semiconductor Reliability. 2002. <http://www.semitracks.com/manuals/12.pdf>. [13] Allers, K.-H. "Prediction of Dielectric Reliability From I–V Characteristics: Poole–Frenkel Conduction Mechanism Leading to Root(E) Model for Silicon Nitride MIM Capacitor." Microelectronics Reliability 44 (2003): 411-423. [14] Black, J.R. "Electromigration-a Brief Survey and Some Recent Results." IEEE Transactions on Electron Devices (1969).

91

[15] Black, J.R. "Metallization Failures in Integrated Circuits." RADC Technical Report (1968). [16] Kirchheim, R., and U. Kaeber. "Atomistic and Computer Modeling of Metallization Failure of Integrated Circuits By Electromigration." Journal of Applied Physics 70 (1991): 172-181. [17] Noguchi, Junji. "Dominant Factors in TDDB Degradation of Cu Interconnects." IEEE TRANSACTIONS ON ELECTRON DEVICES, 52 (2005): 1743-1750. [18] Shiono, N, and M Itsumi. "A Lifetime Projection Method Using Series Model and Acceleration Factors for TDDB Failures of Thin Gate Oxides." 31st Annual Proceedings. Reliability Physics 1993 (1993): 1-6. [19] Rodder, M. "Oxide Thickness Dependence of Inverter Delay and Device Reliability for 0.25um CMOS Technology." International Electron Devices Meeting 1993. Technical Digest (1993). [20] Chen, Chih, and S. W. Liang. "Electromigration Issues in Lead-Free Solder Joints." J Mater Sci: Mater Electron (2007). [21] Cheng, Y.l., Y.l. Wang, and H.C. Chen. "Effect of Inter-Level Dielectrics on Electromigration in Damascene." Thin Solid Films 494 (2006): 315-319. [22] Zhao, Jian H. "Theoretical and Experimental Study of Electromigration." Electromigration and Electronic Device Degradation. John Wiley & Sons, Inc, 1994. 167-233. [23] Blech, I.A. "Electromigration in Thin Aluminum Films on Titanium Nitride." Journal of Applied Physics 47 (1976): 1203-1208. [24] Sankaranarayanan, Karthik. "[Hotspot] Multiple Core Chip Thermal Model." The HotSpot Archives. 4 Feb. 2008. <http://www.cs.virginia.edu/pipermail/hotspot/>. [25] Wu, W., S. H. Kang, J. S. Yuan, and A. S. Oates. "Electromigration Performance for AI/SiO2, Cu/Si02 and Cdow-K Interconnect Systems including Joule Heating Effect." School of Electrical Engineering & Computer Science, University of Central Florida, Orlando, FL 328 16. Print. [26] Wu, W., S. H. Kang, J. S. Yuan, and A. S. Oates. "Thermal effect on electromigration performance for Al/SiO2, Cu/SiO2 and Cu/low-K interconnect systems." Chip Design and Reliability Laboratory, School of Electrical Engineering and Computer Science, University of Central Florida, P.O. Box 162450, Orlando, FL 32816-2450, USA. Print. [27] Black, J. R. Electromigration. Wikipedia. Web. 07 Aug. 2007. <http://en.wikipedia.org/wiki/Electromigration>.

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[28] Johnson, R. W., J. R. Broomstead, and G. B. Weir. "200°C operation of semiconductor power devices."Components, Hybrids, and Manufacturing Technology, IEEE Transactions on 16.7 (1993): 759-64. Print.

93

Appendices

Appendix A: Background Information

Layout Process

To familiarize you with the formal layout process, below is an image showing the layout

of a 2 input XOR gate.

Figure A.1: Basic Layout of 2-input XOR gate, showing key components.

94

Above is the layout of a 2-input XOR gate. Now, the layouts can be done in a variety of ways,

but you always want to design with practicality in mind. You can see the PMOS and NMOS

transistors circles and the silicon that connects any of the gates between them all. The top rail is

my power (vdd) and the bottom is ground (gnd). The blue metal represents metal layer 1 and the

purple metal represents metal layer 2. The various small “squares” are contacts, used for

connecting different metal types or materials together. You can see both the inputs “a” and “b”

as well as the output “y” appear as contacts. The light green region show what’s known as

“diffusion”, or the source and drain for each of the FETs.

This is obviously not a project on how to layout circuits, however, it is important to

discuss a few issues. When laying out any design, you always want keep transistors, contacts,

metals, etc as closely together as possible, obviously to minimize space. You must however

follow the design rules specified by the layout preferences you set up from the beginning.

Following design rules closely helps minimize the amount of parasitic. It is also best to use as

few metal layers as possible, because with them come lots of parasitic capacitances and

resistances as well. Parasitic capacitance, in electric circuits, is the unavoidable and usually

unwanted capacitance that exists between the parts of an electric component or circuit simply

because of their proximity to each other [27]. Parasitic capacitance can also exist between

closely space conductors, such as metal lines, or PCB traces. The parasitic resistance of a metal

or polysilicon line can also have a profound influence on the signal propagation delay over that

line. The resistance of a line depends on the type of material used (polysilicon, aluminum, gold,

copper, etc), the dimensions of the line and finally, the number and locations of the contacts on

that line (http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/ch04/ch04.html).

1

Layout Diagrams for Small Circuits

Figure A.2: Inverter with S/D Metal Line Width of 75 nm

Figure A.3: Inverter with S/D Metal Line Width of 150 nm

Figure A

Figure A

Figure

96

Figure A.4: The layout for a 2-1 MUX

Figure A.5: The layout for a Full Adder

Figure A.6: Layout of the 3-to-8 Decoder.

97

Figure A.7: Layout of a 12 Transistor SRAM Cell

Circuit Diagrams for Small Circuits

Figure A.8: The Circuit for a NAND-gate (left), and a NOR-gate (right).

Figure A.9: Transistor Network that Creates an Exclusive

Figure A

98

Transistor Network that Creates an Exclusive-OR function.

Figure A.10: 2-1 MUX Circuit Diagram

OR function.

Figure A

Figure A CMOS Kogge-Stone

The propagate and generate gate circuits

tiles. Each layer produces inverted outputs from negating logic gates. The circuits shown below

are shown is CMOS, whereas my signals were created using Output Prediction Logic (OPL).

This is a simple tweak and simply requires the addition of a precharge

and Vout and a footer transistor at the bottom of the NMOS stack to ground.

99

Figure A.11: Full Adder Circuit Diagram

Figure A.12: 12 Transistor SRAM Circuit Diagram

ate and generate gate circuits are shown below for even layer and odd layer

tiles. Each layer produces inverted outputs from negating logic gates. The circuits shown below

are shown is CMOS, whereas my signals were created using Output Prediction Logic (OPL).

This is a simple tweak and simply requires the addition of a precharge transistor between VDD

and Vout and a footer transistor at the bottom of the NMOS stack to ground.

layer and odd layer

tiles. Each layer produces inverted outputs from negating logic gates. The circuits shown below

are shown is CMOS, whereas my signals were created using Output Prediction Logic (OPL).

transistor between VDD

One other issue with the Kogge-Stone is the unbalanced loading of individual tiles. Tiles in the

top right corner of the tree are required to drive more gat

should require sizing some of the gates with higher output capacitance up to keep del

the tree fairly even, however with the current OPL design this sizing adjustment was not made

and I assume that the gates will drive their load adequately.

Figure A.13: Even layer tiled CMOS PPA circuit (inverted inputs, non

Figure A.14: Even layer tiled CMOS

100

Stone is the unbalanced loading of individual tiles. Tiles in the

top right corner of the tree are required to drive more gates than tiles in the left of the tree. This

sizing some of the gates with higher output capacitance up to keep del

the tree fairly even, however with the current OPL design this sizing adjustment was not made

gates will drive their load adequately.

: Even layer tiled CMOS PPA circuit (inverted inputs, non-inverted outputs)

: Even layer tiled CMOS-OPL PPA circuit layout cell

Stone is the unbalanced loading of individual tiles. Tiles in the

es than tiles in the left of the tree. This

sizing some of the gates with higher output capacitance up to keep delay through

the tree fairly even, however with the current OPL design this sizing adjustment was not made

inverted outputs)

Figure A.15: Odd Layer Tiled CMOS PPA circuit (non

Figure A.16

The architecture selected for the final design is OPL Kogge

adder was chosen because the PPA sub

evaluate the carry-in values for each bit in a Kogge

generate the same carry-in for each bit that the tiles of the CLA would generate, and therefore

both adder architectures require similar fr

Xi and Yi (inputs) and in 2 logic stages outputs the propagate (pi) and generate (gi) signals for

each bit. Those signals are inputs to the K

101

: Odd Layer Tiled CMOS PPA circuit (non-inverted inputs, inverted outputs)

.16: Odd Layer Tiled CMOS-OPL PPA circuit cell

The architecture selected for the final design is OPL Kogge-Stone Radix-2 Prefix Adder. This

adder was chosen because the PPA sub-circuits already developed and tested would properly

in values for each bit in a Kogge-Stone prefix tree. The PPAs of the K

in for each bit that the tiles of the CLA would generate, and therefore

both adder architectures require similar front and back logic blocks. The front logic block takes

Xi and Yi (inputs) and in 2 logic stages outputs the propagate (pi) and generate (gi) signals for

each bit. Those signals are inputs to the K-S tree, along with the carry-in for bit 0, and the

rted inputs, inverted outputs)

2 Prefix Adder. This

sted would properly

The PPAs of the K-S tree

in for each bit that the tiles of the CLA would generate, and therefore

ont and back logic blocks. The front logic block takes

Xi and Yi (inputs) and in 2 logic stages outputs the propagate (pi) and generate (gi) signals for

in for bit 0, and the

102

outputs of the K-S tree are the carry-in (ci) for each bit. The K-S tree has five logic stages. The

final two stages calculate the sum (Si) for each bit and the carry-out (C16) for the adder. The

basic design requires nine logic stages from Xi,Yi to Si and C16.

Figure A.17: CMOS OPL layout circuits for AND (left) and XOR (right) gates used for the Pi and Gi signals The complete 16-bit Kogge-Stone Parallel Prefix Adder layout is shown below. The center of

the layout area has three north-south parallel signal lines for VDD, GND, and the clock (CLK).

These branch at each layer of the tree to provide connection to the individual cells. The last PPA

for evaluating carry-out from the Gi/Pi bit 15 column has been pushed up into the fourth row to

save total area in the cell; that fourth row is shifted to the right by one PPA cell to accommodate

that last row collapse.

103

Figure A.18: Complete 16-bit Kogge-Stone Adder layout

104

Appendix B: Small Circuit Evaluation

The following sections analyze failure times for small circuits. All tested gates assumed 2

ideal inputs, yielding all input-output combinations. I will call this input strategy “ideal inputs”.

Ideally, having an average gate voltage exactly half of the rail voltage over a long period of time

ensures the gate is ON/OFF for equal time periods. This however doesn’t mean that the failure

locations will be at the gate. In fact, current densities at the gate are often much lower than

source/drain locations. This input strategy will be referred to as the “optimal voltage” which also

corresponds to the “optimal current density”. The data obtained from gate-level simulations is

very important, as these basic gates are the building blocks for subcircuits used in more complex,

higher level designs.

The NAND and NOR Gates

The NAND and NOR gates have a very similar design. If given ideal inputs, their failure

times are roughly the same. For the NAND gate, the higher current densities are found in the

NMOS FETs, as all the current has a straight path to ground through both FETs. However, with

the PMOS FETs, there is a current split between the two. The two gates are essentially “flipped”

versions of one another so the behavior makes sense.

The temperature difference across the gate is too small to have any real effect on MTTF.

Thus, it is the current density that readily determines the failure time. Still, the circuits are too

small for the current density changes to have any drastic effect on MTTF. Also, just like the

inverter, higher MTTF means more power.

105

The XOR-gate

The XOR-gate is made using two inverters for the inputs and eight (8) MOSFETS arranged

in the network shown in figure 7.9. With ideal inputs, all FETs are on 50% of the time, thus all

locations can be said to have “optimal current density”. Again, the source/drain locations are

most prone to failure as this is where the majority of interconnect material is found, not at the

gates (mostly silicon). I can also note that with faster inputs comes a much more erratic current

and higher current density which in turn lowers the MTTF. Figures 7.19 and 7.20 shows the

source current for NMOS1 for input frequencies of 25MHz and 400MHz. NMOS1 is the one of

FETs found at the pull down network (PDN) closest to GND and it makes sense as to why this

would be a weak link. Here the PDN is very active and the current has a clear path from the

source to ground. Current is much higher here, and this yields an increased current density.

However, when the input frequency is 25MHz the source current is able to stabilize and stays

minimal. At 400MHz, the source current is very erratic and current spiking can be seen, which

increases the average current.

106

Figure B.1: NMOS1 Source Current for 25MHz

Figure B.2: NMOS1 Source Current for 400MHz

107

For the case when the input frequency is 25MHz, it was seen that the average source current of

NMOS1 stays low, minimizing current density. The failure site for this case is actually at the

source of PMOS5. Here the source is the power rail so naturally, source current and current

density will be high. When the frequency reaches 400MHz, the circuit is much less stable. A

higher average current is found at the source of NMOS1 as the current takes significantly more

time to stabilize.

The AND and OR Gates

The AND gate was designed using a NAND gate as a basic, and placing an inverter at the

output. Similarly, the OR gate was designed using a NOR gate. For the AND gate, assuming

ideal inputs, the failure location is at the source of NMOS1 despite the input frequency. For the

OR gate, the failure location is the source of PMOS0 at 25MHz and the drain of PMOS1 at faster

switching frequencies.

For the AND gate, NMOS1 is the top FET in the PDN. If I look at the voltage at the gate of

this FET, it is high 75% of the time, meaning this FET is on 75% of the time. With more usage

comes higher current density. Seeing as how it’s on 3x longer than off, it makes sense that it fails

first. The OR gate is a bit more interesting. At an input frequency of 25MHz, PMOS0 fails first.

Current density is highest at the source of this FET, which happens to be the power rail as seen

with the XOR gate. Any current leaving the power rail is going to be significant when compared

to other locations, as the power rail is high 100% of the time. At higher frequencies, the failure

site moves to PMOS1, where current density is highest at the drain. Similar to the AND gate, the

voltage at the gate of PMOS1 is low 75% of the time, meaning this FET is on 75% of the time.

Naturally, current density is much higher in this region, making it a prone site to failure.

108

Obviously, at the higher frequencies the higher current densities move away from the power rail

to other prone sites.

Just like the XOR-gate, increasing the input frequency affects the MTTF of the two gates.

The faster switching frequencies prevent the logic levels from reaching full high/low potential

and make the currents much more irregular. This increases the average current through a given

location, yielding a higher current density thus a lower MTTF.

Multiplexer (MUX)

The MUX utilizes inverters but none of the standard gates and instead uses the transistors to

effectively connect the output inverter to the rail or ground based on what the select bit is. By

using the information gathered from my gate-level circuits, one can assume that one of the

PMOS FETs is likely to fail first. First of all, all PMOS FETs are connected to the power rail and

will naturally have high current densities through the interconnect material. After simulating the

MUX, it turns out that the weak link is PMOS5. This is a very reasonable conclusion, as this is

the PMOS of the large inverter before the output of the MUX. The CMOS logic before this stage

has a heavy load to drive, not to mention that the size of the PMOS is much larger than any of

the other FETS. Also, the CMOS stage has quite a bit of interconnect material and current

through this stage is not forced into a particular area. At the inverter stage, all current from the

power rail flows directly into PMOS5.

Second, the input to the inverter is stressed, and the rise/falls times are slow, preventing

the output from reaching its full potential. Thus, this region is my failure site. Again, temperature

was not a huge factor in determining MTTF for this device.

109

Full Adder

The full adder was implemented using the following equations:

The alternative to the sum would be:

Using the first set of equations reduces transistor count, as the sum is generated using part of

the carry out logic. Similar to the MUX, no standard logic gates are used to implement the full

adder. Inverters are used, but the rest of the design used standard FETs. Analyzing this circuit is

also similar to what was done for the MUX.

The weak link for this design of the full adder is NMOS5, which is the NMOS shown in the

middle of figure 7.5. NMOS5 is part of one of the inverters used in the design and is very heavily

stressed. The input to this FET is /Cout, and seeing as determining the carry out bit requires a

significant amount of logic this is a likely failure location. The output of this inverter is also the

piece of carry logic used to obtain the sum. The drain of this FET happens to be /Sum, and adds

additional stress to this region. The waveforms below show the drain/source current for this FET.

Again, the glitches/current spiking bring the average source/drain current up significantly

increasing current density. Temperature for the full adder is not really a factor in its failure. The

next circuits all make use of subcircuits, and Hotspot will soon show that self heating becomes a

much larger factor.

S = A xor B xor C

Cout = C(A + B) + AB,

S = !A!BC + !AB!C + A!B!C + ABC

110

Decoder

The 3-to-8 decoder used for this project consists of NOR-gates and inverters. There are three

inverters that make up the inverter chain, which supplies the 3 inputs (A, B, and C) and their

compliments. The appropriate inputs were then connected to one of the NOR-gates in the NOR-

chain to obtain the correct logic. The weakest link for this design was the second furthest PMOS

from the inverted B signal. Again, the PMOS FETs typically experience much larger current

densities than the NMOS FETs, so this failure site is justifiable. However, the B signal is only

the second fastest input, which means speed was not the main factor in determining failure.

Temperature as well was not a huge factor here, as this was one of the cooler areas on the device.

Ultimately, very high current density is what caused this FET to fail. This PMOS is in the middle

of the 3 FET chain found in the NOR gate, and current density at the source is very high. It

shares its source with the drain of the first PMOS in the chain, which has all the current fed from

VDD. The results for this decoder are somewhat interesting, as the failing PMOS is on less than

it is off. Also, average gate voltage is about 660mV, higher than the nominal value of 500mV.

These are reasons as to why this wouldn’t be the weakest link, but they do not outweigh the very

high current running through the FET. Self heating is not yet a factor, but will for sure play a role

in the more complex circuits.

Summary

In this section, it was shown that for small circuits, current density and input frequency

are the two main factors in determining MTTF. Higher frequencies and current densities yield

lower MTTFs. Temperature does play a role, however for these small circuits, temperature is

roughly the same throughout the device. The differences have negligible effect on MTTF.

Typically, FETs that are on longer than they are off are prone failure sites. The failure locations

111

are different in each case, depending on the concentration of current density in each area. In

theory, given ideal inputs, all FETs should be on/off for equal amounts of time. However, it is

clear that this is not always the case.

112

Appendix C: Results for Small Circuits

Figure C.1: Delay for Various Changes to Small Circuits @ 25 MHz

223 223 223

286

239 239 239226 231

297 297 297

351

241

0

50

100

150

200

250

300

350

400

Default S/D 2x VDD/GND 2x Gate 1/2x Prev 2x

De

lay

(p

s)

Delay for Various Changes(input Frequency = 25 MHz)

XOR

MUX

Full Adder

113

Figure C.2: Delay for Various Changes to Small Circuits @ 400 MH

Figure C.3: Power Consumption for Various Changes to Small Circuits at 25 MHz

178 178 178

223

198 198 198186 191

248 249 248

298

204

0

50

100

150

200

250

300

350

Default S/D 2x VDD/GND 2x Gate 1/2x Prev 2x

De

lay

(p

s)Delay for Various Changes

(input Frequency = 400 MHz)

XOR

MUX

Full Adder

15 15 15

19

53 53 53

32

5351 52 51

48 48

0

10

20

30

40

50

60

Default S/D 2x VDD/GND 2x Gate 1/2x Prev 2x

Po

we

r (n

W)

Power Consumption for Various Changes(input Frequency = 25 MHz)

XOR

MUX

Full Adder

114

Figure C.4: Power Consumption for Various Changes to Small Circuits at 400 MHz Improving the MUX

The same changes made to the XOR gate in Chapter 5 were implemented on a 2-input MUX.

Again, the weak link was PMOS5, the large PMOS of the output inverter. Doubling the

interconnect width at the source/drain locations of the weak link proved to be most effective.

This is the easiest way to reduce current density, which is one of the two contributing factors to

electromigration. Increasing the width of the power/ground rails had the same effect as before, as

the source of the failing FET was VDD. Decreasing the width of the PMOS5 gate also increased

MTTF. This reduces the amount of current going to the FET and in turn lowers current density.

Finally, changing the speed of the circuit by modifying the stage driving the weak link also

slightly increases MTTF. Again, all the changes made to/around the weak link yield another

failure site. In larger designs, the changes will hopefully increase the MTTF of the entire design.

219 219 219

289

588 589 588

385

554

711 712 711684

645

0

100

200

300

400

500

600

700

800

Default S/D 2x VDD/GND 2x Gate 1/2x Prev 2x

Po

we

r (n

W)

Power Consumption for Various Changes(input Frequency = 400 MHz)

XOR

MUX

Full Adder

115

Figure C.5: MTTF Improvement of the MUX for various changes

Figure C.5 shows the changes in MTTF with the various circuit modifications. With the

improvement in MTTF come some delay and power tradeoffs. Figures C.1 through C.4 show the

changes on delay and power consumption. As you can see, delay remains the same for changes

to interconnect material. However, when the gate of the weak link is reduced in size, the circuit

actually speeds up, as it does when the driving stage is increased in size. The results make sense,

since it is the output inverter that is being driven by the rest of the circuit. Reducing its size

makes the load weaker and allows the circuit to speed up. Also, increasing the size of the driving

stage makes that stage stronger and allows it to more effectively drive the output inverter. Power

also stays the same for changes in interconnect sizing. Power consumption is reduced for smaller

gate size, but variable with changes to the driving stage. It increases slightly at low input

frequencies and decreases a bit at higher frequencies.

0.12 0.120.06

0.00

1.45 1.46

0.88

0.12

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

S/D 2x VDD/GND 2x Gate 1/2x Prev 2x

MT

TF

Im

pro

ve

me

nt

(%)

MTTF Improvement for Various Changes

25MHz

400MHz

Input Frequency

116

Improving a Full Adder

The changes from the previous sections were again implemented, but this time on a full

adder. The weak link was NMOS5 used in the inverter that outputs Cout. Similar performance

results were found for the full adder. All changes increased MTTF by marginal amounts with the

interconnect sizing at the source/drain of the weak link being the most effective. This time

around increasing the size of the power/ground metal lines has no effect on MTTF, as they are

not tied to the failure site. Changes in MTTF are much greater for higher input frequencies.

Figure C.6 shows the MTTF improvement for the various changes.

Figure C.6: MTTF Improvement of the Full Adder for various changes

There are some very noticeable changes to delay and power consumption as well. Figures 7.21-

7.24 show these changes respectively. Delay remains the same for all metal changes. This will be

0.21

0.00 0.03 0.01

2.65

0.00

0.48

0.17

0

0.5

1

1.5

2

2.5

3

S/D 2x VDD/GND 2x Gate 1/2x Prev 2x

MT

TF

Im

pro

ve

me

nt

(%)

MTTF Improvment for Various Changes

25MHz

400MHz

Input Frequency

117

the case always, as increasing or decreasing the size if the metal lines do not change the amount

of current going through them, only the current density. Decreasing the gate size of the weak link

makes the inverter weaker, increasing the amount of time the inverter take to actually invert the

signal. If I increase the size of the driving stage, this speeds up the circuit and allows the rise/fall

times for the inverter to reach their nominal value. Power consumption is reduced in both cases.

Maximum Improvement

The ideas described in the previous section suggest various ways to improve the lifetime

of a circuit. To completely maximize this MTTF, all of the changes can be implemented

simultaneously. For the total “fix”, the driving stage was increased in size, the weak link

decreased in size, and the source/drain metal lines were doubled in width. The figures below

show the effects of the entire fix on tested MUX and full adder.

Figure C.7: Overall MTTF Improvement for MUX and Fu ll Adder

0.14

1.78

0.23

2.87

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

25 MHz 400MHz

MT

TF

Im

pro

ve

me

nt

(%)

Input Frequency (MHz)

Overall MTTF Improvement for Small Circuits

MUX

Full Adder

118

Figure C.8: Delay for the fixed MUX and Full Adder

Figure C.9: Power Consumption for fixed MUX and Full Adder

248

202

293

251

0

50

100

150

200

250

300

350

25 MHz 400MHz

De

lay

(p

s)

Input Frequency (MHz)

Delay for Small Circuits

MUX

Full Adder

32

378

45

632

0

100

200

300

400

500

600

700

25 MHz 400MHz

Po

we

r (n

W)

Input Frequency (MHz)

Power Consumption for Small Circuits

MUX

Full Adder

119

Summary for Simple Circuits

It is clear that in order to maximize the lifetime of the circuits, multiple changes had to be

made to each design. Each of the changes is beneficial to the circuit in its own way, but a single

change is not always best. For example, decreasing the gate size of the weak link increases

MTTF, but makes the circuit much slower. Sizing up the driving stage also improves failure

time, but sometimes at the cost of power consumption. Ideally, I want to improve MTTF but do

so without negatively affecting other performance aspects of the device.

The so-called “fix” for these simple circuits involved three main modifications.

Increasing the size of the driving stage helps speed the circuit up minimizing delay. It makes the

driving stage stronger and the load that much easier to drive. Decreasing the size of the weak link

consumes much less power and minimizes the amount of current going through that FET.

Finally, doubling the width of the metal lines surrounding the weak link halves the current

density associated with the metal. Increasing the driving stage does speed up the circuit, but

consumes more power. However, this extra power consumption and reduction in delay is

countered with the decrease in gate size of the weak link. That decrease uses less power but at

the cost of delay. The increased metal sizing is the most effective way of reducing current

density but requires more area, which with today’s scaling down process could pose a problem.

As can be seen in the figures from Section 5.4, the “fix” provides a strong increase on MTTF,

especially at faster input frequencies. Overall, the delay remains about the same and power

consumption is significantly reduced.

120

Appendix D: List of Acronyms

Al2O3 Aluminum Oxide DC Direct Current DRC Design Rule Checker EDA Electronic Design Automation EDIF Electronic Design Interchange Format

TDDB Time Dependant Dielectric Breakdown

EM Electromigration

PDN Pull Down Network

FET, MOS, MOSFET Metal-Oxide Semiconductor Field-Effect Transistor

IC Integrated Circuit KS Kogge-Stone

LEF/DEF Library Exchange Format/Design Exchange Format

MOSIS Metal Oxide Semiconductor Implementation Service

MTTF Mean Time to Failure MUX Multiplexor NMOS, N-MOSFET n-Channel MOSFET OPL Output Prediction Logic PAL Programmable Array Logic PCB Printed Circuit Board PF Poole-Frenkel PMOS, P-MOSFET p-Channel MOSFET PPA Parallel Prefix Adder RC Resistor-Capacitor Circuit RCA Ripple Carrier Adder SRAM Static RAM (Random Access Memory)

EM Electromigration

VHDL VHSIC (Very High Speed Integrated Circuits) Hardware Description Language

VLSI Very Large Scale Integration

Table D.1: List of Acronyms

121

Appendix E: List of Equations

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