Digggital Integrated Circuits - chungbuk.ac.krbandi.chungbuk.ac.kr/~bdyang/lecture_digital_integrated... · 2011-03-02 · Power Dissipation TrendsPower Dissipation Trends Power consumption

Digital Integrated Digital Integrated g gg gCircuitsCircuits

Coping withCoping withCoping withCoping withInterconnectInterconnectInterconnectInterconnect

© Digital Integrated Circuits2nd Interconnect

Impact of Interconnect ParasiticsImpact of Interconnect ParasiticsImpact of Interconnect ParasiticsImpact of Interconnect Parasitics• Reduce Robustness• Reduce Robustness• Affect Performance

• Increase delay• Increase power dissipation

Classes of Parasitics

• Capacitive

• Resistive

• Inductive


INTERCONNECTINTERCONNECTINTERCONNECTINTERCONNECT


Capacitive Cross TalkCapacitive Cross TalkCapacitive Cross TalkCapacitive Cross Talk


Capacitive Cross TalkCapacitive Cross TalkD i N dD i N dDynamic NodeDynamic Node

V

C

VDD

CLK

CY

CXYCLK

Y

CY

PDNIn1In2In3

X

2.5 V

CLK

3

0 V

3 x 1 μm overlap: 0 19 V disturbance


3 x 1 μm overlap: 0.19 V disturbance

Capacitive Cross TalkCapacitive Cross TalkD i N dD i N dDriven NodeDriven Node

0 50.50.450.4

0 35X t ↑

τXY = RY(CXY+CY)

0.350.3

0.25

X

YVX

RYCXY

C

tr↑

V (Volt)0.2

0.150.1

CY

0

0.050 10.80.6

t ( )0.40.2

Keep time-constant smaller than rise time

t (nsec)


Dealing with Capacitive Cross TalkDealing with Capacitive Cross TalkDealing with Capacitive Cross TalkDealing with Capacitive Cross Talk

Avoid floating nodesP t t iti dProtect sensitive nodesMake rise and fall times as large as possibleDifferential signalingDo not run wires together for a long distanceUse shielding wiresUse shielding layersUse shielding layers


ShieldingShieldingShieldingShieldingShielding

GND

wire

ShieldingVDDg

layerVDD

GND

Substrate (GND )


Cross Talk and PerformanceCross Talk and Performance- When neighboring lines

it h i it di ti f

Cc

switch in opposite direction of victim line, delay increases

DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRESWIRES

Miller EffectMiller EffectMiller EffectMiller Effect

- Both terminals of capacitor are switched in opposite directions (0 → V V → 0)(0 → Vdd, Vdd → 0)

- Effective voltage is doubled and additional charge is needed (from Q=CV)


( Q )

I t f C T lk D l I t f C T lk D l Impact of Cross Talk on Delay Impact of Cross Talk on Delay

r is ratio between capacitance to GND and to neighbor


Structured Predictable InterconnectStructured Predictable InterconnectStructured Predictable InterconnectStructured Predictable InterconnectS SV V SGS SV V SG

SSV

SSV

SG

S

VS

GS

VVVExample: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitance


Also: FPGAs, VPGAs

Interconnect ProjectionsInterconnect ProjectionsLowLow k dielectricsk dielectricsLowLow--k dielectricsk dielectrics

Both delay and power are reduced by dropping interconnectBoth delay and power are reduced by dropping interconnect capacitanceTypes of low-k materials include: inorganic (SiO2), organic (P l i id ) d l ( lt l k)(Polyimides) and aerogels (ultra low-k)The numbers below are on the conservative side of the NRTS roadmapp

ε

Generation 0.25μm

0.18μm

0.13μm

0.1μm

0.07μm

0.05μmμm μm μm μm μm μm

DielectricConstant

3.3 2.7 2.3 2.0 1.8 1.5


Encoding Data Avoids WorstEncoding Data Avoids Worst--CaseCaseC di iC di iConditionsConditions

In

Encoder

Bus

Decoder

Out


D i i L C itD i i L C itDriving Large CapacitancesDriving Large CapacitancesVVDD

Vin VoutV in Vout

CL

• Transistor Sizing• Cascaded Buffers• Cascaded Buffers


Using Cascaded BuffersUsing Cascaded BuffersUsing Cascaded BuffersUsing Cascaded Buffers

In Out

CL = 20 pF1 2 N

0.25 μm processCin = 2.5 fFtp0 = 30 ps

F = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns

(See Chapter 5)


O t t D i D iO t t D i D iOutput Driver DesignOutput Driver Design

Trade off Performance for Area and EnergyGiven tpmax find N and f

AreaArea( ) minminmin

12

11

11...1 A

fFA

ffAfffA

NN

driver −−

=−−

=++++= −

Energyff

( ) 22212 11 LN VCVCFVCfffE ≈−

=++++= −( )11

...1 DDDDiDDidriver Vf

VCf

VCfffE−

≈−

=++++=


Delay as a Function of F and NDelay as a Function of F and NDelay as a Function of F and NDelay as a Function of F and N10,000

F = 10,000

1000

0 p/tp0

100tp/tp0

F 100F = 1000

t p

10

F = 100F = 1000

101 3 5 7

Number of buffer stages N

9 11


Output Driver DesignOutput Driver DesignOutput Driver DesignOutput Driver Design0.25 μm process, CL = 20 pF

Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns

0.25 μm process, CL 20 pF

Transistor Sizes of redesigned cascaded buffer t = 1 8 nsTransistor Sizes of redesigned cascaded buffer tp = 1.8 ns


How to Design Large TransistorsHow to Design Large TransistorsHow to Design Large TransistorsHow to Design Large Transistors

D(rain)

Multiple Reduces diffusion capacitanceMultipleContacts Reduces gate resistance

S(ource)

G(ate)

small transistors in parallel


Bonding Pad DesignBonding Pad DesignBonding Pad DesignBonding Pad DesignBonding Pad GND

100 μm

Out

InVDD GND Out


ESD P t tiESD P t tiESD ProtectionESD ProtectionWhen a chip is connected to a board, there is unknown (potentially large) static voltage u o (pote t a y a ge) stat c o tagedifferenceEqualizing potentials requires (large) chargeEqualizing potentials requires (large) charge flow through the padsDiodes sink this charge into the substrateDiodes sink this charge into the substrate –need guard rings to pick it up.


ESD P t tiESD P t tiESD ProtectionESD Protection

Diode


Chi P k iChi P k iChip PackagingChip Packaging


Pad FramePad FramePad FramePad FrameLayout Die PhotoLayout Die Photo


Chi P k iChi P k iChip PackagingChip PackagingA lt ti i ‘fli hi ’An alternative is ‘flip-chip’:

Pads are distributed around the chipThe soldering balls are placed on padsThe chip is ‘flipped’ onto the packageCan have many more pads

Die

Solder bumps

InterconnectInterconnect

layers

© Digital Integrated Circuits2nd InterconnectSubstrate

Tristate BuffersTristate BuffersVDDVDD

VDDEn

InEn

Out

En

EnOut

EnIn

En

Increased output drive

Out = In.En + Z.En


Reducing the swingReducing the swingReducing the swingReducing the swing

tpHL = CL Vswing/2

IavIav

R d i th i t ti ll i ld liReducing the swing potentially yields linear reduction in delay

Also results in reduction in power dissipationAlso results in reduction in power dissipationDelay penalty is paid by the receiver Requires use of “sense amplifier” to restore signal g

levelFrequently designed differentially (e.g. LVDS)


SingleSingle--Ended Static Driver and Ended Static Driver and R iR iReceiverReceiver

VDD

VDD VDD

VDDLVDD VDDL

VDDLOutOut

CL

LIn

d i idriver receiver


Dynamic Reduced Swing NetworkDynamic Reduced Swing NetworkDynamic Reduced Swing NetworkDynamic Reduced Swing Network

f M2 M4

VDD VDD

fIn2.fIn1. M1 M3Cbus Cout

Bus Out

V busVasym

V sym1 5

2

2.5

V(Volt) f

sym

0 5

1

1.5

2 4 6time (ns)

8 10 120

0.5

0


( )



I t f R i tI t f R i tImpact of ResistanceImpact of ResistanceWe have already learned how to drive RC interconnectImpact of resistance is commonly seen in power supply distribution:

IR dropVoltage variations

Power supply is distributed to minimize the IR drop and the change in current due to

it hi f tswitching of gates


RI I t d d N iRI I t d d N iRI Introduced NoiseRI Introduced NoiseIVDD

XR ‘

f pre VDD - ∆V ‘

M1

X

∆VI

R∆V


Power Dissipation TrendsPower Dissipation TrendsPower Dissipation TrendsPower Dissipation Trends

Power consumption is increasingPower consumption is increasingPower Dissipation Power consumption is increasingPower consumption is increasingBetter cooling technology neededBetter cooling technology needed

Supply current is increasing faster!Supply current is increasing faster!

p

100120140160

(W)

22.533.5

e (V

)

pp y gpp y gOnOn--chip signal integrity will be a major chip signal integrity will be a major issueissuePower and current distribution are criticalPower and current distribution are critical

20406080

Pow

er

0.511.52

Vol

tage

Power and current distribution are criticalPower and current distribution are criticalOpportunities to slow power growthOpportunities to slow power growth

Accelerate Accelerate VddVdd scalingscaling

0EV4 EV5 EV6 EV7 EV8

0

Supply Current140 3 5 gg

Low κ dielectrics & thinner (Cu) Low κ dielectrics & thinner (Cu) interconnectinterconnectSOI circuit innovationsSOI circuit innovations80

100120140

ent (

A)

22.533.5

ge (V

)

SOI circuit innovations SOI circuit innovations Clock system designClock system designmicromicro--architecturearchitecture

0204060

Cur

re

00.511.5

Volta

© Digital Integrated Circuits2nd Interconnect19

ASP DAC 2000

0EV4 EV5 EV6 EV7 EV8

0

Resistance and the Power Resistance and the Power Di t ib ti P bl Di t ib ti P bl V lt DV lt DDistribution Problem Distribution Problem Voltage DropVoltage Drop

BeforeBefore AfterAfter

•• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction•• Heavily influenced by packaging technologyHeavily influenced by packaging technology

© Digital Integrated Circuits2nd InterconnectSource: Cadence

P Di t ib tiP Di t ib tiPower DistributionPower DistributionLow-level distribution is in Metal 1Power has to be ‘strapped’ in higher layers ofPower has to be strapped in higher layers of metal.The spacing is set by IR dropThe spacing is set by IR drop, electromigration, inductive effectsAl lti l t t tAlways use multiple contacts on straps


P d G d Di t ib tiP d G d Di t ib tiPower and Ground DistributionPower and Ground DistributionVDD GND

Logic Logic

VDD VDD

GND GND

(a) Finger-shaped network (b) Network with multiple supply pins


3 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)y pp ( )y pp ( )3rd “coarse and thick” metal layer added to the

technology for EV4 designtechnology for EV4 designPower supplied from two sides of the die via 3rd metal layer

2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routing90% of 3rd metal layer used for power/clock routing

Metal 3

Metal 2Metal 1

© Digital Integrated Circuits2nd InterconnectCourtesy Compaq

4 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)y pp ( )y pp ( )4th “coarse and thick” metal layer added to the

technology for EV5 designgy gPower supplied from four sides of the dieGrid strapping done all in coarse metal

90% of 3rd and 4th metals used for power/clock routingp g

Metal 4

Metal 3Metal 3

Metal 2Metal 2Metal 1

© Digital Integrated Circuits2nd InterconnectCourtesy Compaq

6 Metal Layer Approach 6 Metal Layer Approach –– EV6EV62 reference plane metal layers added to the

technology for EV6 design

6 Metal Layer Approach 6 Metal Layer Approach EV6EV6

technology for EV6 designSolid planes dedicated to Vdd/Vss

Significantly lowers resistance of gridL hi i d tLowers on-chip inductance

RP2/Vdd

Metal 4

M t l 3

RP1/Vss

Metal 3

Metal 2Metal 1


Metal 1

Courtesy Compaq

Electromigration (1)Electromigration (1)Electromigration (1)Electromigration (1)

Limits dc-current to 1 mA/μm


μ

Electromigration (2)Electromigration (2)Electromigration (2)Electromigration (2)


Resistivity and PerformanceResistivity and PerformanceyyTr

The distributed rcThe distributed rc--lineline

R1 R2 RN-1 RN

The distributed rcThe distributed rc--lineline

CN-1 CNC2C1

Vin

2.5

x= L/10

2.5

x= L/10

Diff d i lDiff d i l

1

1.5

2ol

tage

(V

)

x = L/4

x = L/2 1

1.5

2ol

tage

(V

)

x = L/4

x = L/2

Diffused signal Diffused signal propagationpropagation

0

0.5

1vo

x= L

0

0.5

1vo

x= L

Delay ~ LDelay ~ L22


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5time (nsec)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5time (nsec)

Th Gl b l Wi P blTh Gl b l Wi P blThe Global Wire ProblemThe Global Wire Problem( )( )outwwdoutdwwd CRCRCRCRT +++= 693.0377.0

ChallengesNo further improvements to be expected after the i t d ti f C ( d ti ti l?)introduction of Copper (superconducting, optical?)Design solutions

Use of fat wiresUse of fat wiresInsert repeaters — but might become prohibitive (power, area)Efficient chip floorplanning

Towards “communication-based” design How to deal with latency?Is synchronicity an absolute necessity?


Is synchronicity an absolute necessity?

I t t P j ti CI t t P j ti CInterconnect Projections: CopperInterconnect Projections: CopperCopper is planned in full sub-0.25 μm process flows and large-scale d i (IBM M t l IEDM97)designs (IBM, Motorola, IEDM97)With cladding and other effects, Cu ~ 2.2 μΩ-cm vs. 3.5 for Al(Cu) ⇒μ ( )40% reduction in resistanceElectromigration improvement; 100X longer lifetime (IBM100X longer lifetime (IBM, IEDM97)

Electromigration is a limiting factor beyond 0 18 μm if Al is used (HP

Viasbeyond 0.18 μm if Al is used (HP, IEDM95)


Interconnect:Interconnect:# of Wiring Layers# of Wiring Layers# of Wiring Layers# of Wiring Layers

# of metal layers is steadily increasing due to:• Increasing die size and device count: we need more wires and longer wires to connect everything

M6

Tins

ρ = 2.2 μΩ-cm

y g

• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC

M5

WS low RC

M4H

S

Minimum Widths (Relative)

3.0

3.5Minimum Spacing (Relative)

3.5

4.0

M2

M3

1.5

2.0

2.5

M5M4M3 1 5

2.0

2.5

3.0

M5M4M3

substrate

poly

M1

M2

0 25 μm wiring stack 0 0

0.5

1.0M3M2M1Poly

0 0

0.5

1.0

1.5 M3M2M1Poly


0.25 μm wiring stack 0.01.0μ 0.8μ 0.6μ 0.35μ 0.25μ

0.01.0μ 0.8μ 0.6μ 0.35μ 0.25μ

Diagonal WiringDiagonal WiringDiagonal WiringDiagonal Wiringdestination

ydiagonal

xsource

Manhattan

• 20+% Interconnect length reduction• Clock speedSignal integrityPower integrity

• 15+% Smaller chips plus 30+% via reduction

© Digital Integrated Circuits2nd InterconnectCourtesy Cadence X-initiative

Using BypassesUsing Bypassesg ypg ypDriver

P l ili d liWL Polysilicon word lineWL

Metal word line

Driving a word line from both sides

Metal bypass

Polysilicon word lineWL K cells

Using a metal bypass


Reducing RCReducing RC--delaydelayReducing RCReducing RC delaydelay

Repeaterp

(chapter 5)


Repeater Insertion (Revisited)Repeater Insertion (Revisited)p ( )p ( )Taking the repeater loading into account

For a given technology and a given interconnect layer, there exists For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!




L di/dtL di/dtL di/dtL di/dtV DD

L i(t)

Impact of inductance on supply voltages:

V’DD

L i(t)

voltages:• Change in current induces a change in voltage

Longer supply lines have larger LCL

V outV in

• Longer supply lines have larger LCL

GND ’

L


L di/dt: SimulationL di/dt: Simulation1 5

2

2.5

1 5

2

2.5

0 0 5 1 1 5 20

0.5

1

1.5V ou

t(V)

0 0 5 1 1 5 20

0.5

1

1.5

0 0.5 1 1.5 2x 10-9

0.04

A)

0 0.5 1 1.5 2x 10-9

0.04Without inductorsWith inductors

0 0.5 1 1.5 20

0.02i L(A

0 0.5 1 1.5 20

0.02decoupled

x 10-9

0.5

1

(V)

x 10-9

0.5

1

With inductors

0 0.5 1 1.5 210-9

0

V L

time (nsec)0 0.5 1 1.5 2

10-9

0

time (nsec)

decoupled


x 10 9time (nsec) x 10 9time (nsec)

Input rise/fall time: 50 psec Input rise/fall time: 800 psec

Dealing with Ldi/dtDealing with Ldi/dtDealing with Ldi/dtDealing with Ldi/dtSeparate power pins for I/O pads and chip coreSeparate power pins for I/O pads and chip core.Multiple power and ground pins. Careful selection of the positions of the powerCareful selection of the positions of the power and ground pins on the package.Increase the rise and fall times of the off-chip signals to the maximum extent allowable.Schedule current-consuming transitions. U d d k i t h l iUse advanced packaging technologies.Add decoupling capacitances on the board.Add deco pling capacitances on the chipAdd decoupling capacitances on the chip.


Ch i th Ri ht PiCh i th Ri ht PiChoosing the Right PinChoosing the Right Pin


D li C itD li C itDecoupling CapacitorsDecoupling Capacitors


DeDe--coupling Capacitor Ratioscoupling Capacitor RatiosDeDe coupling Capacitor Ratioscoupling Capacitor RatiosEV4EV4

total effective switching capacitance = 12.5nF128nF of de coupling capacitance128nF of de-coupling capacitancede-coupling/switching capacitance ~ 10x

EV5EV513.9nF of switching capacitance 160nF of de-coupling capacitance160nF of de-coupling capacitance

EV634nF of effective switching capacitance34nF of effective switching capacitance320nF of de-coupling capacitance -- not enough!

© Digital Integrated Circuits2nd InterconnectSource: B. Herrick (Compaq)

EV6 DeEV6 De--coupling Capacitancecoupling CapacitanceEV6 DeEV6 De--coupling Capacitancecoupling CapacitanceDesign for ΔIdd= 25 A @ Vdd = 2.2 V, f = 600Design for ΔIdd 25 A @ Vdd 2.2 V, f 600

MHz0.32-µF of on-chip de-coupling capacitance was µ p p g padded

– Under major busses and around major gridded clock driversOccupies 15 20% of die area– Occupies 15-20% of die area

1-µF 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de-( ) g y pcoupling

– 160 Vdd/Vss bondwire pairs on the WACC minimize inductanceinductance


EV6 WACCEV6 WACCEV6 WACCEV6 WACC

389 Signal - 198 VDD/VSS Pins389 Signal Bondwiresg

395 VDD/VSS Bondwires320 VDD/VSS Bondwires

MicroprocessorWACC

G

Microprocessor

Heat Slug587 IPGA


Th T i i LiTh T i i LiThe Transmission LineThe Transmission Line

l l l lVin Vout

r

g c

r r x

g c

r

g c g c

The Wave Equation


Design Rules of ThumbDesign Rules of ThumbDesign Rules of ThumbDesign Rules of Thumb

Transmission line effects should be considered when theTransmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).g

tr (tf) << 2.5 tflightTransmission line effects should only be considered whenTransmission line effects should only be considered when the total resistance of the wire is limited:R < 5 Z0

The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic i dimpedance, R < Z0/2


Should we be worried?Should we be worried?Should we be worried?Should we be worried?

T i i li ff tTransmission line effects cause overshooting and non-monotonic behavior

Clock signals in 400 MHz IBM Microprocessor(measured using e-beam prober) [Restle98]


g p

Matched TerminationMatched TerminationMatched TerminationMatched TerminationZ

Z Z

Z 0

Z 0 Z L

Series Source Termination

Z S

Z 0 Z 0

S

0 0

Parallel Destination Termination


Segmented Matched Line DriverSegmented Matched Line DriverSegmented Matched Line DriverSegmented Matched Line Driver

I

Z0

VDDIn

Z0

s0 s1 s2 snZL

c1 c2 cnGND


Parallel Termination─Parallel Termination─T i R iT i R iTransistors as ResistorsTransistors as Resistors

V) NMOS only1.92

Mr

Vdd

PMOS only

y

1.61.71.8

Out

r

NMOS-PMOS1 21.31.41.5

Vdd Vdd

0.5

Normalized Resistance (1

PMOS with-1V bias

1.5 2 2.50

1.11

1.2Mr

Vbb

Mrp Mrn

VR (Volt)Out Out


Output Driver with Varying Output Driver with Varying T i iT i iTerminationsTerminations

Vs

Vd

Vin

1

2

3

4

VDD

1 2 3 4 5 6 7 80

1

0

1

Vin V s V d

VDD

ClampingDiodes

L = 2.5 nH

L = 2.5 nH Z 0 = 50 Ω120

Vout(V)V

Vd

Vin

2

3

4

Initial design

L= 2.5 nH

CL= 5 pF CL275

(V)

Vout( )V

s

1

0

1

Vout(V) 1 2 3 4

time (sec)

Revised design with matched driver impedance

5 6 7 80


Th “N t kTh “N t k Chi ”Chi ”The “NetworkThe “Network--onon--aa--Chip”Chip”

EmbeddedEmbedded MemoryMemoryProcessorsProcessors Sub-systemSub-system

Interconnect Backplane

AccelatorsAccelatorsConfigurableAcceleratorsConfigurableAccelerators PeripheralsPeripherals


Documents

Digggital Integrated Circuits - chungbuk.ac.krbandi.chungbuk.ac.kr/~bdyang/lecture_digital_integrated... · 2011-03-02 · Power Dissipation TrendsPower Dissipation Trends Power consumption