Dielectrically isolated saturating circuits

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-15, NO, 9, SEPTEMBER 1968 645

Dielectrically Isolated Saturating Circuits FAITH HOPE LEE, ~ M B E R , IEEE

Abstract-A description of the three main substrate preparation processes to achieve silicon dioxide dielectric isolation are described. The use of dielectric isolation for high-speed and low-power circuits is outlined, with calculations of saturation resistance and transient characteristics.

Introduction of carrier lifetime-reducing gold into a dielectrically isolated wafer can cause problems, which are delineated.

Final results are listed and photomicrographs of working circuits are presented.

H E D I F F E R E N C E S between diffused isolated monolithic integrated circuits and dielectrically isolated integrated circuits may be spelled out in

terms of the greatly diminished parasitic capacitances [ 2 ] , [SI, the tremendously increased collector-to substrate breakdown voltage [SI, and the lessened photodiode currents (at the collector-substrate junction) in radiation environments [4] of the dielectrically isolated structure. Parasitic capacitances, such as collector-to-substrate capacitance and collector-to-collector capacitance are reduced to a negligible figure because of the dielectric characteristics of the isolating silicon dioxide. The inter-island breakdown and capacitance in diffused isolation is directly a function of the epitaxy resistivity and (for high-speed circuits) may be as low as 20 volts and 0.3 pF/mi12. In dielectric isolation, breakdown is independent of resistivity (average values -1000 volts) and the capacitance is only 0.02 pF/mi12, or an order of magnitude improvement. Photodiode currents are not induced at the silicon-silicon dioxide interface, since this is not the back-to-back diode used for isolating in the diffused isolation circuit.

SUBSTRATE PREPARATION There are, of course, problems in forming the requisite

structured layers of the necessary geometry, where needed. These problems are predominantly in the form of wafer shaping [4]. It is necessary to have the wafer perfectly flat with both sides parallel to each other. The isolated area into which the active devices are placed is approximately 0.5 mil thick with a tolerance of 3 p. Any crowning or tipping of the starting layer causes severe decrease in yield.

In terms of circuit performance improvement, dielectric isolation is most effective for ultra-high-speed switching circuits, especially the high-level saturating kinds such as transistor-transistor logic, where isolation capacitance severely degrades performance.

was supported by the U. S. Army Electronics Command, Fort Mon- Manuscript received November 10,1967. A large part of the work

mouth, N. J., under Contract DA 28-043AMC-O163O(E).) The author is with Motorola Company, Semiconductor Products

Division, Phoenix, Ariz.

A distinct class of problems, however, is associated with small geometry devices in dielectrically isolated circuits. The devices we will consider are high-speed gates for use in computers. We require that the collector saturation resistance and the emitter capacitance be low, and that the amount of gold introduced into the structure be enough to reduce the lifetime of minority carriers sufficiently in both the base and collector. In a practical sense, for both types of isolation, we deal with nonideal systems, so that i t is generally not possible to introduce enough gold to get lifetimes of only a few nanoseconds without compensating the collector material, nor can we lower the collector resistivity enough to provide the low saturation resistance required without lowering breakdown voltages below operating requirements. When we form a circuit designed for high speed and usable fan-out in a diffused isolated structure, there are often differences of important consequence between this circuit and the fabrication of an identical design in a dielectrically isolated structure. This will become evident as we discuss the processes.

The trend toward dielectrically isolated circuits, and away from circuits fabricated using diffused isolation, is very strong in the areas of electronics involved in radiation hardening [SI. The increased range of radiation environments in which a dielectrically isolated circuit will continue to function (particularly when combined with thin film-passive elements) is motivation for fabricating various gates, drivers, flip-flops, and linear circuits utilizing techniques developed, while exploring the structures possible in this approach to integrated circuits [7] .

SHAPE-BACK n/IETHOD The formation of dielectrically isolated wafers can be

divided into roughly three general techniques. Two of these have been mentioned in the literature and are called shape-back and etch-out-backfill. In the first method, Fig. 1, the starting material is n type of the desired resistivity with a diffused or epitaxially grown n+ layer. After poly growth, the single-crystal starting wafer is shaped-back to within a few microns of the n+ layer.

With sufficient precision in planarizing the starting wafer and meticulous shaping, i t is possible to hold the final n-layer thickness to +_ 1 p. However, the extended period of time at high temperature, which occurs during poly growth, produces over 2 p of out-diffusion from the n+ layer. This out-diffused region may vary somewhat due to some unavoidable variations in the n+-layer doping concentration, so that a more reasonable tolerance is f 1.5 to 2 p,

646 IEEE TRANSACTIONS ON ELECTRON DEVICES, SEPTEMBER 1968

- S I 0 2 I POLY POLYCRYSTPLLINE SILICON

( 4 Fig. 1. Shape-back epic.

While n-layer thicknesses of 4 to 7 p are entirely acceptable for many circuits, other approaches were explored for small geometry devices where the saturation resistance is a direct function of excess n-layer thickness.

ETCH-OUT AND BACKFILL METHOD The etch-out and backfill method, Fig. 2 , starts with

an n+ substrate, which is channel-etched and oxidized. The poly is grown and the n+ layer reduced to a con- venient thickness of about 12 to 15 p. The surface is oxidized and appropriate apertures cut for masked-area growth of n epitaxy. A suitable quantity of n+ material is selectively etched through these apertures and the areas are then epitaxially refilled with the desired resistivity n-layer silicon. Since the apertures must often be overfilled to ensure that variation in epitaxy growth in such small regions does not leave vacancies, the wafer must then be polished back to the starting oxide and overlayed with a deposited pyrolytic oxide. All of the etching and polishing has meanwhile roughened the oxide surface and leaves an irregular aperture, which is hard to bridge, as well as mechanically damaging the surface of the working region, which affects both performance and yield.

Variations in etch rates and polish control restrict the tolerances by this process to approximately 1 0 . 5 to 0.75 p.

Because of the limitations of the previously mentioned methods, a new method of fabrication was developed wherein precision and uniformity are of domi- nant concern. This method, Fig. 3, starts with an n+ planarized and oxidized wafer, but no channels are etched.

A relatively thick polycrystalline base is grown on the n+ wafer. After poly growth, the n+ layer is brought down to 8 to 10 p and a standard (well-understood and well-controlled) epitaxy n layer of the desired thickness and resistivity is grown over the entire wafer. The wafer is then oxidized and channel-etched in the epi side, so that the channels stop at the original oxide interface between the single-crystal and polycrystalline silicon.

The edges of the channel are oxidized and the entire surface covered with only enough poly silicon to fill the channels to their original height. The wafer is then polished back to the surface oxide to remove the poly from the working areas, and a final pyrolytic oxide finishes the process, Fig. 4.

Note that the working region is epitaxially grown and immediately protected by a thermal oxide against surface damage, unlike etch-out and backfill where the working area is mechanically polished. This provides improved device characteristics and is consistent with the best practices employed in the manufacture of planar epitaxial transistors.

Because these standard techniques are thoroughly known and under good control, i t is feasible to control the epitaxial layer thickness to f0.25 p and make the layers as thin as desired. Also, from a logistics point of view, since the first polycrystalline silicon growth and the epitaxial growth are both completed before channels are etched, i t is possible to stockpile wafers in a nearly completed form, which can later be allocated to various circuits, depending on which is most needed a t any particular time. Since the channel etching is the specific process that determines which particular circuit will be fabricated, and since the channel is etched into the top side of the wafer in this third method discussed, a posi- tive mask is used for the etching, whereas in the other two methods a mirror image mask is used. For this reason, the method is called Epic P [l]. A finished substrate ready for base diffusion is shown in Fig. 5.

HIGH-SPEED GATES IN DIELECTRICALLY ISOLATED MATERIAL

High-speed saturating gates, which use very low power drain are in demand for military uses. The Army Signal Corps at Fort Inmouth, N. J. is presently inter ested in such switching gates and flip-flops for use in a field-data computer. The circuit fabricated in a dielectrically isolated medium was a T2L six-input gate. To achieve very high speed, gold must be introduced into the base and collector areas. For low power and high speed, the emitter area and, subsequently, base and collector areas must be small. Starting with the collector

LEE: DIELECTRICALLY ISOLATED SATURATING CIRCUITS 647

N+ SINGLE CRYSTAL SILICON

t f

I LPOLYCRYSIALLINE SILICON

(a)

POLY

FIRST OXIDE

I POLY I ~~

( 4 Fig. 2. Etch-out, backfill epic.

PYROLYTIC S i 0 2

LAP BACK - - - - - - - - - - - - - - N EPITAXY s i 0 2 N +

s i02

POLY

POLY

( 4 Fig. 3. Epic-P processing. (a) Starting sandwich. (b) After N epitaxy and pyrolytic oxide. (c) Channels

etched, oxidized, and poly filler deposited.

, N EPITAXY

N+ Si02

POLY SlLlCOW

Fig. 4. Epic-P processing after poly filler is polished back to first oxide and a second oxide deposited. Fig. 5. Epic-P finished substrate.

Fig. 6 . Saturation resistance path.

area, 1 to 1.5 p are needed which will be used up in oxide growth and base diffusion, 1 p to allow for the depletion layer in the resistivity chosen, and 1 p for out-diffusion of the buried layer. This gives a total epitaxial layer thickness of 3.5 to 4 p, if minimization of the collector saturation resistance is expected. Calculations for Rsat for the output transistor in a high-speed T2L gate are as follows, using Fig. 6 :

RI = d / A , (1) where p is the resistivity of the epitaxial layer, I is the distance from base to buried layer, and A , is the area of the emitter. If the n-layer resistivity is 0.3 Qscm, then

3 x 10-1 x 2 x 10-4 Iil =

4 X 10-1 X 1/(400)2 = 24 ohms. (2)

Assuming the out-diffused n+ averages 0.1 Q-cm, 10-1 x 10-4

R: = = 4 ohms. (3) 4 X 10-1 X 1/(400)2

With a substrate doped to 0.005 Q-cm, this gives a sheet resistance of 50 ohms/O/p of thickness. Even if only 5 p of n+ substrate are used, each emitter sees only 0.75 laterally to the n+ surface ring; so that the hori- zontal resistance component (E,) is only 2.5 ohms.

The second vertical component (R3) from substrate to n+ ring has the same path length as the emitter but has an area of 0.5X9.0 mil2 and contributes only 18 percent of the emitter vertical resistance (approximately 5 ohms).

Thus, Rsat total is approximately 35 ohms. Of this value, about $ is a direct function of emitter area and epi-layer thickness. For this reason, a controlled epitaxial layer is a necessity. If epi-layer resistivity is reduced to 0.2 Q.cm, Rsat can be reduced by about a, but breakdown voltages decrease by 20 percent. To increase B V C E O , a sharply graded base is needed, which dictates use of a shallow base in order to increase the slope of the diffusion curve.

Saturation resistance could also be minimized by increasing the size of the emitter area. However, this would not be compatible with the speed requirements. For a total propagation delay of 4 ns, assume that storage time must be less than 2 ns, or equal to the sum of the other time constants:

Fig. 7 . Emitter geometry.

t s = t d + tr + tf. (4) Further assume that these three time constants are equal or delay time is equal to + ns.

G f f x dV Q = I- = 2/3 ns.

1 avarnge

Now, with two transistors in series, adding delay times in quadrature allows us to compute input diode capacitance. Using an average current of 4.5 mA and a signal voltage swing of 3 volts, the capacitance of our diode inputs should be approximately 1.0 pF. Since shallow e-b junctions have a capacitance of approximately 1.5 pF/mi12, this value dictates the size of the emitter. The geometry chosen, Fig. 7, was a circular emitter 0.2 mil in radius. Six of these emitters, thus, have an area of ~ 0 . 8 mil2 and a total capacitance of 1.2 pF.

Having decided on a collector resistivity and an emitter size, there remain the processing problems of base width and profile and selective gold diffusion. For a propagation delay of 4 ns, ft should be approximately 1.5 to 2 GHz. This level of speed requires a base width in the order of 3000 A or less, using the relationship that frequency response is inversely proportional to the square of the effective base width. However, to prevent depletion layer spread in the base in order to raise the collector-to-emitter breakdown voltage, the base must be steeply graded and shallow, from 0.5 to 1 p deep.

Because of the very narrow base width and dielectric isolation, introduction of gold into the desired areas presents some special problems. We want gold in the base to kill the lifetime of carriers and also in the collector to reduce the time required for the stored charge to be depleted. The first problem was the amount of gold necessary. A permutation series of gold concentration, gold diffusion temperature and time, as well as starting p and post-gold 0 was carried out. Preliminary results on storage time versus gold diffusion temperatures are as follows:

LEE: DIELECTRICALLY ISOLATED SATURATING CIRCUITS 649

Flg. 8. Gold apertures, collector.

Temperature (C) t,(mean) (ns)

1050 25 1075 10 1100 5-7

Since t, must be reduced to less than 4 ns, a second permutation series for temperatures between 1100O and 1150C was also initiated. Thus, it was found that a temperature in excess of 1100OC is necessary to reduce storage time to the required values. Since the emitter diffusion is performed at temperatures 200 less than the gold diffusion temperature, the emitter moves rapidly during the short gold diffusion cycle. A careful adjust- ment of p at emitter diffusion is necessary to prevent a punch-through condition following gold diffusion.

Second, because the dielectric isolation masks the diffusion of gold, thus precluding the usual method of introducing gold on the back of the slice as is done with diffused isolation circuits, a method was used that intro- duces the gold through special apertures in the surface of each island. However, the n+ collector surface contact area acts as a sink for gold. For this reason, i t is necessary to place sources of gold outside the base areas so that sufficient gold would remain in the base, Fig. 8. These sources were placed just inside the collector ring. The sequence in which the gold was introduced was studied. Gold was diffused before the base, before the emitter, and after the emitter. Diffusion after the emitter diffusion and a liquid nitrogen quench was found to give the best results.

Third, gold in the pre-ohmic openings can cause severe contact problems with the aluminum metalliza- tion. Fig. 9 shows the gold openings occupying only half of the base pre-ohmic areas. Last, since the magnitude of the gold introduced and collector resistivity of 0.3 Qecm material both exceed 10l6, this amount of gold largely compensates the collector. Saturation re-

Fig. 9. Gold apertures, base.

sistance rises and a standard fan-out of 5 is difficult, if not impossible, to achieve. Lowering the epitaxial resistivity to 0.2 to 0.25 Q.cm reduces the effect of the compensating gold, thus lowering R,,,. The coincident occurrence of lower B V C E ~ is mitigated by the sharply graded base, and such compensation as occurs. Using a power supply voltage of 4 or 4.5 volts rather than 5 volts allows the use of a lower breakdown voltage device also. I t was also found necessary to lower slightly the temperature at which the gold was diffused. The average propagation delay in the actual device was less than 3 ns, so the slightly increased switching time caused by the lower gold diffusion temperature was still within the desired 4 ns.

ADDITIONAL PROBLEMS When working with dielectrically isolated circuits,

rather severe problems can arise in photoresist proce- dures unless care is taken to avoid them. During the growth of polycrystal1 silicon, spikes or spurs can de- velop, which resist removal by polishing. These tiny spikes may later project through the photoresist layer and penetrate the emulsion on the mask, scratching the mask or causing adherence of the wafer to the mask. In Epic P, the polycrystalline channel filler is polished level with the protective oxide over the single crystal region. During subsequent oxidation, this poly region oxidizes and swells while the originally oxidized region does not. This forms a step in the surface of the wafer. At subsequent photoresist steps, the resist, which must be thin enough for good definition in these small openings, can separate over the swelling causing pinholing or wide- spread etching of the isolating oxide. Fig. 10 shows the pre-ohmic openings on one die of a wafer of high-speed gates. Fig. 11 is a 5OOX magnification of the emitter pre-ohmic. With spacings and apertures in the pre- ohmic and ohmic masks of 2 to 5 p, i t can easily be seen that oxide thickness variations can prevent intimate

6.50 TEEE TRAYSACTTONS ON ELECTRON DEVICES, SEPTEMBER 1968

Fig. 10. Pre-ohmic openings. Fig. 11. Emitter pre-ohmic openings.

contact of the mask to the wafer, allowing dispersion of the exposing ultra-violet light and subsequent fringing of the openings.

Another area in which problems arise is in the scribing of the wafer. Standard diffused isolated wafers have two different layers to scribe through, the basic silicon and the silicon oxide protective layer. This oxide layer is normally etched through to the silicon before the scribe is made; the crystal then cleaves along the scribe lines. With a dielectrically isolated wafer, however, there are five distinct and separate layers, only one of which is removed prior to scribing, and all of which can cleave along their own separate planes. I t is advisable to lap the wafer down to a few mils thickness before attempt- ing to scribe it.

Assembly of ultra-small geometry units also has its own special techniques. Ultrasonic bonding is recom- mended for the following reason. The bonding pads are, of necessity, quite small to reduce excess parasitic capacitance. Fig. 12 shows the 1 mil pads with l$-mil spacing used in this circuit. Thermocompression bonding uses a needle that flattens the wire as the bond is made. Although 0.7 mil wire is used, the finished bond is 1 .2 to 1.5 mils wide. Two adjacent bonds must be perfectly placed if shorting is to be prevented. Ultrasonic bonding does not flatten out the wire.

Final results of integrating this gate in a dielectrically isolated circuit, minimizing device geometry, and using selective gold diffusion, are as follows. Using a supply voltage of 4 volts, with a fan-out of 1, the current drain - averages 4.5 mils. With the total propagation delay of 3 ns, the power-speed product is 54 pJ. The circuits measured ranged from 40 to 60 pJ. As fan-out increases, current also increases, and at a fan-out of 5 , the power- speed product rises to 90 pJ. As a comparison, the same circuit with diffused isolation has propagation delays of 5 to 7 ns and requires approximately 20 to 25 mW of power.

Fig. 12. Bonded unit.

ACKNOWLEDGMENT The author thanks U. Davidsohn and I. A. Lesk for

their help in the preparation of this paper. Logistics of circuit fabrication were largely handled by F. Whitener and I. Estreicher.

REFERENCES [l] U. S. Davidzohn, Tech. Rept. ECOM-01630-2, November 1966. [ 2 ] H. Dicken, Parasitics in integrated circuits, Electronics, vol. 36,

[3] J . Fordemwalt et al., Motorola Co. Rept., June 1965. [4] W. Price, A glass dielectric isolation technique, presented

[5] -, A Study of the Effects of S@ace Radiation, Battelle Memorial a t the 1966 IEEE G-ED Conf., Washington, D. C.

[6] -, A Study of the Effects of Space Radiation, Battelle Memorial Inst., vol. 1, September 1965.

[7] G. C. Messenger, Radiation effects on microcircuits, IEEE Inst., vol. 2 , June 22, 1965 to August 31, 1966.

[8] G. Kinoshita, C. T. Kleiner, and E. D. Johnson, Radiation in- Trans. Nuclear Science, vol. NS-13, pp. 141-159, Dxernber 1966.

duced regeneration through the P-N junction isolation in mono-

90, October 1965. lithic I/Cs, IBEE Trans. Nuclear Science, vol. NS-12, pp. 83-

pp. 32-36, July 5, 1963.

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Dielectrically isolated saturating circuits