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7/28/2019 DFT Rules.ppt 0
1/18
DFT Rule #1
All internal clocks must be controlled by port level CLK signal
(primary input) in scan test mode
Issue :
DTC10
CLK
D Q
DTC10
CLK
D Q
Gated
Clock
INPUT1
INPUT2
CLK
OUTPUT
7/28/2019 DFT Rules.ppt 0
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DFT Rule #1
Solution:
DTC10
CLK
D Q
DTC10
CLK
D QINPUT1
INPUT2
CLK
OUTPUT
MU111
A
B
TEST_MODE
Circuit Without Internal Clock Violation
7/28/2019 DFT Rules.ppt 0
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DFT Rule #2
Avoid implementation of combination feedback circuit. If present, the
feedback loop must be broken to test.
Issue:
COMBINATIONAL
LOGIC
FEEDBACK SIGNAL
INPUT
OUTPUT
The outputs of this circuit cannot be controlled by their inputs alone.
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DFT Rule #2
Solution 1:
Issue:
The gate output is not testable for stuck-at faults as it is usually held constantduring test.
The feedback signal may not be testable (observable) in test mode.
COMBINATIONAL
LOGIC
INPUTOUTPUT
TEST_MODE
Cannot
Observe
(At All)Cannot
Control
(Much)
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DFT Rule #2
Solution 2:
Solve the controllability and observability limitation at the cost of
increased complexity
COMBINATIONAL
LOGIC
INPUTOUTPUT
MU111
A
B
TEST_MODE
FF
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DFT Rule #3
Asynchronous SET/RESET pins of flip-flops must be controlled by a
port level RESET (primary input) in scan test mode
Issue :
R
D Q
CLK
Combinational
Logic OR
Test_mode
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DFT Rule #3
Solution :
R
D Q
CLK
CombinationalLogic
Test_mode
1
0
RESET from port
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DFT Rule #4
Gated clock must be enabled in scan test mode
Issue:
Gated clocks can block the scan chain from shifting
7/28/2019 DFT Rules.ppt 0
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DFT Rule #4
Gated clock must be enabled in scan test mode
Solution:
The muxed scan flip-flop observer is not required
if the HOLD signal is directly issued from a scan flip-flop.
7/28/2019 DFT Rules.ppt 0
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DFT Rule #5
Latches have to be avoided as much as possible. If present, make it
transparent in scan test mode
Issue : In an edge-triggered design, it is difficult to put latches on
a scan chain because the library does not contain their edge-
triggered scan equivalents. If they are not part of a scan chain, their
outputs will be difficult to control. The fault coverage will therefore
be very low.
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DFT Rule #5
Solution :
Process(DATA,ENABLE,TEST)
begin
if (ENABLE = 1 orTEST = 1) thenlatch_signal
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DFT Rule #6 Do not replace flip-flops of the shift register structure by equivalent scan flip-
flops.
For efficient area purposes, the flip-flops of the shift register structure will not bereplace by equivalent scan flip-flops. The SCAN_EN signal have to be addedin your VHDL RTL code of the shift register to allow the shift of scan patternsin scan mode.
Process(CLK)
beginif (CLKEVENT and CLK = 1) then
if (RESET = 1 and SCAN_EN = 0) then
shifter_bus 0);
elsif (ACTIVE_SHIFT = 1 or SCAN_EN = 1) then
shifter_bus(16 downto 1)
7/28/2019 DFT Rules.ppt 0
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DFT Rule #7 Clock should not be used as data in scan test mode
Issue: For ATPG to be successful, there should be minimal coupling between
the clocks and data. When there is any coupling between clock and data, theATPG tool will have a set of conflicting requirements to satisfy at the same
time. This results in loss of test coverage. When the clock pulses, it can create
race conditions too.
DATA_IN
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DFT Rule #7
Clock should not be used as data in scan test mode
Solution:You must change your VHDL RTL code as shown
below
CLK_TEST
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DFT Rule #8
Bypass the Memory in scan test mode
Issue:
All the paths ending at Memory cell are not observable
All the paths starting from Memory cell are not controllable
Solution:
Read Data
Memory
Address/ Control
Write Data
7/28/2019 DFT Rules.ppt 0
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DFT Rule #9
The SCAN_ENABLE signal must be buffered adequately.
Issue:
The scan enable signal that causes all flip flops in the design to beconnected to form the scan shift register, has to be fed to all flip flops in the
design. This signal will be heavily loaded.
The problem of buffering this signal is identical to that of clock buffering.
The drive strength of scan enable port on each block of the design must beset to a realistic value when the design is synthesized. If this port is left
unconstrained during synthesis, it could result in silicon failure.
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DFT Rule #10
Negative edge flops should also be triggered at the same clock edge
as positive edge triggered in scan test mode
Issue : For ATPG tool to work,in one clock cycle only one
capture/shift should happen. With negative edge flip-flops it is not
possible.
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DFT Rule #10
Solution : Invert the clock for negative edge triggered flip-flops
in scan test mode
D Q
CLK
D Q
CLK
0
1
Test_mode