DFT Course Section 1

7/31/2019 DFT Course Section 1

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PresentersPresenters

Presenters: 1. Nilanjan Mukherjee

Mentor Graphics [email protected]

2. Prof. Sudhakar ReddyUniversity of Iowa

[email protected]

3. C. P. Ravikumar

Texas Instruments, India

[email protected]


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OutlineOutline -- Day 1Day 1

Introduction (9:00 am 10:00 am)

CAD Tools (10:00 am 10:45 am)

Coffee Break

Logic Test Basics (11:00 am 12:30 pm)

Lunch

Logic Test (2:00 pm 2:30 pm)

Advanced Fault Models (2:30 pm 4:00 pm)Coffee Break

Advanced Fault Models (4:15 pm 5:00 pm)


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Power Aware Test (9:00 am 10:00 am)

DFT (10:00 am 10:45 am)

Coffee Break

DFT (11:00 am 11:15 am)

Logic BIST (11:15 am 12:30 pm)

Lunch

Logic BIST (2:00 pm 2:45 pm)

Memory Test (2:45 pm 4:00 pm)Coffee Break

Memory Test (4:15 pm 5:00 pm)


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Test Compression (9:00 am 10:30 am)

Coffee Break

Fault Diagnosis (11:00 am 12:30 pm)

Lunch

Industrial Experiences (2:00 pm 4:30 pm)


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AcknowledgementsAcknowledgements

Xioagang Du, Mentor Graphics

Dhiraj Goswami, Mentor Graphics

Ruifeng Guo, Intel

Xijiang Lin, Mentor Graphics

Srinivas Patil, Intel

Janusz Rajski, Mentor Graphics

Nagesh Tamarapalli, Mentor GraphicsNandu Tendolkar, Freescale

Jerzy Tyszer, Poznan Institute of Technology


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AcknowledgementsAcknowledgements

Sudhakar Reddy acknowledges the help of

University of Iowa graduate students Zhuo

Zhang, Santiago Remersaro, Chen Liu,

Narendra Devtaprasanna


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Introduction (9:00 am 10:00 am)

CAD Tools (10:00 am 10:45 am)

Coffee Break

Logic Test Basics (11:15 am 12:30 pm)

Lunch

Logic Test (2:00 pm 2:45 pm)

Advanced Fault Models (2:45 pm 4:00 pm)Coffee Break

Advanced Fault Models (4:30 pm 5:30 pm)


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OutlineOutline

Design Characteristics

Defects on DSM Circuits

Systematic vs. Random Defects Objectives of Digital Testing

Defect Coverage, Yield, Test Quality Functional vs. Structural Tests

Benefits of Structural Tests

Factors Affecting Test


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Nanometer DesignsNanometer Designs Test ChallengesTest Challenges

Complex SoC architectures Multiple test methods required

Embedded memory everywhere

180 nm180 nm

90 nm90 nm

Small geometries + new

materials = new defect types Resistive bridging & vias Traditional stuck-at testing

is not enough

Resistive

via

R

R = 50 KDelay of 250ps

How do you test for it?

Growing gate counts Exploding test data volume Unacceptable test application times


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Growing ComplexityGrowing Complexity -- ITRSITRS

Intel transistortechnology

evolution

G. Spirakis, Intel,ETW02

70nm

Year 2001 2004 2007 2010 2013 2016

Node [nm] 130 90 65 45 32 22

Devices [million tr.] 276 553 1106 2212 4424 8848

Voltage [V] 1.2 1.0 0.7 0.6 0.5 0.4

Oxide thickness [nm] 2.3 2.0 1.4 1.2 1.0 0.9

Static power per dev 1.00 1.96 9.46 17.32 25.00 19.64


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SystemSystem--onon--aa--Chip CharacteristicsChip Characteristics

System architecture

Microprocessors, DSP cores

Buses, peripherals, memory

ASIC portion

Structures: Logic, memory, analog

Multiple embedded memories:SRAM, DRAM, Flash, CAM

Analog and mixed signal: PLLs,clock recovery

Field programmable logic

RF cores: wireless receivers

IP cores and reusable blocksavailable from multiple vendors

Design efficiency achieved byhierarchical core-based designstyle

CPU coreCPU core

MemoryMemory

ASICASIC

ASICASIC

ASICASIC

PLLPLL

IP coreIP core

DSP coreDSP core

MemoryMemory

IP coreIP core

MemorMemoryy

MemoryMemory

MemoryMemory

ASICASIC

AnalogAnalogI / 0I / 0


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Complex InterconnectsComplex Interconnects Many FeaturesMany Features

100 million gates

400 million transistors

Billions of vias

6 km of wire / cm2

90 nm interconnects, Intel

Nigh, IBM, ITC01


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Process Shrinks vs. Defect TypesProcess Shrinks vs. Defect Types

Defect Pareto 350 nm 350 nm Process 5 million Transistors

BridgeM1-2

Bridge M2

Bridge M4

Break trans

Bridge Poly M2

Bridge M3

Bridge M1-3Bridge poly M1

Bridge M3-4

Open Poly

Open Contact

Bridge M1

Unknown Br

Break M3

Bridge Poly M2

Break M2

Bridge M3-4

Break M1Bridge Poly M4

Bridge Poly

Unknown

Via breakAl4-5 Levels

OxideDielectric

W Plugs

A Transistor


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Process Shrinks vs. Defect TypesProcess Shrinks vs. Defect Types

Defect Pareto 100 nm100 nm Process -- 250 million transistors

Unknown

A Transistor

Cu(8 Levels)

Low-KDielectric

CuPlugs

?? Defect distribution change

with process


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New Defect TypesNew Defect Types

Gelsinger, Intel, ITC 99

Resistive shorts

Nigh, IBM, ITC01

Vias

Many additional small delays

Q


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Quality RequirementsQuality Requirements

11 -- p

YY 11 -- YY

ppshipment

shipment

FaultsFaultsdetecteddetected

Escapes p

QQ li R i


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Quality RequirementsQuality Requirements

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0.990 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000 pp

Yield = 0.1Yield = 0.1

Yield = 0.9Yield = 0.9

Escapes = (1Escapes = (1 -- Y)(1Y)(1 -- p)p)

Wh i Yi ld?Wh t i Yi ld?


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What is Yield?What is Yield?

FabMetrology

Fabrication

ElectricalTest

WaferSort

AssemblyFinalTest

Hi t i l I iti l Yi ldHi t i l I iti l Yi ld11


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Historical Initial YieldHistorical Initial Yield11

0%

5%

10%

15%

20%

25%

500 250 180 130 90 65 nm

1M. Rencher and G. Allan,GDSII Yield Signoff Methods, Design for Yield, EE Times

D i RD i R ii


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Design ReDesign Re--spinsspins

Sour ce : Mark Mi l le r , eeDesign .com , 2004

0

10

20

30

4050

60

70

80

90

100

350 250 180 130 90

Technology Node (nm)

Rate(%)

First Time Design Success

Full Reticle Set Respins

Th S t ti Yi ld C i iThe S stematic Yield Crisis


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The Systematic Yield CrisisThe Systematic Yield Crisis

Target

350nm250nm130nm90nm

T f D f t i N t D iTypes of Defects in Nanometer Designs


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Types of Defects in Nanometer DesignsTypes of Defects in Nanometer Designs

Manufacturing Test RequirementsManufacturing Test Requirements


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Manufacturing Test RequirementsManufacturing Test Requirements

Feature related defects are becoming moreprevalent than particle-driven defects in

nanometer designs1

Better and more effective (Higher Quality)testing is necessary to maintain quality (or DPM)levels

1 Hsu and Chen TSMC: Scan Diagnostics in the Nanometer Design Era; Semiconductor Manufacturing, March 2006.

Yield DPM and Test QualityYield DPM and Test Quality


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Yield, DPM, and Test QualityYield, DPM, and Test Quality

DPM is a function of yield and test quality

As yield decreases, DPM increases

Highest test quality is needed just to maintain DPMlevels

Why not Functional Tests?Why not Functional Tests?


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Why not Functional Tests?Why not Functional Tests?

Functional tests are tests developed to mimic

functional behavior of the circuit Disadvantages

Requires detailed circuit knowledge

Expensive development and troubleshooting

Difficult to create high coverage patterns

Complicated failure diagnosis

Often requires high performance testers

Large inter-dependent test sets

Why Structural Tests?Why Structural Tests?


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Why Structural Tests?Why Structural Tests?

Targeted for detecting manufacturing defects inthe device

Use fault models to enable test generation

Correlates to defects

Proven in industry Predictable results

Provides high coverage tests, quickly

Can be automated and is repeatable

What is DFT?What is DFT?


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What is DFT?What is DFT?

Inserts structures inside the IC to make it easier to test

Generates test sets

Provides measures of test quality Diagnoses the cause of a failing device

Improves Product QualityImproves Product Quality


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Improves Product QualityImproves Product Quality

Test quality impacts your product quality

Assume 90% yield and 1M chips shipped/yr 99% defect coverage => 1053 defective chips are

shipped

95% defect coverage => 5254 defective chips are

shipped

Defect coverage is not just stuck-at coverage Includes coverage for all defects: at-speed, bridging,

stuck-open, etc.

Shortens TimeShortens Time--toto--MarketMarket


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Shortens TimeShortens Time--toto--MarketMarket

Time-to-market pressures

More test (e.g. at-speed)

Higher coverage

Bigger designs

Longer runtimes

DFT tools must keep pace withdesign technologies and test

methodologies Increased integration

Increased automation

Improved performance

Reduces Test CostReduces Test Cost


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Reduces Test CostReduces Test Cost

DFT reduces test set sizes

Reduces ATE memory

requirements

Reduces test time

Minimizes or eliminatestester reloads

Improves tester throughput

Test Cost

Pattern Volume

Coverage

Escapes

Tester Capacity Limit

Traditional Fault ModelsTraditional Fault Models


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Traditional Fault ModelsTraditional Fault Models

Stuck-at-0 and stuck-at-1

Transitions Path delay

VDD Iddq

IDDQ TestingIDDQ Testing


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Models high current flow through a gate

Measures quiescent power supply current during

the stable state Involves measuring current - not logic values

A

BY

1/00

0/1

P1

P2

Y1/0

N2B

A0

0

N1 VSS

VDD

Faulty transistor stuck on



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1

10

100

1000

130 90 65 45 32 22

Technology nodes

Iddq

PolySi

Silicon

PolySiPolySi

Silicon

G. Spirakis Intel, ETW02

Effectiveness of Iddq test is fading

Scan test needs to compensate

Quality is Driving ChangeQuality is Driving Change


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Quality is Driving ChangeQuality is Driving Change

At 130 nanometer and below, stuck-at test alone is not sufficient

Fabless Forum March 2003

Mentor Graphics & Nvidia - Fabless Forum, March 2003

AtAt--Speed TestSpeed Test Effect on DPMEffect on DPM


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AtAt Speed TestSpeed Test Effect on DPMEffect on DPM

LSI* experiments At .18 m 1% defects were

speed-related

At .13 m 2% defects werespeed-related

30-70% DPM reduction

w/at-speed test

Intel** claims 1-5% ofdefects are at-speedfailures

ASIC Technology DPMreduction

1 0.18m 70%

2 0.18m 59%

3 0.18m 60%

4 0.18

m 33%5 0.18m 33%

** Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICsVTS 2003.

**** Delay Defect Characteristics and Testing StrategiesIEEE Design & Test of Computers, Sept-Oct 2003.

Phases of TestPhases of Test


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Phases of Testases o est

Burn-in,Packaged Part Test

BurnBurn--in,in,Packaged Part TestPackaged Part Test

Wafer TestWafer TestWafer Test

Slice & Dice, PackageSlice & Dice, PackageSlice & Dice, Package

FabricationFabricationFabrication

Ship to CustomerShip to CustomerShip to Customer

Our focusis here

Test Program ComponentsTest Program Components


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est og a Co po e tsg p

Test programs can contain various test sets -

DC Parametric

Test logic verification DC logic stuck-at

AC frequency assessment

AC logic delay

Memory testing

Memory retention

IDDQ test

Specialty vectors

Factors Affecting TestFactors Affecting Test


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gg

ATE characteristics define DFT constraints

Examples Scan configuration

Test pattern generation

Test coverage Test application time

Cost of test

Diagnosis

ConclusionsConclusions


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Better and more effective testing is necessary tomaintain quality (or DPM) levels

Scan test and diagnostics are playing an

increasingly important role in failure analysisand yield learning

Documents

DFT Course Section 1