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Device models
Mohammad Sharifkhani
A model for manual analysis
Current-Voltage RelationsThe Deep-Submicron Era
LinearRelationship
-4
VDS (V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
Velocity Saturation
(V/µm)c = 1.5
n
(m/s
)
sat = 105
Constant mobility (slope = µ)
Constant velocity
Perspective
IDLong-channel device
Short-channel device
VDSVDSAT VGS - VT
VGS = VDD
ID versus VGS
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VGS (V)
I D (
A)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VGS (V)
I D (
A)
quadratic
quadratic
linear
Long Channel Short Channel
ID versus VDS
-4
VDS (V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS (V)
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
ResistiveSaturation
VDS = VGS - VT
Long Channel Short Channel
Unified model
Unified model
• Model presented is compact and suitable for hand analysis.
• Still have to keep in mind the main approximation: that VDSat is constant . – When is it going to cause largest errors?– When E scales – transistor stacks.
• But the model still works fairly well.
Velocity saturation
Velocity saturation
Smaller EcL Smaller VDsat Saturates quicker
Velocity saturation
Velocity saturation
Velocity saturation
Velocity Saturation
Output resistance
• Slope in I-V characteristics caused by:– Channel length modulation– Drain-induced barrier lowering (DIBL)
• Both effects increase the saturation current beyond the saturation point
• The simulations show approximately linear dependence of Ids on Vds in saturation.
Output resistance
Output resistance
Output resistance
Transistor stacks
Transistor stacks (Velocity sat.)
NAND Suffers less from VS
In NAND VDsat is larger
Velocity Saturation
• How about NAND3?– IDSat = 1/2 of inverter IDSat (instead of 1/3)
• How about PMOS networks?
• NOR2 – 1.8x, NOR3 – 2.4x, NOR4 - 3.2x
• What is ECL for PMOS?
Alpha power law
Alpha power law
• This is not a physical model• Simply empirical:
– Can fit (in minimum mean squares sense) to variety of α’s, VTh
• Need to find one with minimum square error – fitted VTh
• can be different from physical• Can also fit to α = 1• What is VTh?
Alpha power law
I-V Curves
Regular sat.
TriodeVel. Sat.
I-V curves
A PMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0-1
-0.8
-0.6
-0.4
-0.2
0x 10
-4
VDS (V)
I D (
A)
Assume all variablesnegative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
Transistor Model for Manual Analysis
The Transistor as a Switch
VGS VT
RonS D
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
The Transistor as a Switch
0.5 1 1.5 2 2.50
1
2
3
4
5
6
7x 10
5
VDD
(V)
Req
(O
hm)
The Transistor as a Switch
MOS capacitance
• The capacitance of the MOS affects the dynamic behavior of a circuit
• Speed Caps
• Proper modeling is needed
MOS Capacitance
Dynamic Behavior of MOS Transistor
DS
G
B
CGDCGS
CSB CDBCGB
The Gate Capacitance
tox
n+ n+
Cross section
L
Gate oxide
xd xd
L d
Polysilicon gate
Top view
Gate-bulkoverlap
Source
n+
Drain
n+W
Gate Cap
Gate Capacitance
S D
G
CGC
S D
G
CGC
S D
G
CGC
Cut-off Resistive Saturation
Most important regions in digital design: saturation and cut-off
Diffusion Capacitance
Bottom
Side wall
Side wallChannel
SourceND
Channel-stop implant NA1
SubstrateNA
W
xj
LS
Junction Capacitance
Capacitances in 0.25 m CMOS process
MOS Caps behavior