Development of Organic Multi Chip Package for High ...thor.inemi.org/webdownload/2014/Substrate_Pkg_WS_Apr/12...2014/04/22 · Page 1 i-NEMI Substrate & Packaging Technology Workshop

i-NEMI Substrate & Packaging Technology Workshop

Development of Organic Multi Chip

Package for High Performance

Application

Shoji Watanabe

SHINKO ELECTRIC INDUSTRIES CO., LTD.

April 22, 2014

Agenda

Introduction

Topics of Discussion

Structure

Design Study

Process flow

TV introduce

Reliability test and warpage

Thin core i-THOP

PoP Application

Conclusions

Background

Miniaturization of Electronics

( Mobile Phone, Tablet, Digital Camera etc. )

2.5D lower cost and higher yield solution,

Development the “ i-THOP” (integrated - Thin film High density Organic Package)

Miniaturization and High Functionality of Electronic Components

2.5D technology will be needed Can be assemble in narrow pitch divided high performance die,

another type die

Target application

2D 2.5D 3D

HD organic interposer

Silicon interposer

Organic substrate 10/10

8/8

5/5

3/3

2/2

1/1

Architecture

options

A : “Hybrid” high density interposer

B : “Single” high density interposer

Advantage

•Combination of known good substrate

•Relatively smaller interposer size

•No solder interconnect between layers

•Total height is reduction compare to Type A.

•Assembly is simple.

•No supply chain complexity

Organic interposer structure

Comparison of 2 candidate architectures for 2/ 2.5D

Interposer substrate architecture

Shinko recommendation :

The process of type A is needed the same dry process as option B and then, type B is not

necessary solder interconnect between layers.

Supply chain for interposer substrate

Si wafer

Foundry

interposer

Interposer suppliers

Build up substrate

Substrate suppliers

Ass’y & Test

OSAT

Middle interconnect

Substrate suppliers

Ass’y & Test

OSAT

Customer Customer

Si wafer

Foundry

Build up substrate or Interposer

Substrate suppliers

Ass’y & Test

OSAT

Customer

•Design •Qualification •Purchasing

“Type A” “Type B”

Organic interposer structure

Shinko recommendation :

There are no supply chain complexity on type B . It can be follow to conventional process.

I. Stack up structure of i-THOP

Core

Cu foil

Cu foil

Dielectric layer Electric Cu plating

Solder resist

Thin film

Layer

FL1 Cu

FL2 Cu

FL3 Cu

FL4 Pad

Electric Cu plating

Dielectric layer

The configuration of the metal layer is 4+2/2/3 layer.

This structure is the integration of a thin film interposer on the conventional Build up PWB.

Layer Material

FL4 Cu

FL3-FL4 photosenstive resin

FL3 Cu


FL2 Cu


FL1 Cu

2F-FL1 Dielectric resin

2FC Cu

1FC-2F Dielectric resin

1FC Cu

0FC-1F Dielectric resin

0FC Cu

0BC-0FC Core

0BC Cu

0BC-1B Dielectric resin

1BC Cu

1BC-2B Dielectric resin

2BC Cu

2B-3B Dielectric resin

BGA Cu

BSR Solder resist

Total thickness

Drawing image

Stack up structure (3-1/2/2)

I. Design Study ~ASIC-Wide I/O2

ASIC

Wide I/O2 Wide I/O2

Via structure Line/Space DRs

2FLS layers +1pad layer are necessary at least on ASIC-wide I/O2

Drawing image

Stack up structure (4-1/2/2)

ASIC

HBM HBM

Via structure

I. Design Study ~ASIC-HBM

FLS design

3FLS layers +1pad layer are necessary at least on ASIC-HBM

1_1 TH formation.

1_2 Cu patterning

1_3 Dielectric layer

1_4 Laser via

1_7 Dielectric layer

1_5 Resist patterning

1_6 Cu layer

Common Build up process

2_1 Laser via Cu

plating

2_2 CMP process

3_4 Photo-

sensitive resin

photo via form

3_2 Photo resist

patterning

3_3 thin Cu layer

formation

3_1 Seed layer

formation

3_5 Pad form.

Surface finish

II.. Process Flow

Planarization process

Thin film layer process

(b) Stacked φ10 μm via (a) Overall picture of TV

(c) L / S=2/2 μm trace

2.0 μm 2.0 μm 1.9 μm

II. X-section of i-THOP

The thin film layers have been formed on the conventional BU layers.

φ10um micro via and L/S = 2/2μm of fine line is made on thin film layer

Schematic of i-THOP

FL3

FL2

FL1

φ10 μm via

III. Over View the Fine Line Layer (FL3)

Die to die connected fine trace L/S=2/2 μm Cu trace

fan out

L/S=2/2μm

Cu trace is formed L/S=2/2 to 5/5 μm connected between the assuming wide I/O memory to logic.

FL3

FL2 FL1

FL4

Schematic of i-THOP

Logic IC side

Memory side

IV. Reliability Test of i-THOP

Test Conditions Out put items

Pre-

condition

MSL 3A(HTS125degC/24hr.)+

THS(60degC/60%RH/40hr.)

Reflow(260+5/-0degC x3 times)

Visual inspection

Thermal

Shock

w/ pre-condition

Condition-B

(-55 deg C~ 125deg C

100,300,500,700,1000cycles.)

Conductive resistance

For cracking bottom of micro via

Bias

HAST

w/ pre-condition

130degC/85%RH

50,100,150hr. 3.5V

Insulation resistance

For migration between the fine lines.

Reliability Test of i-THOP Sample size: 40.0 x 40.0mm x 0.8mmt

Overview of i-THOP TV

IV.. TS Test Pattern

To BGA To BGA

Stacked micro via

200μm pitch

Stagger micro via

To BGA To BGA

Stacked via Max:

887via/net

FL2

CF2

FL1

10μm

25μm

FL3

Laser via

CF2

25μm

FL2

FL1

FL3

Laser via

10μm

45μm

Stagger via Max:

1076via/net

Schematic of i-THOP

FL3

FL2 FL1

FL4

Criteria:

Via daisy Change of resistance +10 ~ -10[%]

IV.. Result of TS Test

Initial Pre-con 100cyc. 300cyc. 500cyc. 700cyc. 1000cyc.

Stagger via Pass Pass Pass Pass Pass Pass Pass

Stacked via Pass Pass Pass Pass Pass Pass Pass

There was no significant change of resistance by 1000cycle.

No delamination observed on via bottom x-sectional by SEM.

X-section of photo defined via

representative After TS 1000cyc.

IV. HAST Test Pattern

FL2 Layer

L/S=3/3μm

L/S=4/4μm

L/S=5/5μm

L/S=2/2μm To Pad (-)

To Pad(+)

1mm

FL3

FL2 FL1

FL4

Schematic of i-THOP

IV. Result of HAST

All design has kept the criteria.

Criteria:

Comb pattern Insulation resistance >100Mohm

Initial Pre-con 50hours. 100hours. 150hours.

L/S=2/2μm Pass Pass Pass Pass Pass




X-section of 2μm Cu trace

After HAST 150hr.

IV. Unit Level Warpage

The warpage is convex and 70 μm at room temperature.

Heated to maximum temperature, the warpage increased by 10 μm but was stable.

0

10

20

30

40

50

60

70

80

90

100

110

120

R.T 75 100150200230250260250230200150100 75 R.T

Co

pla

nar

ity

[μm

]

Temperature [deg.C]

#Sample_1

#Sample_2

#Sample_3

Unit: μm

R.T R.T

260degC

Scan area : 40.0mmsq.

Core thx. : 0.8mm

Temperature profile : R.T~260degC~R.T

Method : Shadow Moiré

Overview of i-THOP TV

0.8mm thickness Core

(Described presentation)



Image of i-THOP

V. Thin core i-THOP ~Over View~ For thin technology solution

Features:

Z direction of the total height is reduced.

Low warpage structure.

Minimum of Cu trace is L/S=2/2um.

V. Thin core i-THOP ~X-Section~ Core thickness 0.8mm 0.4mm 0.2mm

Structure

(Fine layer+

PWB layer)

4+2/2/3

X-section

Total height(mm) 1.2 0.780 0.580

Dynamic

Warpage(μm)

@7mmsq

11 11 12

Status Reliability test Passed

(Described presentation)

Under

Developing

Using the 0.2mm core , Total thickness could be thinner than 600μm.

In any case, warpage of die assembly area is around 10μm.

Total height Total height

Total height

0

5

10

15

20

25

30

35

40

45

50

R.T 75 100150200230250260250230200150100 75 R.T

War

pag

e [

um

]

Temperature [degC]

0.8_1

0.8_2

0.8_3

0

5

10

15

20

25

30

35

40

45

50

R.T 75 100150200230250260250230200150100 75 R.T

War

pag

e [

um

]

Temperature [degC]

0.4_1

0.4_2

0.4_3

0

5

10

15

20

25

30

35

40

45

50

R.T 75 100150200230250260250230200150100 75 R.T

War

pag

e [

um

]

Temperature [degC]

0.2_1

0.2_2

0.2_3

V. Die area warpage

Core thx.:0.2mmt

Core thx.:0.4mmt Core thx.:0.8mmt

39mm

39

mm

Measurement area

Inside white square

7mmx7mm.

Compared the warpage of core thickness.

It is stable to assuming wide I/O die area.

Dynamic range is under the 12μm over

temperature range.

Ⅵ . i-THOP PoP Application

For POP

Die 1 Die 2

Other type of Device

It can be used for Memory, logic IC, Analog IC, sensor and, optical elements and so on.

Die 1 Die 2

With MCeP®

Build-up embedded

1) We invented a novel high density package to enable multi chip

interconnect directly on a conventional organic substrate.

2) The structure and process were successfully demonstrated.

3) Reliability test result showed no failure at the TS 1000cycles

and HAST 150hr.

4) Warpage of i-THOP was stable. The temperature dependency

was small from room to reflow-temp. range.

5) For proposing the thinner package solution, we are developing

the thin core i-THOP.

Conclusions

We have developed the i-THOP as an alternative to the silicon

interposer.

Thank you for your attention.

Documents

Development of Organic Multi Chip Package for High ...thor.inemi.org/webdownload/2014/Substrate_Pkg_WS_Apr/12...2014/04/22 · Page 1 i-NEMI Substrate & Packaging Technology Workshop