Development of a robust reverse tone pattern transfer processcnt.canon.com/wp-content/uploads/2017/08/SPIE-AL-2017-tone-reversal.pdfThere have been several publications on tone reversal

Development of a Robust Reverse Tone Pattern Transfer Process

Niyaz Khusnatdinov, Gary Doyle, Douglas J. Resnick, Zhengmao Ye, and Dwayne LaBrake Canon Nanotechnologies, Inc., 18707 West Braker Lane, Austin, TX USA

Brennan Milligan, Fred Alokozai, Jerry Chen ASM America, 3440 E University Drive, Phoenix, AZ USA

Abstract

Pattern transfer is critical to any lithographic technology, and plays a significant role in defining the critical features in a device layer. As both the memory and logic roadmaps continue to advance, greater importance is placed on the scheme used to do the etching. For many critical layers, a need has developed which requires a multilayer stack to be defined in order to perform the pattern transfer.

There are many cases however, where this standard approach does not provide the best results in terms of critical dimension (CD) fidelity and CD uniformity. As an example, when defining a contact pattern, it may be advantageous to apply a bright field mask (in order to maximize the normalized inverse log slope (NILS)) over the more conventional dark field mask.

The result of applying the bright field mask in combination with positive imaging resist is to define an array of pillar patterns, which then must be converted back to holes before etching the underlying dielectric material. There have been several publications on tone reversal that is introduced in the resist process itself, but often an etch transfer process is applied to reverse the pattern tone. The purpose of this paper is to describe the use of a three layer reverse tone process (RTP) that is capable of reversing the tone of every printed feature type. The process utilizes a resist pattern, a hardmask layer and an additional protection layer. The three layer approach overcomes issues encountered when using a single masking layer. Successful tone reversal was demonstrated both on 300mm wafers and imprint masks, including the largest features in the pattern, with dimensions as great as 60 microns. Initial in-field CD uniformity is promising. CDs shifted by about 2.6nm and no change was observed in either LER or LWR. Follow-up work is required to statistically qualify in-field CDU and also understand both across wafer uniformity and feature linearity. Keywords: Nanoimprint lithography, reverse tone process, RTP, Atomic layer deposition, ALD, PE-ALD

1. Introduction Pattern transfer is critical to any lithographic technology, and plays a significant role in defining the critical features

in a device layer. As both the memory and logic roadmaps continue to advance, greater importance is placed on the scheme used to do the etching. For many critical layers, a need has developed which requires a multilayer stack to be defined in order to perform the pattern transfer.1-3 A typical multilayer stack consists of a bottom carbon-based film, such as a spin-on carbon (SOC), followed by a hardmask, such as a spin-on-glass (SOG) and the imaging resist.

In the process sequence, the resist pattern is used as an etch mask for the SOG, and the SOG then serves as the mask for the bottom SOC film. The SOC and remaining hardmask are then used to pattern the underlying substrate material.

There are many cases however, where this standard approach does not provide the best results in terms of critical dimension (CD) fidelity and CD uniformity. As an example, when defining a contact pattern, it may be advantageous to apply a bright field mask (in order to maximize the normalized inverse log slope (NILS)) over the more conventional dark field mask.4 The result of applying the bright field mask in combination with positive imaging resist is to define an array of pillar patterns, which then must be converted back to holes before etching the underlying dielectric material.

In the application of nanoimprint lithography (NIL), there is the possibility that the existing residual layer beneath the imprinted features will have some measure of non-uniformity, which when removed, causes an additional CDU error. As a second example, NIL requires the use of replica mask fabricated from an existing master mask. High resolution positive tone electron beam resists currently are used for most imprint levels, and if there is a requirement to

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maintain the same tone of the master mask, then either the master mask must be replicated twice, or a reverse tone process (RTP) must be applied.

There have been several publications on tone reversal that is introduced in the resist process itself, but often an etch transfer process is applied to reverse the pattern tone.5-8 An example of a typical RTP is illustrated in Figure 1. In this figure, the resist pattern is over coated with a hardmask such as an SOG material. The hardmask is etched back to expose the tops of the resist features and the tone is reversed by selectively removing the resist. The remaining SOG material then serves as the etch mask for any underlying layers.

Figure 1. Reverse tone process using a hardmask overcoat and etch back sequence. Larger features are not

successfully tone reversed.

This approach is typically effective for small features or dense arrays of critical features where the SOG overcoat is

effective in planarizing the original resist pattern. However, the process has the potential to breakdown, in particular in areas such as large gaps or transition regions, where the spin-on films conformally cover the features. In these areas, either there will be no tone reversal or critical dimensions will be impacted.

The purpose of this paper is to describe the use of a three layer RTP that is capable of reversing the tone of every printed feature type. Section 2 of the paper describes the three layer RTP approach and the processes necessary to execute the approach. Section 3 presents two applications of the process. Conclusions and next steps are then described.

Resist features

Small features Large features

Etch mask planarization layer not ideal

Substrate

Etch back of planarization layer.Substrate

transient features are over etched

Resist etch accompanied by feature loss

Substrate

larger CDs of transient features



2. RTP Approach and Process Development

a. Three Layer RTP Approach The three layer RTP approach adopted for this work is shown schematically in Figure 2. Figure 2a depicts the

deposition of a thin conformal dielectric layer, such as an atomic layer deposited (ALD) oxide film, over the imaging resist, followed by the deposition of an organic protection layer, such as an SOC film. In Figure 2b, the protection layer is selectively etched back, thereby exposing the oxide layer in dense patterned areas where the SOC tends to planarize reasonably well, but remaining in areas where there are large gaps between features. In Figure 2c, the oxide is selectively removed, exposing the printed resist in densely patterned areas, while maintaining the deposited ALD film around the large features. Finally, as shown in Figure 2d, the original resist is selectively removed, effectively reversing the tone of the initial pattern.

Figure 2. A three layer RTP flow that is capable of reversing the tone of all feature types.

To develop an effective process, it was necessary to:

• Develop an ALD deposition process compatible with the printed resist

Resist featuresResist or SOC protection layer (PL) for oxide

ALD SiO2 (oxide)

Resist residual layerSubstrate

2. Protection layer etch back

3. ALD oxide etch. The bottom oxide is protected.

4. Etching of the patterned resist

transient features are preservedBack etch with selectivity PRL/oxide, ξ1 .

Oxide etch with selectivity oxide/PRL, ξ2 .

Transfer resist etch with selectivity resist/oxide, ξ3 .

1. ALD oxide and protection layer deposition



• Understand the etch selectivity of the various etch processes required to optimize CDU and maintain the protection layer during the etch back steps

• Develop the etch processes These topics are the subject of the next three sections in the paper.

b. Atomic Layer Deposition of the oxide film For all experiments, the printed resist used was an acrylate based imprint resist using a nanoimprint process previously described.9-19 For work done on 300mm silicon wafers, an Imprio 450 system was applied. For mask applications, an MR5000 alpha tool was employed. An ASM EmerALDTM single wafer PEALD process module was used for all oxide deposition work.20-21 The choice of a plasma enhanced process was dictated by the need to minimize the temperature of the wafer surface, so as not to exceed the glass transition temperature of the resist. The EmerALDTM reactor employs a capacitively-coupled direct plasma with a showerhead and enhanced precursor delivery system. The PE-ALD SiO2 process was developed with low plasma power and low temperature. Spectroscopic ellipsometry was used to measure SiO2 film thickness, uniformity, and refractive index inline. Figure 3 shows the first attempt at deposition over dense 30nm resist features. It is clear that the deposited 20nm oxide film impacted the resist height, width and profile. In fact, feature height was decreased by about 10nm, resist width changed by almost 13nm and the sidewall slope degraded from 84o down to 77o. The likely cause of the shift was the initial un-optimized plasma power and duration in the PE-ALD SiO2 process. As a result, a short DOE was run in which these parameters were varied in order to further optimize and fine-tune the PE-ALD SiO2 process.

a b Figure 3. a) 30nm printed resist features. b) Impact of the PE-ALD process on resist height, width and sidewall slope. The red line highlights the resultant change in height, width and sidewall slope. The DOE matrix applied shorter duration times and plasma power as shown in Figure 4a. The results of the matrix experiments are reported in Figure 4b. It should be noted that for all conditions tested, the impact of the oxide refractive index and deposition uniformity were minimal.

Figure 4. a) PE-ALD design of experiments. b) Resulting CD and sidewall slope after PE-ALD

Original 30nm resist features. Resist features under 20 nm ALD.

Plasma Time

BKM-- BKM- BKM

Pow

er

BKM-- 2x

BKM- 1x 1x 1x

BKM 2x 1x 2x

lowest

low

standard

lowest low standard

23.16 ± 2.6

82.52+3.40

22.59 ± 1.0

84.45+3.38

25.13 ± 3.1

81.82+6.75

21.76 ± 1.1

81.33+1.88

Process choice

CD

Sidewallslope

lowest

low

standard

lowest low standard

DOE CD and sidewall slope



20152365 St

rTT = 5.

Best results were obtained in the cell in which plasma power was lowered and plasma time was set to the minimum time in the DOE. The initial resist CD and sidewall slope before oxide deposition was 26.4nm and 82.4o, respectively. The resultant change in resist height, CD and sidewall slope after deposition was 22.6nm and 84.5o. Resist feature height changed by only 6nm. The change in CD was considered small enough to proceed to the development of the pattern transfer process. The resist profile before and after deposition is shown below in Figure 5.

a b Figure 5. a) 30nm printed resist features. b) Impact of the PE-ALD process on resist height, width and sidewall slope, using an optimized PE-ALD deposition process. Changes to the original resist profile were minimal, as indicated by the red line.

c. CDU analysis and etch selectivity

To better understand what level of etch selectivity was required during pattern transfer, a simple model was developed which takes into account the protection layer uniformity, residual layer uniformity, resist sidewall profile, profile uniformity, resist feature height and etch selectivity of the final resist. Etch chamber uniformity was not included, as the purpose of the model was to understand the requirements for etch selectivity. The results are shown in the equations below.

Figure 6. Layer stack before and after etch back and pattern transfer.

Imprint

Imprint planarization

ALD SiO2

Imprint

(power, RF time) = (low, lowest)

Resist Resist + SiO2 ALD layer

θ

substrate

CD0

HM

resist

PL ∑=

⋅=N

iic

NCD

1

1

( ) ( )∑∑==

⋅⋅=−⋅⋅=N

ii

N

ii dc

NcCD

NCDU

1

2

1

2 1313

resist

CD1



4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

CDU1

PLUt

CDUO

CDU1 and some of its components

Out

0 2 4 6 8 10 12

Etch selectivity, 1

PLU=20nmCDUO =1 nm

FHU = 2 nm

FH=38nm

8=85°,8U=1°

( )( )

( )( ) ( )

( )( )2

2

30

3

34

22

21

2

22

2

3

32

20

21

1tan

)(tan14tan

41tan

4 UrlthhhPLUFHUCDUCDU HMf θξξ

ξθθ

ξθξξ

θ ⎟⎟⎠

⎞⎜⎜⎝

⎛+−−

++++⎟⎟

⎠

⎞⎜⎜⎝

⎛ ++=

To better understand their influence on CDU, the following assumptions for the starting protection layer, uniformity (PLU), resist feature height uniformity (FHU), feature height (FH), resist sidewall angle (θ) and resist sidewall angle uniformity (θU) were made:

The resulting impact on CDU sensitivity as a function of the resist etch selectivity, is plotted below in Figure 7. The main contributor to the final CDU, CDU1, was the first term involving the final resist etch selectivity, ξ 1. From the graph, it is apparent that as the selectivity approaches a value of 10:1, the term’s impact on final CDU becomes almost negligible. As a result, minimum values of 10:1 were targeted during the etch development process.

Figure 7: CD uniformity for the three layer etch process as a function of etch selectivity, ξ1.

d. CDU analysis and etch selectivity

All wafer etch development work was done in a single chamber Lam 2300 Exelan Flex 45 300mm etch tool located at the University of Texas, Austin. For demonstration purposes, a bottom layer of 100nm thick SOC was deposited prior to imprinting the resist pattern. A 20nm PE-ALD SiO2 hardmask and 100nm SOC protection layer were applied over the resist. The results of the development work are described in Table 1. Using an O2/Ar gas chemistry, the selectivity of the protection layer relative to the SiO2 hardmask greatly exceeded the target of 10:1. Similarly, the etch selectivity of the resist/SOC combination relative to the hardmask was 15:1. In this case the gas chemistry consisted of a mixture of hydrogen and nitrogen in order to achieve good anisotropy during the etching of the SOC film. During the etch back of the SiO2 layer, a selectivity to the SOC of 6.7:1 was achieved. While this selectivity does not impact CDU, it does



play an important role in the maintenance of the protection layer over the large feature gaps, as shown in Figure 2. In this work, a planarization efficiency of only 35% was required for the larger features, such as 60 µm x 60 µm squares. Etch Step Gas Chemistry Etch Selectivity

Protection layer etch back O2 and Argon 37:1

ALD SiO2 etch CHF3 and Argon 6.7:1

Resist/SOC etch Hydrogen and Nitrogen 15:1

Table 1. Etch step, gas chemistry and the resultant etch selectivity.

3. RTP Results

a. RTP Results on a 300mm silicon wafer For test purposes, four feature types were monitored: 22nm half pitch lines, 50nm half pitch lines, logic-like features located adjacent to 120nm pitch lines and large open area metrology features located next to 120nm pitch lines. These features, prior to any subsequent processing are shown below in Figure 8.

Figure 8. Imprinted resist with feature sizes ranging from 22nm up to 35 microns.

22nm half pitch

Archer markLogic-type features

50nm half pitch



The resutone reversaachieved forsection as sh

Figur

ultant features al was achiever these featureshown in Figure

re 9. The same

Figure

after the RTP ed. Note that ins as well as the10. Pictured a

features after t

10. Final featu

etch sequencen the case of e adjacent 120

are the profiles

the RTP etch s

ure profile after

are shown in the larger log

0nm pitch linesfor both the 22

sequence. Tone

r etch for the 2

Figure 9. For agic-like and mes. Feature prof2nm and 50nm

e reversal was a

22nm and 50nm

all feature typeetrology featurfile was also v

m half pitch line

achieved for al

m half pitch lin

es, a successfulres, tone revererified by SEMes.

ll feature types

es.

l pattern rsal was M cross-

s.



Preliminary work was also started to understand the resultant CDU after pattern transfer. Four locations within an imprint field were measured for the 22nm half pitch features and the results are shown in Table 2. There was a shift of about 2.6nm in final feature size. However, the CDU, LER and LWR remain largely unaffected. More work is required to statistically qualify in-field CDU and also understand both across wafer uniformity and feature linearity.

Features Resist 22 nm HP: space measurement RTP 22 nm HP: line measurement

Parameters Loc 1 Loc 2 Loc 3 Loc 4 Average Loc 5 Loc 6 Loc 7 Loc 8 Average

CD, nm 18.1 17.27 18.19 17.05 17.65 20.11 19.23 20.69 21.09 20.28

CDU, 3|σ|, nm 1.95 2.1 1.35 1.86 1.82 2.31 1.77 1.71 1.62 1.85

LWR, 3|σ|, nm 4.32 3.85 3.67 4.01 3.96 4.06 3.66 3.63 3.98 3.83

LER, 3|σ|, nm 3.11 2.95 2.59 3.11 2.94 3.07 2.65 2.54 2.56 2.71

Table 2. CDU, LER and LWR before and after etch.

b. RTP Results on am imprint replica mask

As previously described, a single replication step is preferred during the manufacturing of an imprint replica mask, and there may be cases when it is not possible to correctly define the tone on the electron beam written master mask. In this case, an RTP process is required to maintain the same mask tone between master and replica. The standard etch process typically includes a pattern transfer into both a thin chromium and the underlying fused silica. As a result, test samples were prepared in which a 20nm PE-ALD SiO2 film was applied over the imprint resist. Because the replica mask blank already has a mesa, it is not possible to use a spin-on SOC film as the protection layer because of the resultant defects caused during the spin process at the edges and corners of the mesa. Instead, an imprinted resist is applied over the SiO2 coated pattern. Because the initial topography of the imprinted pattern is well understood, it is possible to create a drop pattern that anticipates the underlying topography, thereby creating a protection layer that is essentially planar across all feature types. This process is typically referred to as Inkjet-based Adaptive planarization or IAP.22 For this work, patterns like 19 nm half pitch lines, various other line/space patterns with varying pitches, and larger metrology marks were investigated. Figure 11 depicts the sequence from the imprinted feature (Figure 11a), to the deposition of the SiO2 and protection layer (Figure 11b) to the RTP etch into to the fused silica (Figure 11c). Again, tone reversal was achieved. The tops of the etched features appear rounded, mainly because some of the chromium hardmask is still in place.

a b c

Figure 11. RTP process for 19nm half pitch lines demonstrated on an imprint replica mask.

19nm HP imprint pattern ALD and Protection Layer RTP and etch into Cr and Glass



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As in the 300mm wafer case, all feature types studied were successfully tone reversed. Shown below in Figure 12 in the top row are transition areas in which pitch and feature size vary. In the bottom row, a 50 micron box-in-box alignment mark located adjacent to both logic-like features and 120nm pitch lines is shown before and after RTP.

Figure 12. Top row: Transition region, before and after etch, in which both feature size and pitch are changed. Bottom

row: Alignment mark, before and after the RTP etch sequence.

Conclusions

A reverse tone process (RTP) utilizing a highly conformal and uniform in thickness ALD hardmask layer and protection layer was demonstrated. The two masking layer approach overcomes issues encountered when using a single masking layer. Demonstrations on two different substrate types and two different material stacks were presented. The wafer case used a spin-on carbon protection layer. In the mask case, an inkjet-based adaptive planarization (IAP) process was used to form the protection layer. Successful tone reversal was demonstrated for each case, including the largest features in the pattern, with dimensions as great as 60 microns. For gaps greater than 60 microns, it is possible that the SOC protection layer may not provide even the minimal amount of planarization needed to preserve the SiO2 hardmask, and the IAP approach provides a means for overcoming this potential restriction. Initial in-field CD uniformity is promising. CDs shifted by about 2.6nm and no change was observed in either LER or LWR. Follow-up work is required to statistically qualify in-field CDU and also understand both across wafer uniformity and feature linearity.

Resist RTP into Glass

Box-in-Box Align The same box-in-box AM after RTP

50 µm

30nm line 120nm pitch

19nm HP

After RTP

30nm line 120nm pitch

200nm pitch

After RTP

RTP into Glass



Acknowledgments The authors gratefully acknowledge the support of Chris Jones and Andy Eckert from Canon Nanotechnologies

Inc., and Chris Moldenhauer from ASM.

References

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Documents

Development of a robust reverse tone pattern transfer processcnt.canon.com/wp-content/uploads/2017/08/SPIE-AL-2017-tone-reversal.pdfThere have been several publications on tone reversal