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Swiss Federal Institute of Technology, Lausanne Microelectronic Systems Laboratory Master Thesis Developing a Standard Cell Library for Sub-

threshold Source-Coupled Logic Student: Mohammad BEIKAHMADI Professor: Yusuf Leblebici Project Supervisors: Armin Tajalli Stéphane Badel January 2009

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ACKNOWLEDGMENTS I am grateful to many people who supported and encouraged me during the work leading to this master project. I would like to specially thank Prof. Y. Leblebici, the director of Microelectronic Systems Laboratory (LSM), for his extensive support during master study and guiding me to select worthwhile research topics for both semester and master projects. I am grateful to him and to other professors and colleagues at LSM for providing an enjoyable environment. Special thank goes to Mr. Tajalli and Mr. Badel for guiding me through all stages of the project. I really appreciate their help and invaluable advices. Finally, I would like to thank my family for their interest and never-ending support during my studies.

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ABSTRACT Power consumption is one of the main concerns in design of modern integrated circuits. The trend for implementing the required functionality using digital circuits has made the design of ultra-low power logic circuits very desirable. Sub-threshold Source-Coupled Logic (STSCL) technique is a novel method that could be used to design ultra-low power circuits operating in sub-threshold regime. In this technique, the load and the source-coupled nMOS transistors are biased in Weak Inversion (WI). The circuits designed using the STSCL technique can operate over a wide range of frequency. An interesting advantage of this technique is that the speed and power consumption of such circuits can be simply adjusted by altering the bias current of the gates without the need to resize the devices. In fact, as long as the nMOS devices remain in WI, logic evaluation will be performed correctly. In this work, design and characterization of a standard cell library for the STSCL circuits is presented. As the existing tools cannot handle the circuits with differential input/output ports, a unique method is employed to create so called fat cells out of the STSCL cells. These cells are treated exactly like their CMOS counterparts by the tools. When placement and routing of a design is finished, the fat wires are splitted into differential ones and the fat cells are replaced by corresponding cells with differential input/output ports. An FIR filter, as a demonstration circuit, is finally synthesized and implemented using the STSCL library cells to show the capabilities of the mentioned technique.

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CONTENTS CHAPTER 1 Introduction ............................................................................................................................................... 8 1.1 Motivation ............................................................................................................................................................... 8 1.2 Thesis Organization ............................................................................................................................................. 9 CHAPTER 2 Sub-threshold Source-Coupled Logic Circuits .......................................................................... 10 2.1 SCL Circuits .......................................................................................................................................................... 10 2.2 Sub-threshold SCL Circuits ............................................................................................................................ 12 CHAPTER 3 STSCL Standard Cell Library ............................................................................................................ 14 3.1 What is a Standard Cell? ................................................................................................................................. 14 3.2 Approaches in Integrated Circuit Design ................................................................................................ 15 3.3 Library Specifications ...................................................................................................................................... 16 3.4 Drawing Layout Strategies ............................................................................................................................ 17 3.4.1 Routing Grids and Differential Pins ................................................................................................... 18 3.4.2 Power, Ground and Bias Rails.............................................................................................................. 19 3.5 STSCL Buffer/Inverter .................................................................................................................................... 20 3.5.1 Schematic and Layout ............................................................................................................................. 21 3.5.2 Characteristics ........................................................................................................................................... 21 3.6 Bias Circuit Preparation ................................................................................................................................. 25 3.6.1 Amplifier Design ........................................................................................................................................ 27 3.6.2 Bias Current Generator .......................................................................................................................... 27 CHAPTER 4 Library Cell Creation ........................................................................................................................... 30 4.1 Template Generation ....................................................................................................................................... 30 4.2 Fat Library Creation ......................................................................................................................................... 31 4.3 LEF File Generation .......................................................................................................................................... 32 4.4 Library Characterization ................................................................................................................................ 33 CHAPTER 5 Sub-threshold Source Coupled Logic Test Circuit .................................................................. 35 5.1 FIR Filter Structure ........................................................................................................................................... 35 5.2 Test Circuit Structure ...................................................................................................................................... 36 5.3 Synthesis of the Filter ...................................................................................................................................... 38 5.4 Placement and Routing ................................................................................................................................... 42 5.5 Simulation Results ............................................................................................................................................ 45 CHAPTER 6 Conclusions ............................................................................................................................................. 48 APPENDIX A Developed STSCL Library Cells ..................................................................................................... 50 AND2_x1 .................................................................................................................................................................. 51

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AND3_x1 .................................................................................................................................................................. 52 Latch_x1 ................................................................................................................................................................... 53 XOR2_x1 ................................................................................................................................................................... 54 XOR3_x1 ................................................................................................................................................................... 55 MUX2_x1 .................................................................................................................................................................. 56 HA_x1 ........................................................................................................................................................................ 57 FA_x1 ......................................................................................................................................................................... 58 DFF_x1 ...................................................................................................................................................................... 59 DFF_ARESET_x1.................................................................................................................................................... 60 APPENDIX B STSCL Library Cell Creation Procedure .................................................................................... 61 APPENDIX C FIR Filter VHDL Model and Test Bench ..................................................................................... 64 VHDL Behavior .......................................................................................................................................................... 64 Test Bench for the Filter ........................................................................................................................................ 70 APPENDIX D Synthesis Scripts ................................................................................................................................. 73 Contraints File ............................................................................................................................................................ 73 Script for Synthesizing the FIR Filter Using the STSCL Cell Library .................................................... 75 Script for Synthesizing the FIR Filter Using the Standard CMOS Library .......................................... 80 APPENDIX E Placement and Routing Script ....................................................................................................... 81 APPENDIX F Verilog-A Code for Converting the Analog Outputs of the STSCL Test Circuit into Digital Hexadecimal Code .......................................................................................................................................... 88

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LIST OF FIGURES Figure 2-1: General topology of Source-Coupled Logic circuits ................................................................. 12 Figure 2-2: Schematic of a buffer/inverter designed using the STSCL technique ............................... 12 Figure 2-3: Replica bias circuit for generating the bias voltage of the load devices [2] ................... 13 Figure 3-1: The template for placing the differential and fat pins with respect to routing grids . 19 Figure 3-2: The template of the designed cell with power, ground and bias rails .............................. 20 Figure 3-3: The schematics of the Buffer gates with driving strength of (a) 1, (b) 2, (c) 4, (d) 8 and (e) 16 ........................................................................................................................................................................... 22 Figure 3-4: The layouts of the buffers with driving strength of (a) 1, (b) 2, (c) 4, (d) 8 and (e) 16 ................................................................................................................................................................................................ 23 Figure 3-5: Schematic of the amplifier in the replica bias circuit. All the dimensions are in micro meter .................................................................................................................................................................................... 25 Figure 3-6: (a) Total gain of the amplifier and the pMOS load device and (b) corresponding phase in degrees for various bias current of the load device ...................................................................... 26 Figure 3-7: Schematic of the bias current generator for the replica bias circuit ................................. 28 Figure 4-1: Footprints of 1-2 levels networks ................................................................................................... 31 Figure 5-1: Signal flow graph of an FIR filter with N=M+1 taps ................................................................. 35 Figure 5-2: FIR filter (a) Frequency Response and (b) Phase Response ................................................. 37 Figure 5-3: FIR filter (a) Step Response and (b) Impulse Response ......................................................... 37 Figure 5-4: Pre-synthesis simulation results of the FIR filter ...................................................................... 37 Figure 5-5: Post-synthesis simulation results of the (a) STSCL and (b) CMOS test circuit ............. 41 Figure 5-6: The placed design and the power and bias rings ....................................................................... 43 Figure 5-7: Layout view of the implemented FIR filter .................................................................................. 44 Figure 5-8: Post-Layout simulation results of the implemented FIR filter; the outputs which are not presented are at logic ‘0’ ...................................................................................................................................... 46 Figure 5-9: Verilog simulation results of the implemented FIR filter ....................................................... 47 Figure 5-10: The current drawn from the power supply rails of the STSCL test circuit ................... 47

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LIST OF TABLES Table 3-1. Driving strength and bias current correspondence ................................................................... 17 Table 3-2. Propagation delay of the buffers for various bias currents (μs) ........................................... 24 Table 3-3. Rising transition time of the buffers for various bias currents (μs) .................................... 24 Table 3-4. Falling transition time of the buffers for various bias currents (μs) ................................... 24 Table 3-5. Simulated relative error in the output of the bias current generator in percent for various corners at a temperature of 50 ˚C ........................................................................................................... 29 Table 5-1. FIR filter specifications ........................................................................................................................... 37 Table 5-2. Reference cells of the test circuit synthesized using developed STSCL library .............. 39 Table 5-3. Reference cells of the test circuit synthesized using standard CMOS technology ......... 40 Table 5-4. General design information for the routed single ended and differential circuits ........ 45

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CHAPTER 1 INTRODUCTION MOS Current Mode Logic (MCML) or Source-Coupled Logic (SCL) circuits are of great interest for designing high speed mixed-signal circuits. These circuits benefit from immunity to noise and crosstalk, low swing voltage and insensitivity to process variations because of differential operation [1]. Unfortunately, designing ultra-low power circuits using the traditional SCL circuits seems challenging. The problem with conventional SCL circuits is that for extremely low bias current, the load resistance becomes huge to achieve the same swing at the output node which makes them unattractive for low power applications. Nevertheless, a novel technique is proposed in [2] for designing SCL circuits in sub-threshold regime which is one of the most power efficient regions for ultra-low power applications. In this proposed technique, the PMOS load device is biased in weak inversion and the bulk terminal of the device is connected to the drain. This will result in a finite large equivalent resistance instead of almost infinite output impedance of conventional PMOS devices [2]. 1.1 MOTIVATION Nowadays, various tools are available to accelerate and automate the process of constructing digital circuits using the standard CMOS technology. Contrary to the CMOS circuits, no CAD tool is currently available for the synthesis and Place and Route (P&R) of the SCL circuits with differential input/output ports. Besides, integrity of differential signals is an important issue in dealing with SCL circuits. In [3], a method is presented to use existing CAD tools for the synthesis and P&R of MCML circuits. The key point in dealing with these circuits is that although the information is carried by differential signals, but the designer does not need to consider the differential nature of the signals unless when physical tasks are concerned. In fact, the differential signals can be replaced by one signal from the logic point of view [3].

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In this thesis, a STSCL cell library is designed using standard 0.18 μm CMOS technology. The method presented in [3] is then applied to the STSCL library to generate a library which can be used by existing tools to construct STSCL circuits. 1.2 THESIS ORGANIZATION The thesis is organized as follows. Chapter 2 introduces basic structure of the SCL circuits and then discusses design of ultra-low power Sub-threshold SCL circuits. Chapter 3 is dedicated to the STSCL cell library design which discusses the specifications of the library, designing a STSCL library cell and preparing the bias circuit. Design of a simple Buffer/Inverter gate is discussed in detail in this chapter to show how a STSCL library cell is created. Chapter 4 discusses creating and characterization of the library cells and then generating the required files out of the cells which will be used by the tools during synthesis and place and route of a circuit using the STSCL technique. Design, synthesis and placement and routing of a Finite Impulse Response (FIR) filter as a demonstration circuit using both the designed cell library and standard CMOS library is discussed in Chapter 5. The simulation results of the filter are also presented in this chapter. Finally, the conclusions are given in Chapter 6. 2.

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CHAPTER 2 SUB-THRESHOLD SOURCE-COUPLED LOGIC CIRCUITS This chapter introduces the topology of Source-Coupled Logic circuits and their characteristics as well. Then the advantages and drawbacks of these circuits is mentioned. Finally, the architecture of Sub-threshold SCL circuits which are operating with extremely low bias current is discussed. 2.1 SCL CIRCUITS MCML or SCL circuits consist of a constant current source, one (or multiple) source-coupled nMOS pair(s) and the loads. Figure 2.1 shows the general topology of these types of circuits. The differential pair switches the constant current between two branches and the load converts the current to voltage. The speed of switching can be very high and is proportional to the amount of the bias current. The signal level in SCL circuits is either VDD (logic ‘1’) or VDD-∆V (logic ‘0’) where ∆V is the swing voltage at the output. The swing voltage at the output is given by: (2-1) where RL is the load resistance and Iss the bias current of the gate. Note that the output voltage swing should be large enough otherwise the differential pairs of the next stage cannot completely switch the current. The SCL circuits draw a constant DC current from the power supply even when the gates are in the idle mode but sometimes this constant current is desirable. The DC current ensures that there are no sudden bursts of current in the supply and ground rails to cause switching effects [4]. Because of differential operation, the SCL circuits

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benefit from low output signal swing (and hence small dynamic power dissipation), fast switching speed, and low sensitivity to supply and substrate noise. In contrast to CMOS circuits, the power consumption of SCL circuits is fixed and independent of the clock frequency: (2-2) The time constant at the output node of each SCL gate is: (2-3)

where CL is the total capacitance at the output node. Using equation (2-3), the gate delay of SCL circuits is roughly estimated as 2 . The power-delay product which is important factor in evaluating the performance of each logic circuit is then calculated using: 2 (2-4) One drawback of SCL circuits is that when the bias current is decreased, the load resistance should be increased to have the same voltage swing at the output while implementing large on chip load resistance is difficult. The load device proposed in [2] overcomes this problem for very low bias currents. High design complexity and lack of proper EDA tools are the other drawbacks of designing circuits using the SCL technique [3]. In the next section, general topology of sub-threshold SCL circuits which are biased with extremely low bias currents is discussed.

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Figure 2-1: General topology of Source-Coupled Logic circuits

Figure 2-2: Schematic of a buffer/inverter designed using the STSCL technique 2.2 SUB-THRESHOLD SCL CIRCUITS In Sub-Threshold SCL (STSCL) circuits, the load is a pMOS transistor where the bulk terminal is connected to the drain. This device is biased in WI and provides a large equivalent resistance [2]. In addition to the load devices, the source-coupled nMOS

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differential pairs are also biased in Weak Inversion (WI). The logic evaluation in STSCL circuits will be performed correctly if the swing voltage is larger than about 4×nUT where n is the sub-threshold slope factor for nMOS devices and UT the thermal voltage. The schematic of a buffer/inverter designed using the STSCL technique is shown in Figure 2-2. The bias current (ISS) is chosen based on the trade off between the power consumption and the speed of the circuit. An nMOS device which is biased in strong inversion provides this current. The bias current can be simply altered by adjusting the bias voltage of the nMOS device (VBN). An advantage of designing circuits using the STSCL technique is that these circuits can operate over a wide range of bias current. When the bias current is altered, all nMOS devices which switch the current should remain in WI for proper operation. Based on the EKV model [5], the dimensions of the nMOS devices is determined by: , / 2 . . . . (2-5) where μn is the carrier mobility, Cox the gate oxide capacitance per unit area and IC the device inversion coefficient. After choosing an appropriate value for the bias current, the bias voltage of the pMOS devices (VBP) must be fixed to provide the desired swing voltage at the output. A replica bias circuit can be used for this purpose which enables the circuit to operate with different bias currents. An example of a replica bias circuit is shown in Figure 2-3 [2]. The amplifier in the replica bias circuit compares the reference voltage with the drain voltage of the load transistor and adjusts the bias voltage of the device such that the desired output swing is achieved.

Figure 2-3: Replica bias circuit for generating the bias voltage of the load devices [2]

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CHAPTER 3 STSCL STANDARD CELL LIBRARY This chapter mainly discusses design and specification of the STSCL library cells. General design methodology and specifically detailed layout design of the STSCL library cells are discussed as well. Designing the bias circuitry for the STSCL circuits is mentioned briefly at the end of this chapter. 3.1 WHAT IS A STANDARD CELL? A standard cell consists of a set of transistors and their connections which implements a boolean logic or a storage function. Although it is possible to generate any boolean function using only a NAND (or a NOR) gates, but the designs will be more area effective by including other logical gates in the library. The elementary gates such as Buffer, Inverter, NAND, NOR, XOR and memory cells are often found in any standard library while the rich and fancy libraries contain additional gates with higher complexity such as adders and multipliers. The initial design of a standard cell begins with implementing the functionality of the cell at the transistor level. The schematic view of a cell is used for this purpose. In addition, schematic views are widely used for simulating and debugging the circuits. The schematic of a cell can be represented by symbol view which consists of the input and output ports of the cell as well as some text information. Standard cell libraries contain another view which is called layout. Designing the layout view of a cell is compulsory since the netlist is useful for simulation purposes and not for fabrication. The layout of a cell represents what will be physically placed on a chip. Each layout consists of several base layers which form the structures of the transistors and interconnect lines. Designing area efficient layouts which could meet the

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required power and timing constraints is still a challenging task despite the existence of different CAD tools to aid the process of design. The designed cell layouts must be checked to insure that no design rules are violated (Design Rule Check). Then it’s necessary to test the layout by Layout Versus Schematic (LVS) in order to verify compatibility of the layout with corresponding schematic. Now, post layout simulation can be performed by extracting the parasitic after passing the LVS check. 3.2 APPROACHES IN INTEGRATED CIRCUIT DESIGN The way that an integrated circuit is constructed depends on the constraints to fulfill. There are three approaches to create a digital integrated circuit. The first approach, Full-Custom Design, is when the designer plans the layout manually. In this approach, each transistor in design is sized and optimized manually to meet the desired constraints. The advantages of this approach include a compact area, performance improvements as well as the ability to include various components such as microprocessors or analog components. Obviously, manufacturing time and cost will increase and a higher skill will be required on the part of the design team as well. As a result, this method is suitable for the designs with strict requirements to fulfill. The second approach, Semi-Custom Design, is when the designer uses already designed logic blocks from a cell library to construct the circuit. In this approach, the desired functionality is realized by placing set of simple or even complex logic blocks (instead of transistors and interconnects in the full-custom approach) over and over again in the layout. The main advantage of semi-custom over full-custom design is that the required time to develop a circuit is decreased dramatically. The drawback of semi-custom approach is the loss of control over the layout as well as characteristics of the gates as pre-developed logic blocks are used in the design. In contrast with full-custom method, the chips designed using the semi-custom method are cheaper in small production volume, but more expensive in high production

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volume. This makes semi-custom design very appropriate for debugging and prototyping new designs [6]. A good approach in chip design is using a combination of full and semi-custom design methods, where the designer creates and optimizes logical blocks manually and then uses them in the layout instead of using pre-designed blocks from a library. The third approach, Automatic Design, is when a CAD tool creates the layouts automatically and uses standard library cells to realize the circuit. The design is described in high-level hardware description languages such as verilog or VHDL. Then, the high level description is fed to the tool to create the corresponding layout. The CAD tools are able to optimize the generated layouts to meet the desired constraints. Although this method is the fastest way of realizing a circuit layout, but it suffers from less optimized layouts as well as loss of control over the way that the layout is generated. 3.3 LIBRARY SPECIFICATIONS The STSCL library is implemented in 0.18 μm standard CMOS technology. Each standard cell library usually contains at least NOT, NAND, NOR and DFF to be able to implement different logic functions without difficulty. The designed cell library contains 13 types of elementary gates: BUFF/INV, DFF, DFF_ARESET, MUX, AND2, AND3, XOR2, XOR3, HA, FA, LATCH, OR2 and OR3. Because of differential operation of the STSCL gates, OR2/OR3 gates can be replaced by AND2/AND3 gates whose input and output ports are negated. Hence, OR2 and OR3 gates will not be included to be characterized in the characterization step where any possible combinations of input and output ports are tried. The cells in the library (except the Flip Flop with asynchronous reset) come with five different driving strengths: x1, x2, x4, x8 and x16. For most of the cells, the driving strength of x4 corresponds to a bias current per gate of Iss except for the Flip Flops, HA and FA gates which corresponds to 2 Iss. The relation between the bias current and

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driving strength of the gates in the library is given in Table 3-1. The information provided by this table can be used to estimate the total current drawn from the supply voltage by knowing the number and types of the cells used in the design. The height of the layout of each cell in the library is fixed and equals to 14 μm. The width of the layouts of the cells varies between 6.3 and 26.6 μm for the INV_x1 and FA_x16 gates respectively. The width of each cell must be an integer multiple of the horizontal grid spacing. The area of each STSCL cell is quite larger than its CMOS counterpart due to the load devices and the tail transistors. In addition to these overhead transistors, sometimes it is necessary to increase the width of the cell to accommodate all the transistors. As the increase in the width must be a multiple of the vertical grid (0.7 μm), a large area may stay unoccupied. The differential pins, as will be discussed in section 3.4.1, also occupy a relatively large area since they must be placed on the intersections of adjacent grids. The differential inputs and outputs of the cells are represented by a “_H” for a High and a “_L” for a Low value at the end of the name of the signals. For various driving strengths of a cell, the “_x1”, “_x2”, “_x4”, “_x8” and “_x16” suffixes are added to the name of the cell. 3.4 DRAWING LAYOUT STRATEGIES All of the cells in the library have VBN, VBP, power and ground pins in common and hence the corresponding rails must be placed in the same place in the layout of the cells. Table 3-1. Driving strength and bias current correspondence Driving strength X1 X2 X4 X8 X16

Bias current of FFs, HA and FA gates

0.5 Iss Iss 2 Iss 4 Iss 8 IssBias current of other

gates 0.25 Iss 0.5 Iss Iss 2 Iss 4 Iss

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In addition, the connections near the borders of the cells are spaced at least 0.35 μm from the boundary to prevent DRC errors when the cells are placed side by side. The body contacts of the pMOS devices should be spaced at least 0.45 μm from the borders. The differential pins must be places on the intersections of the minor grids. Placing the fat pins of a cell on different horizontal or vertical routing grids will ease routing of the pins. It is also beneficial to make the connections only by ME1 and poly layers to generate lower blockages. Sometimes it is not possible to draw all of the connections using the mentioned layers due to high complexity of connections. In this case, making the connections on the preferred grids using higher metal layers will generate fewer blockages. 3.4.1 ROUTING GRIDS AND DIFFERENTIAL PINS Routing grids are where the router routes the pins over the cells. In general, it’s important to choose grid spacing for different routing layers properly to simplify routing and to avoid errors. The grid spacing is chosen 0.7 μm in the layout view of the cells. In the designed cells, both vertical and horizontal routing grids have offset with respect to the cell’s origin and the offset distance is exactly one-half of the grid spacing. The scripts written for the synthesis and placement and routing of the STSCL gates impose some extra restrictions on the layout of the cells. Contrary to the CMOS standard cells whose pins can be placed on the intersections of grids everywhere on the layout (except the power and ground pins), the differential pins in the STSCL cells must be placed on the intersections of the minor grids near each other. Although this rigid constraint wastes a relatively large area for the differential pins (0.8836 μm2 for the pins on ME1), but ensures the integrity of the differential signals as well as ease of differential routing. Before differential routing, the scripts of fat routing need to be run which use fat pins. The fat pins are created on each pair of differential pins using the layer fat ME1 and fully cover the differential pins. Figure 3-1 shows the template for placing the fat and differential pins with respect to routing grids.

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Figure 3-1: The template for placing the differential and fat pins with respect to routing grids 3.4.2 POWER, GROUND AND BIAS RAILS The differential pins need to be placed on the intersection of minor grids but power and ground pins are abutment pins and do not need to be placed on the intersections. All of the STSCL cells in the library need two bias voltages (VBN and VBP) for proper operation in addition to the power and ground pins. The VBN and VBP pins are treated exactly like the abutment pins. This means that the bias rails are drawn in the layout such that they are automatically connected by placing the cells side-by-side. Polysilicon layer is used for connecting the bias rails to the gate of the corresponding transistors in the design. The reason for using polysilicon layer is that all of the rails on the layout are in ME1 layer and block any connection with ME1 to the lower rails. It’s important that the poly contacts are placed properly on these shared rails to prevent DRC errors after placement. To do this, the poly contacts are placed symmetrically on the intersection of the major grids. The remaining space between the contact and the adjacent major grids should be filled with polysilicon and metal layers. This is to prevent DRC errors if the contact of another cell is placed on the same or adjacent major grid.

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Poly Contact

Vss

VBP

Vdd

VBN

prBoundary Layer

14 um

Variable width Figure 3-2: The template of the designed cell with power, ground and bias rails Figure 3-2 shows the detailed template of the layout view of the cells with power, ground and bias rails. In this figure, a layer called prBoundary is also shown which determines the effective boundary of the cell. The boundary of each cell is smaller than the overall cell layout since the bias rails are shared amongst adjacent cells. In the next section, design of an STSCL buffer/inverter cell is discussed in detail. 3.5 STSCL BUFFER/INVERTER The detailed design of a simple cell of the library with various driving strengths is discussed in this section. The schematics, layouts and description of other cells are

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given in Appendix A. Post-layout simulations are performed on all of the cells to verify correct functionality of them. 3.5.1 SCHEMATIC AND LAYOUT Figure 3-3 shows the schematics of the designed buffer with various driving strengths. The size of the source-coupled nMOS devices is fixed for all of the cells and equals to 600 300 . The size of each load device with one finger equals to 500 1 . It is necessary for the load devices and current sources to be composed of identical unit devices in order to ensure a good matching. Therefore, for all of the cells with the same driving strength, the size of the load devices and current sources will be identical. Please note that the increase in the driving capability of the pMOS devices is achieved through increasing the number of the fingers of these devices. Changing the number of series or parallel tail transistors is a simple way of changing the bias current and hence the driving strength of a cell. The dimensions of each nMOS device providing the bias current of the cell equals to 500 2.5 . The layouts of the buffers with various driving strengths are shown in Figure 3-4. 3.5.2 CHARACTERISTICS As the outputs of each STSCL gate are connected to the gates of the nMOS differential pairs of another gate, the swing voltage should be chosen larger than the minimum allowed voltage which is 4×nUT 130 mV (at room temperature) to ensure that the current in the next stages is switched completely. The chosen supply and swing voltages for the library cells are 500 and 200 mV respectively. The designed buffer using the STSCL technique is characterized carefully for various tail bias currents. The time constant of the circuit is proportional to the output swing (200 mV), load capacitance and inversely proportional to the bias current:

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Figure 3-3: The schematics of the Buffer gates with driving strength of (a) 1, (b) 2, (c) 4, (d) 8 and (e) 16

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(a) (b) (c)

(d) (e) Figure 3-4: The layouts of the buffers with driving strength of (a) 1, (b) 2, (c) 4, (d) 8 and (e) 16

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(3-1) As the bias current increases, the propagation delay, rising and falling transition times of the gates will decrease. The dependency of the delay, rising and falling transition times to the bias current with an external capacitance of 20 fF are summarized in Tables 3-2 to 3-4. Table 3-2. Propagation delay of the buffers for various bias currents (μs)

Cell\Bias Current 100 pA 500 pA 1 nA 10 nA 100 nA BUF_x1 150 29.02 14.16 1.301 0.136 BUF_x2 81.92 15.53 7.51 0.675 0.069 BUF_x4 47.33 8.784 4.193 0.362 0.036 BUF_x8 32.29 5.236 2.463 0.207 0.017

BUF_x16 20.92 3.653 1.738 0.146 0.007 Table 3-3. Rising transition time of the buffers for various bias currents (μs) Cell\Bias Current 100 pA 500 pA 1 nA 10 nA 100 nA

BUF_x1 449.4 82.950 39.770 3.455 0.343 BUF_x2 240.9 44.24 21.22 1.818 0.181 BUF_x4 137.4 25.16 12.06 1.033 0.101 BUF_x8 87.88 14.84 7.058 0.598 0.057

BUF_x16 59.28 10.45 5.001 0.423 0.038 Table 3-4. Falling transition time of the buffers for various bias currents (μs) Cell\Bias Current 100 pA 500 pA 1 nA 10 nA 100 nA

BUF_x1 401.1 78.32 39.37 4.197 0.507 BUF_x2 208.7 41.18 20.77 2.246 0.271 BUF_x4 116.9 23.51 11.92 1.302 0.156 BUF_x8 68.8 13.58 6.898 0.754 0.093

BUF_x16 48.76 9.713 4.926 0.535 0.069

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3.6 BIAS CIRCUIT PREPARATION This section discusses design of a bias circuit for the STSCL circuits. The bias circuit consists of a replica bias and another circuitry which provides the replica bias with the desired current. The purpose of this circuitry is to generate a well-controlled wide range of current out of a fixed off chip current. The replica bias circuit is a controlling circuit which keeps the output of SCL gates on the desired value (see Figure 2-3). Matching of replica bias circuit with the SCL gates is critical in order to have low deviation in operating point [2]. The amplifier in the replica bias circuit should provide low offset as well as enough gain to achieve the desired accuracy. Design of an amplifier for the replica bias circuit is discussed in the following section.

Figure 3-5: Schematic of the amplifier in the replica bias circuit; All the dimensions are in micro meter.

Figur

re 3-6: (a) TpTotal gain of phase in degf the amplifiegrees for var

(a)

(b) er and the prious bias cupMOS load durrent of thedevice and (be load devicb) corresponce

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nding

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3.6.1 AMPLIFIER DESIGN The replica bias circuit is working at dc frequency when the bias current of the circuit is fixed. Hence, the amplifier does not need to be fast but should provide enough gain. A folded/cascoded topology is chosen to realize the amplifier. This topology offers a high gain but a speed in the range of basic amplifiers. The schematic of the designed amplifier is given in Figure 3-5. The bias current of the amplifier is provided through a pseudo cascoded current mirror. Area of the main nMOS devices in this current mirror are selected large enough to limit the 1/f noise as well as to ensure that the required precision is achieved. Besides, larger length of the device results in a larger modulation voltage and hence smaller output conductance. The amplifier must provide enough gain and phase margin when the bias current of the replica bias circuit is altered. Figure 3-6 shows the bode plot of the circuit consists of the amplifier and load device for various bias current of the replica bias circuit. The bias current and supply voltage of the amplifier are 1 nA and 1.8 V respectively while the supply voltage of the load device is 1 V. The unity gain frequency is approximately 1.6 kHz for the lowest bias current (10 pA) while the corresponding phase margin is around 60˚. Both phase margin and unity gain frequency will increase when the bias current of the circuit is increased. The dc gain of the amplifier for all range of bias current is higher than 80 dB. 3.6.2 BIAS CURRENT GENERATOR The aim of bias current generator is generating a wide range of current for the replica bias circuit. A fixed off chip current of 10 μA is applied to this circuit. The generated output current ranges between 10 pA and 700 nA. The core part of the circuit consists of several current mirrors that provide the programmable part with required bias voltages. The output current can be precisely controlled by applying some external

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control signals to both core and programmable parts. Figure 3-7 shows the schematic of the bias current generator. All the dimensions are in micro meter. The key point for designing the circuit is proper sizing of the devices of the current mirrors. The procedure for sizing the devices is as follows. The dimensions of the transistors in the current mirror are determined by applying the MOS current equation and the following equation which insures that the required current precision is achieved:

Figure 3-7: Schematic of the bias current generator for the replica bias circuit

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(3-2) where √ . √ . . In 0.18 μm CMOS process, beta factor mismatch and threshold voltage mismatch parameters for the nMOS devices are 1 %. and 5 . respectively. The MOS current equation based on the EKV model [5] is:

. , (3-3) It is necessary that a proper precision for the current is chosen when dealing with equation 3-2 is concerned. Obviously, increasing the dimensions of the devices will result in a higher precision but a larger circuit area. The relative error in the output of the current mirror in percent for various corners at a temperature of 50 ˚C is given in Table 3-5. Table 3-5. Simulated relative error in the output of the bias current generator in percent for various corners at a temperature of 50 ˚C

Corner\Desired Current 100 nA 10 nA 1 nA 100 pA 10 pA

tt 0.04 0.01 0.07 0.5 4.8 ss 0.064 0.025 0.05 0.56 5.04 ff 0.008 0.029 0.22 1.59 9.7

snfp 0.04 0.01 0.089 0.69 6.3 fnsp 0.02 0.01 0.12 0.96 6.94

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CHAPTER 4 LIBRARY CELL CREATION This chapter describes the necessary steps for characterizing the library cells as well as generating the data for various back-end tools. These steps include template generation, Library Exchange Format (LEF) file generation and library characterization. 4.1 TEMPLATE GENERATION The logic function in MCML/STSCL circuits is realized by an N-level network. This network can be modeled by a Binary Decision Diagrams (BDD). All possible N-level BDDs topologies are called footprints. The footprints of 1-2 levels network are shown in Figure 4-1 [7]. A 1-level network can only be mapped to the Buffer and Inverter gates while for networks of 1-3 levels, 19 unique footprints exist and can be mapped to a large number of cells like XOR3, AND3, etc. Generation of the footprints is discussed in detail in [3]. Each of these footprints corresponds to a different physical network. The number of the nodes in an N-level footprint is between N and 2N − 1. The footprints correspond to the function with the maximum number of inputs that can be realized with this network. Obviously, the functions with fewer inputs can also be realized by assigning the inputs to more than one node in the network. All boolean functions that can be realized by a specific footprint are simply obtained by trying all possible variable assignments [3]. The templates are generated out of the footprints by trying different input assignments. This way, a rich cell library is created with only a limited number of physical cells. A unique function may be realized using different templates and therefore the function can be physically implemented with different networks. The different

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implementations of a same function are called variations which might have different electrical properties. One important aspect of MCML/STSCL circuits is that all inputs and outputs are differential and therefore, inverted signals are always available. A new set of cells can be created by inverting the inputs and outputs of the cells in all possible combinations (2N+M possible combinations for a cell with N inputs and M outputs) [3]. The new set of cells enables the synthesizer to select a gate with any combination of inputs and outputs. In this way, the synthesizer does not need to explicitly invert a signal when a signal has to be inverted. As a result, a significant number of inverters is reduced in a large design which improves the delay as well as reducing the area. The drawback of this approach is that the number of cells in the library is increased dramatically. 4.2 FAT LIBRARY CREATION Currently, design automation tools cannot handle circuits with differential inputs/output ports. In particular, working with these tools seems problematic with MCML/STSCL circuits due to the importance of integrity of differential signals. Although two differential signals carry the information in these circuits, but from the logic point of view, the signals can be replaced by one signal.

Figure 4-1: Footprints of 1-2 levels networks

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In fact, only when dealing with physical tasks is concerned, it is necessary to take into account the differential nature of the signals. The idea behind synthesis and place and route of MCML/STSCL circuits is to replace differential pins with larger pins called fat pins. Other specifications of the cells like area, layers and blockage remain unchanged [7]. The resulting cells can now be treated exactly like the standard cells with single input/output ports. After place and route of the fat cells, each logical wire will be splitted into a pair of differential wires. To generate the fat library out of differential template cells, a specific layer is added on the differential pins in the corresponding layout view. Then, corresponding symbol and layout views are generated for all of the cells. The next step is generating fat cells out of the differential cells with inverted input/output ports. Only one fat cell needs to be generated for the set of cells created by inverting the inputs and outputs of a specific cell. Running the SKILL scripts generates all the fat cells out of the differential cells [8]. 4.3 LEF FILE GENERATION The LEF files describe the cells in a standard cell library. The LEF abstract of a cell does not contain all the layout of the cell but the layers and vias that are important from a routing point of view. There are two types of LEF files: The first type is technology LEF and the second type is generated by the abstract generator. The abstract generator uses the technology LEF file to generate the other. A LEF file contains the technology, site and macros. Macro cell definition includes description, dimensions, blockages, layout of pins and capacitances of a cell. The technology LEF file is provided by the foundry and contains all the technology specifications including the layers, Vias and design rules. Layers are defined in process order from bottom to top and each layer consists of several attributes such as type, width, direction, resistance and capacitance per unit square, spacing rules and antenna factor.

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An abstract view is also generated by the abstract generator which will be used by Silicon ensemble for placement and routing. The abstract view of a cell contains information such as routing obstructions, and the name, orientation and PR boundary of a cell, as well as the name, direction, type and metal layers of the pins. In case of MCML/STSCL circuits, the LEF files must be generated for both differential and fat libraries. The “create_lef.csh” script runs the abstract generator and produces the required LEF files. 4.4 LIBRARY CHARACTERIZATION The designed library cells must be characterized to extract the timing behavior of the cells. Timing characteristics of the cells affects the synthesizer’s choice of what cells to use in a particular design to meet the timing constraints. The differential template library with layouts and the geometry LEF for the templates are required to complete characterization of the cells. The cells are characterized for the corner with a swing voltage of 200 mV and a bias current of 100 pA. The procedure for characterization of STSCL library cells is as follows. First, the “avextract.csh” script must be executed to extract the SPICE netlists from the cell layouts. A SPICE netlist is a list of components and their connections to each other. Second, the “characterize.csh” script must be run to simulate the extracted netlists. The inputs to this script are the netlists and the functionality of the cells. The circuit's time domain response is now calculated by applying the proper stimulus. The simulation results are used to verify whether the library cell implements the desired function, and to estimate important parameters such as propagation delay and power consumption of the cell. After simulating the netlists, the script generates the liberty library and the verilog models of the cells. The corresponding liberty library and verilog models are also generated for variants of the cells with inverted input/output ports. Liberty library, the Synopsys' widely used library, includes the “.lib” and “.plib” formats.

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The liberty standard enables precise modeling of timing, noise and power as well as test. Finally, the “compile_lib.csh” script needs to be executed to compile the liberty library and to create the VHDL models. The complete procedure for creating the STSCL library cells, characterizing the cells as well as detailed use of the scripts is discussed in Appendix B.

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CHAPTER 5 SUB-THRESHOLD SOURCE COUPLED LOGIC TEST CIRCUIT A test circuit has been implemented using the STSCL library cells in 0.18 μm CMOS technology to verify correct operation of the cells. The test circuit is a low pass Finite Impulse Response (FIR) filter. This chapter discusses the structure, synthesis, placement and routing of the FIR filter and then presents simulation results of the test circuit. 5.1 FIR FILTER STRUCTURE FIR filters are one of popular types of filters used in digital signal processing systems. Almost any sort of frequency response can be realized using these filters. Each FIR filter consists of one or multiple delay elements, multipliers and adders. The output is the sum of delayed inputs multiplied with their respective filter coefficients. The coefficients in an FIR filter are the impulse response of the filter. The following equation represents operation of an FIR filter with N=M+1 taps [9]: ∑ . (5-1)

Figure 5-1: Signal flow graph of an FIR filter with N=M+1 taps

36

where h(n) represents the filter coefficients and x(n) the sequence of input samples. The corresponding signal flow graph is shown in Figure 5-1 [9]. One important aspect of the FIR filters is that they are inherently stable since there is no feedback element in their structure. Therefore, any bounded input will produce a bounded output. FIR filters are usually designed to be linear-phase. A linear-phase filter is typically used when a causal filter is needed to modify a signal's magnitude-spectrum while preserving the signal's time-domain waveform as much as possible [9]. If the coefficients of an FIR filter are symmetrical around the center coefficient, the filter will be linear-phase. Consequently, the delay of the filter is the same at all frequencies. Therefore, the phase or delay of the filter is not distorted which could be an important advantage of FIR filters over IIR and analog filters in particular systems [9]. The number of calculations in an FIR filter can be reduced by reducing the number of taps used in the filter; however, this will deteriorate the quality of the filtering by producing more ripples, less accurate passband and less steep roll off. 5.2 TEST CIRCUIT STRUCTURE A 16-bit, 9-tap low pass FIR filter is synthesized to verify functionality of the STSCL cell library. MATLAB Filter Design and Analysis Tool (fdatool) and WinFilter software by A. Kundert were used for the design and test of the filter. The specifications of the filter are given in Table 5-1. The sampling frequency of the filter must be quite low since the cells in the library are characterized for a low bias current (100 pA here). The filter offers more than 30 dB attenuation in the stopband. The frequency and phase responses of the filter are shown in Figure 5-2. Figure 5-3 shows the step and impulse responses of the filter. The zeros of the filter are located at 1 and the poles at 0.524300 0.145774 and 0.6604570.443323. The group delay of the filter is constant and equals to 40 ms: 40 (5-2)

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Table 5-1. FIR filter specifications Specification Value

Type Low passOrder 8

Number of Taps 9Cut Off Frequency 10 Hz

Sampling Frequency 100 HzSignal Resolution 16 bits

Coefficients Quantization 8 bits

Figure 5-2: FIR filter (a) Frequency Response and (b) Phase Response

Figure 5-3: FIR filter (a) Step Response and (b) Impulse Response Figure 5-4: Pre-synthesis simulation results of the FIR filter

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Prior to synthesis of the filter using STSCL technique, the behavior of the digital filter is simulated in Modelsim to verify if the filter is working properly. The VHDL code for modeling the behavior of the filter and the test bench for simulating the circuit are given in Appendix C. Note that the complete test bench for applying various stimulus is generated using MATLAB and contains thousands of lines of code; therefore, only the template of the test bench is given in Appendix C. The circuit is operating at a clock frequency of 100 Hz for the bias current per gate of 100 pA. The sampling frequency and the frequency response of the filter can be simply scaled by altering the bias current of the gates. Figure 5-4 shows the response of the filter to various stimulus such as a ramp, step, chirp (a signal in which the frequency increases or decreases with time), impulse and noise signal. According to this figure, the filter can effectively remove high frequency components of the input signal. 5.3 SYNTHESIS OF THE FILTER The filter is synthesized using both 0.18 μm standard CMOS and the developed STSCL libraries. The circuit constraints and the scripts for synthesizing the circuit are given in Appendix D. The script reads the VHDL code, elaborates and compiles the design, creates various reports and finally generates the necessary files for the place and route tool as well as the files for post-synthesis simulation. Worth mentioning, it is possible to reuse the scripts for synthesizing similar circuits as they are written such that the user has the possibility to specify the design, technology, corner, library and other general parameters. The reference cells of the test circuit synthesized using the developed STSCL library and the standard CMOS library are given in Tables 5-2 and 5-3 respectively. The total cell area of the circuit synthesized using the developed library is more than 11 times that of the standard CMOS library. This not a surprising result since each STSCL library cell is fairly larger than its CMOS counterpart. For example, the area of an inverter from the STSCL library is 88.2 μm2 which is quite large compared to the area of a CMOS

39

Table 5-2. Reference cells of the test circuit synthesized using developed STSCL library Reference Unit Area Count Total Area Attributes

AND2_x4_0 98 9 882 AND2_x4_4 98 17 1666 AND2_x4_6 98 15 1470 AND2_x4_7 98 1 98 AND3_x4_7 127.4 1 127.4 AND3_x4_8 127.4 1 127.4 DFF_ARESET_x1_0 215.6 533 114914.8 n FA_x1_31 254.8 65 16562 r FA_x4_0 254.8 211 53762.8 r HA_x2_0 205.8 11 2263.8 r BUF_x4_2 88.2 36 3175.2 XOR2_x2_0 107.8 6 646.8 XOR2_x2_3 107.8 1 107.8

Total 13 references 195804 n: non-combinational, r: removable

inverter (2 μm2). In addition, the synthesizer has used several adders and multipliers to synthesize the filter from the rich standard CMOS library which significantly improves utilizing the area while only very basic cells are available for the synthesis from the STSCL cell library. Furthermore, redesigning the Flip Flops or revising their layout could reduce the overall area dramatically since they have occupied nearly 60 % of the area. The total bias current of the cells in the test circuit synthesized using the STSCL cell library can be simply calculated by knowing the type and number of the cells in the design. The relation between driving strength and bias current of the cells was given in Table 3-1. The total bias current of the STSCL circuit is then: ∑ (5-3) The power consumption of the STSCL circuits can now be simply estimated by: (5-4) Hence:

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Table 5-3. Reference cells of the test circuit synthesized using standard CMOS technology Reference Unit Area Count Total Area Attributes

BUF1CK 4 5 20 INV1S 2 2 4 MOAI1S 6 16 96 ND3 4 1 4 NR3 5 1 5 QDFFRBN 19 177 3363 n TIE0 3 1 3 TIE1 3 1 3 adder_A15_0_B15_0_Q16_0_0 641 1 641 h, n adder_A15_0_B15_0_Q16_0_1 641 1 641 h, n adder_A15_0_B15_0_Q16_0_2 641 1 641 h, n adder_A15_0_B15_0_Q16_0_3 641 1 641 h, n adder_A24_0_B24_0_Q25_0_0 968 1 968 h, n adder_A24_0_B24_0_Q25_0_1 987 1 987 h, n adder_A25_0_B25_0_Q26_0 997 1 997 h, n adder_A26_0_B26_0_Q27_0 783 1 783 h, n dummyAdder_A15_0_Q16_0 325 1 325 h, n dummyAdder_A24_0_Q25_0 481 1 481 h, n dummyAdder_A25_0_Q26_0 500 1 500 h, n multiplier_A7_0_B16_0_Q24_0_0 1047 1 1047 h, n multiplier_A7_0_B16_0_Q24_0_1 1498 1 1498 h, n multiplier_A7_0_B16_0_Q24_0_2 1426 1 1426 h, n multiplier_A7_0_B16_0_Q24_0_3 1085 1 1085 h, n multiplier_A7_0_B16_0_Q24_0_4 1082 1 1082 h, n Total 24 references 17241n: non-combinational, h: hierarchical 100 9 1 17 1 15 1 1 1 1 1 1 1 5330.5 65 0.5 211 2 11 1 36 1 6 0.5 1 0.581.55 Using equation 5-4, the power consumption of the STSCL circuit is then 40.775 nW approximately. The power consumption of the synthesized CMOS circuit is mainly due to the leakage power since the operation frequency is quite low. The reported power

41

consumption of the CMOS circuit is 818.178 nW for a supply voltage of 1.8 V. At the moment, it is not possible to make a fair and direct comparison between the power consumption of the CMOS and STSCL circuits since the CMOS library cells are characterized for a supply voltage of the 1.8 V. In addition, the reported power consumption by the synthesizer is not very precise since the power consumption of each CMOS circuit also depends on the activity factor of the circuit. In order to make a fair comparison between CMOS and STSCL circuits, the CMOS library must be characterized for the given supply voltage. Then SPICE simulation should be performed on the netlist extracted out of the routed circuits. The post-synthesis simulation of the synthesized STSCL test circuit shows correct operation of the filter. The simulation results are depicted in Figure 5-5a. Figure 5-5b shows the post-synthesis simulation results of the filter realized using the standard CMOS library. The placement and routing of the test circuit is discussed in detail in the next section.

(a)

(b) Figure 5-5: Post-synthesis simulation results of the (a) STSCL and (b) CMOS test circuit

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5.4 PLACEMENT AND ROUTING After synthesizing the design, the synthesized netlist is saved in the verilog format. This synthesized design can now be converted into a layout using the Cadence SoC Encounter. This place-and-route tool uses the synthesized verilog netlist and generates its equivalent layout view. A few files are necessary for a successful place and route of a design including the synthesized verilog netlist and the technology file as well as the fat and differential LEF files. The first step is specifying the floorplan. The floorplan size can be extracted from the area report generated by the synthesis tool. The next step is power planning. The global nets (Vdd, Vss, VBP and VBN) are now connected and the corresponding rings can be inserted. Special route (sroute) is used to create connections between the core rows and core rings and from the core rows to the core supply pads. In the next step, the information in the gate-level netlist is used to place the fat cells on the floorplan. The cells may be arranged by providing timing information generated during RTL synthesis. Figure 5-6 shows the placed design and the power and bias rings as well. In digital designs, the location of registers is known after the library cells are placed and therefore, a clock tree must be synthesized in this step. The constraints for clock tree synthesis are obtained from the clock tree specification file. It is important that the clock tree is synthesized before routing of other signals. This way, the clock tree is routed in an efficient way and therefore, clock skew is reduced. Unfortunately, synthesizing a clock tree for the FIR filter is not possible since the SoC encounter could not handle extremely low clock frequencies (100 Hz here). Hence, the clock signal of the test circuit is drived with large buffers instead of synthesizing a clock tree. Although a clock tree could not be synthesized, as we will see later, the circuit will work properly since driving the clock signal with large buffers is enough as the speed of the circuit is quite low. The clock buffers are placed in the gaps of the floorplan. In the next step, the signals as specified in the netlist need to be routed to complete physical placement of the single ended design. Then the designer is checked to see if everything is properly connected. When fat routing is finished, all the information is

43

exported into a DEF file which will be modified to be used in the differential routing phase. Now, wire splitting has to be performed to change fat wires into differential ones. A DEF parser is employed for this purpose which changes the fat DEF file into a differential one. The L-shape and S-shape wires are handled by the script but the remaining T-shape wires should be removed [7]. The fat design is now removed and the differential LEF and DEF files along with the differential netlist are imported to the tool. The result is a circuit where the fat cells are replaced by differential cells and the fat wires by differential wires. The floorplan and the power supply rings remain unchanged. The final step is refining the differential connections, adding vias, and routing the T-shape connections which were deleted at the wire splitting step. The design is now checked to insure that all the connections are properly routed. If everything is correct, the differential routing is complete and the final layout can be exported as a GDSII file.

Figure 5-6: The placed design and the power and bias rings

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The final differential layout view of the FIR filter is shown in Figure 5-7. The script for placement and routing of the test circuit is also given in Appendix E. General design information for the routed single ended and differential test circuit is given in Table 5-4.

Figure 5-7: Layout view of the implemented FIR filter

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Table 5-4. General design information for the routed single ended and differential circuits Parameter Single Ended Differential

Design Status Routed Routed # Instances 872 872

# Hard Macros 0 0# Std Cells 872 872

# Pads 0 0# Net 1190 2376

# Special Net 4 4# IO Pins 35 70

# Pins 3698 7396 # PG Pins 3488 3488

Average Pins Per Net (Signal) 3.108 3.113 5.5 SIMULATION RESULTS Post-layout simulation has been performed on the implemented design, confirming its correct functionality. SPICE simulation of the circuit which consists of 20773 nodes is time consuming and hence, functionality of the circuit can be examined only for limited number of inputs. A Verilog-A code is written to convert the analog outputs of the STSCL test circuit into corresponding digital hexadecimal code in order to simplify comparison of the results from SPICE simulation with those of verilog simulation. The code is given in Appendix F. Figure 5-8 shows the outputs of the filter for the hexadecimal input sequence of 0000, 000F, 00FF, 08FF and 00FF. The replica bias current is 100 pA and the supply and swing voltages are 500 and 200 mV respectively. The circuit is working at a clock frequency of 100 Hz. The corresponding verilog simulation results are shown in Figure 5-9. The results of SPICE simulation matches with those of verilog simulation for the mentioned input sequence. The filter is also working properly at higher sampling frequencies which is simply achieved by increasing the bias current of the circuit. As explained before, one advantage of STSCL circuits over their CMOS counterparts is that the DC current drawn form the supply voltage prevents switching effects [4]. The current drawn form the supply voltage for the mentioned SPICE simulation is shown in Figure 5-10. It can be seen clearly that the circuit generates extremely low amplitude

46

current spikes. The power consumption of the routed STSCL circuit is approximately 39 nW at the bias current of 100 pA and the corresponding clock frequency of 100 Hz.

Figure 5-8: Post-Layout simulation results of the implemented FIR filter; the outputs which are not presented are at logic ‘0’.

47

Figure 5-9: Verilog simulation results of the implemented FIR filter

Figure 5-10: The current drawn from the power supply rails of the STSCL test circuit

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CHAPTER 6 CONCLUSIONS In this thesis, design of a library cell for the STSCL circuits was discussed. The synthesized and implemented FIR filter using the STSCL library cell was working properly for various sampling frequencies. The power consumption of the implemented 16-bit, 8-taps filter is as low as 39 nW for a clock frequency of 100 Hz, supply voltage of 500 mV and swing voltage of 200 mV. Currently, it is not possible to make a fair comparison between the power consumption of CMOS and STSCL circuits unless the CMOS library is characterized for the given supply voltage. The total cell area of the filter is far larger than the CMOS circuit which is not a surprising result as each cell in the STSCL library is quite larger than its CMOS counterpart due to the overhead load and bias transistors as well as a large area for differential pins. Although the designed library cannot compete with relevant CMOS library in terms of area and variety of cells, but several modifications can be applied to the library to make it more efficient. The first improvement is to redesign the Flip Flops which will reduce the area of the sequential circuits dramatically. Current Flip Flops in the library have the same driving strength as other cells in the library. Changing the number or dimensions of the tail and load devices can help to reduce the area of these important gates significantly. The next improvement is to design more complex cells such as multipliers and adders as these cells are often found in any complex design. Currently, the library only contains the bias circuit for the STSCL circuits but it can be extended by including other cells such as a memory cell, level converters, filler cells and output buffers.

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BIBLIOGRAPHY [1] J. M. Musicer and J. Rabaey, “MOS Current Mode Logic for Low Power, Low Noise CORDIC Computation in Mixed-Signal Environments”, in Proc. of the Int. Symp. on Low Power Electronics and Design, pp. 102 – 107, 2000. [2] A. Tajalli, E. J. Brauer, “Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications”, IEEE Journal of Solid-State Circuits, vol. 43, no. 7, July 2008. [3] S. Badel, “MOS Current-Mode Logic Standard Cells for High-Speed Low-Noise Applications”, PhD Thesis, Ecole Polytechnique Fédérale de Lausanne, 2008. [4] O. M. Abdulkarim and M. Shams, “A Symmetric MOS Current-Mode Logic Universal Gate for High Speed Applications”, in Proc. of the 17th ACM Great Lakes Symp. on VLSI, pp. 212 – 215, 2007. [5] C. Enz, and E. Vittoz, Charge-Based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design, Wiley, 2006. [6] W. Chen, The VLSI Handbook, CRC Press, 2000. [7] P. Vietti, “Design of MCML Standard Cell Library and Differential Routing Methodology”, Master Project, Ecole Polytechnique Fédérale de Lausanne, 2007. [8] M. Mercaldi, “Design of Source Coupled Logic Circuits for Ultra-Low Power Applications”, Master Project, Ecole Polytechnique Fédérale de Lausanne, 2007. [9] J. O. Smith, “Introduction to Digital Filters: with Audio Applications”, W3K, 2007.

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APPENDIX A DEVELOPED STSCL LIBRARY CELLS The schematics, layouts and description of the cells with driving strength of 1 are given here. Designing various driving strengths for the cells and dimensions of the transistors are discussed in detail in section 3-5.

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AND2_X1 Description: Function: 2-input AND gate Dimensions: 14 x 7 μm2 Logic equation: Z=A . B Schematic (a) and layout (b):

(a) (b)

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AND3_X1 Description: Function: 3-input AND gate Dimensions: 14 x 9.1 μm2 Logic equation: Z=A . B . C Schematic (a) and layout (b):

(a) (b)

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LATCH_X1 Description: Function: D-Latch Dimensions: 14 x 7.7 μm2 Operation: if CLK=’1’ then Z=D else holds the latched value Schematic (a) and layout (b):

CLK CLK

VDD

VBPZZ

VBN

M1

M7

M8

......

Nf:1Nf:1

D D

(a) (b)

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XOR2_X1 Description: Function: 2-input XOR gate Dimensions: 14 x 7.7 μm2 Logic equation: Z= A B Schematic (a) and layout (b):

(a) (b)

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XOR3_X1 Description: Function: 3-input XOR gate Dimensions: 14 x 10.5 μm2 Logic equation: Z= A B C Schematic (a) and layout (b):

(a) (b)

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MUX2_X1 Description: Function: 2 to 1 multiplexer Dimensions: 14 x 8.4 μm2 Logic equation: . . Schematic (a) and layout (b):

(a) (b)

57

HA_X1 Description: Function: Half adder Dimensions: 14 x 14.7 μm2 Logic equation: S= A B, CO= A . B Schematic (a) and layout (b):

...... ......

(a)

(b)

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FA_X1 Description: Function: Full adder Dimensions: 14 x 18.2 μm2 Logic equation: S= A B CIN, CO= A . B + CIN . (A + B) Schematic (a) and layout (b):

(a)

(b)

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DFF_X1 Description: Function: D-Flip Flop Dimensions: 14 x 14.7 μm2 Logic equation: OUT= D at rising edge of CLK else unchanged Schematic (a) and layout (b):

...... ......

(a)

(b)

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DFF_ARESET_X1 Description: Function: D-Flip Flop with asynchronous reset Dimensions: 14 x 15.4 μm2 Logic equation: OUT= ‘0’ if RESET=’1’ else D at rising edge of CLK else unchanged Schematic (a) and layout (b):

CLK CLK

VDD

VBPOut1OUT1

VBN

M1

M7

M8

......

Nf:1Nf:1

D D

CLK CLK

VDD

VBP OUTOUT

Nf:1Nf:1

OUT1 OUT1

RESET RESET

VBN

M1

M7

M8

......

RESET RESET

(a)

(b)

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APPENDIX B STSCL LIBRARY CELL CREATION PROCEDURE For correct operation of some scripts, it’s necessary to create a folder for the current user in the tmp directory:

>Mkdir tmp/username The working directory is called rev0 located at : /net/lsmsun1/da0/users/mcml/libraries/umc_1180/stscl/. To start a new library design, the content of the rev0 directory should be copied somewhere else since all of the scripts work with the rev0 directory: stscl> cp -R rev0 rev1 The required scripts are located in the .scripts directory: rev0> cd .scripts A list of the scripts can be obtained by the command: .scripts> ls *.csh

1. Load(“create_logical_views.il”) The command should be entered in the Cadence command line environment. This command loads the create_logical_views.il script which is used to create logical views from the symbol view. The script should be placed in the same directory that the Cadence environment is launched. The name of the Library can be set in the script. The script removes the _H and _L extensions from the name of the differential signals and creates a new view in the library called logical. 2. .scripts> csh avextract.csh

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This command is used to extract the SPICE netlists out of the cell layouts. The result is a library with all extracted spice netlists. The script should be executed again only if a cell layout has been changed. Before running the script, some extract options including the working directory, ground name and etc. should be set in the “avextract.in” file. The other abstract options including the metal layer definitions, power pin names and etc. can be set in the “abstract_options.il” and “abstract_options_fat.il” files. The script also generated a log file called avextract.log which contains the information, warnings and errors generated by the script. 3. .scripts> csh create_lef.csh This command is used for creating the LEF files from the layout library by running the Cadence abstract generator. The script creates a detailed log file named “create_lef.log” in the .scripts directory and a report named “stscl.rpt” in the “rev0/lib_s/lef/” directory. 4. .scripts> csh create_gds.csh 5. .scripts> csh create_mw.csh This command is used for creating the milkyway libraries from the LEF files. The milkyway libraries will then used by the physical compiler. The script also generates the technology files (.tf) and the physical libraries (.plib, .pdb). A detailed log file named “Milkyway.log” is also created by the script in the “rev0/lib_s/milkyway/” directory. 6. .scripts> csh characterize.csh This script simulates and outputs the liberty and verilog files. It uses pin functions of the cells which are defined in the “cell_definitions.tcl” and “flipflop_definitions.tcl” files. As an example, the definition of the AND2 gate is: Set_pin_function AND2_x* Out {A&B}

db_set [get_cells –name “AND2_x*”] footprint AND2 It is also possible to force the script not to characterize a specified cell in the library. The cells are characterized for a supply voltage of 0.5 V, swing voltage of 0.2 V and a bias

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current of 100 pA. These corners can be simply modified in the characterize.tcl file. The measurements are stored in the “tmp/username” directory. The characterization speed can be increased by running more processors in parallel. This can be done by adjusting the num_processors parameter in the plc.tcl file. The output of the characterize.csh script is written in the “tt_200m100p.log” which corresponds to the desired swing voltage and bias current. The script may not characterize a cell which was added later to the library. In this case, it is possible to debug characterization of a cell manually. As an example, the procedure for debugging the AND2 gates is given here: 6.1. .scripts> perl ./tools/plc/plc.pl 6.2. plc> db_load stscl_tt_200m100p_done.db 6.3. plc>list_cells 6.4. plc>delete_cell AND2* 6.5. plc>read_spice ../lib_d/spice/AND2_x* 6.6. plc>set_pin_function AND2_x* Out {A&B} 6.7. plc> db_set [get_cells –name “AND2_x*”] footprint AND2 6.8. plc>read_lef –macro ../lib_s/lef/stscl.lef 6.9. plc>db_save stscl_tt_200m100p.db 6.10. plc>exit 6.11. .scripts>csh characterize.csh

7. .scripts> csh compile_lib.csh This script compiles the liberty library and creates the VHDL model.

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APPENDIX C FIR FILTER VHDL MODEL AND TEST BENCH The VHDL behavior of the FIR filter and the test bench are given here. MATLAB Filter Design and Analysis Tool (fdatool) and WinFilter software by A. Kundert were used for the design and test of the filter. VHDL BEHAVIOR -- Component: multiplier library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity multiplier is Port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; A : in std_logic_vector; B : in std_logic_vector; Q : out std_logic_vector ); end multiplier; architecture rtl of multiplier is signal A_tmp : signed( A'length-1 downto 0 ); signal B_tmp : signed( B'length-1 downto 0 ); signal prod_tmp : signed( Q'length-1 downto 0 ); begin assert Q'length = (A'length + B'length) report "multiplier: Q length must equal A + B length" severity error; -- A to signed value conversion A_pro : process(A) begin for i in A'length-1 downto 0 loop A_tmp(i) <= A(i); end loop; end process A_pro; -- B to signed value conversion

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B_pro : process( B ) begin for i in B'length-1 downto 0 loop B_tmp(i) <= B(i); end loop; end process B_pro; -- multiplication prod_tmp <= A_tmp * B_tmp; -- Registered output prod_pro : process(GLOBAL_CLK, GLOBAL_RESET) begin if (GLOBAL_RESET = '1') then for i in Q'length-1 downto 0 loop Q(i) <= '0'; end loop; elsif rising_edge(GLOBAL_CLK) then for i in Q'length-1 downto 0 loop Q(i) <= prod_tmp(i); end loop; end if; end process prod_pro; end rtl; -- Component: adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity adder is Port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; A : in std_logic_vector; B : in std_logic_vector; Q : out std_logic_vector ); end adder; architecture rtl of adder is begin assert A'length = B'length report "adder: A and B must be the same length" severity error; assert A'length = Q'length-1 report "adder: Q length must be the 1 bit wider than A or B" severity error; -- Registered output process(GLOBAL_CLK, GLOBAL_RESET) begin if (GLOBAL_RESET = '1') then Q <= conv_std_logic_vector(0, Q'length); elsif rising_edge(GLOBAL_CLK) then Q <= (A(A'length-1) & A) + (B(A'length-1) & B);

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end if; end process; end rtl; -- Component: Dummy Adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity dummyAdder is Port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; A : in std_logic_vector; Q : out std_logic_vector ); end dummyAdder; architecture rtl of dummyAdder is begin assert A'length = Q'length-1 report "adder: Q length must be the 1 bit wider than A or B" severity error; -- Registered output process(GLOBAL_CLK, GLOBAL_RESET) begin if (GLOBAL_RESET = '1') then Q <= conv_std_logic_vector(0, Q'length); elsif rising_edge(GLOBAL_CLK) then Q <= (A(A'length-1) & A); end if; end process; end rtl; -- Component: FIR filter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity fir is generic ( Coef_Width_g : integer := 8; NTAP_g : integer := 9 ); port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; X_IN : in std_logic_vector(15 downto 0); SATURATION_ERR : out std_logic; Y_OUT : out std_logic_vector(15 downto 0) );

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end fir; architecture speed of fir is component adder is Port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; A : in std_logic_vector; B : in std_logic_vector; Q : out std_logic_vector ); end component; component dummyAdder is Port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; A : in std_logic_vector; Q : out std_logic_vector ); end component; component multiplier is Port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; A : in std_logic_vector; B : in std_logic_vector; Q : out std_logic_vector ); end component; constant CoefScalingBitDrop_c : integer := 9; constant nCoef0_c : integer := 5; constant nCoef1_c : integer := 3; constant nCoef2_c : integer := 2; type DELAYARRAY is array (0 to NTAP_g - 1) of std_logic_vector(X_IN'length-1 downto 0); signal DELAY : DELAYARRAY; type XSUMARRAY is array (0 to nCoef0_c-1) of std_logic_vector(X_IN'length downto 0); signal Xsum : XSUMARRAY; type ROMARRAY is array (0 to nCoef0_c-1) of std_logic_vector(Coef_Width_g-1 downto 0); signal ROMDATA : ROMARRAY; type YSUM0ARRAY is array (0 to nCoef0_c-1) of std_logic_vector(X_IN'length + Coef_Width_g + 0 downto 0); signal Ysum0 : YSUM0ARRAY; type YSUM1ARRAY is array (0 to nCoef1_c-1) of std_logic_vector(X_IN'length + Coef_Width_g + 1 downto 0); signal Ysum1 : YSUM1ARRAY; type YSUM2ARRAY is array (0 to nCoef2_c-1) of std_logic_vector(X_IN'length + Coef_Width_g + 2 downto 0); signal Ysum2 : YSUM2ARRAY;

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signal Y_I : std_logic_vector(X_IN'length + Coef_Width_g + 3 downto 0); signal X_IN_reg : std_logic_vector(X_IN'length-1 downto 0); constant zeros : std_logic_vector(Y_OUT'length-2 downto 0) := (others => '0'); constant ones : std_logic_vector(Y_OUT'length-2 downto 0) := (others => '1'); begin assert Y_OUT'length = X_IN'length report "fir: Y_OUT and X_IN must be the same length" severity error; ROMDATA(0) <= x"06"; ROMDATA(1) <= x"1f"; ROMDATA(2) <= x"41"; ROMDATA(3) <= x"61"; ROMDATA(4) <= x"6e"; process(GLOBAL_CLK, GLOBAL_RESET) begin if (GLOBAL_RESET = '1') then X_IN_reg <= (others => '0'); SATURATION_ERR <= '0'; Y_OUT <= conv_std_logic_vector(0, Y_OUT'length); elsif rising_edge(GLOBAL_CLK) then X_IN_reg <= X_IN; if Y_I( Y_I'length-1 downto CoefScalingBitDrop_c + Y_OUT'length - 1) = zeros(Y_I'length-1 - (CoefScalingBitDrop_c + Y_OUT'length - 1) downto 0) or Y_I( Y_I'length-1 downto CoefScalingBitDrop_c + Y_OUT'length - 1) = ones(Y_I'length-1 - (CoefScalingBitDrop_c + Y_OUT'length - 1) downto 0) then SATURATION_ERR <= '0'; Y_OUT <= Y_I(CoefScalingBitDrop_c + Y_OUT'length-1 downto CoefScalingBitDrop_c); else SATURATION_ERR <= '1'; if Y_I(Y_I'length-1) = '0' then --positive saturation Y_OUT <= '0' & ones(Y_OUT'length-2 downto 0); else --negative saturation Y_OUT <= '1' & zeros(Y_OUT'length-2 downto 0); end if; end if; end if; end process; process(GLOBAL_CLK, GLOBAL_RESET) begin if (GLOBAL_RESET = '1') then for i in 0 to NTAP_g-1 loop DELAY(i) <= (others => '0'); end loop; elsif rising_edge(GLOBAL_CLK) then for i in 1 to NTAP_g-1 loop DELAY(i) <= DELAY(i-1); end loop; DELAY(0) <= X_IN_reg; end if; end process; Xadder_gen : for i in 0 to nCoef0_c-2 generate

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adder_inst : adder port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => DELAY(i), B => DELAY(NTAP_g-1 - i), Q => Xsum(i) ); end generate Xadder_gen; SingleXin_inst : dummyAdder port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => DELAY(nCoef0_c-1), Q => Xsum(nCoef0_c-1) ); CoefMult_gen : for i in 0 to nCoef0_c-1 generate mult_inst : multiplier port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => ROMDATA(i), B => Xsum(i), Q => Ysum0(i) ); end generate CoefMult_gen; AdderLevel1_gen : for i in 0 to nCoef1_c-2 generate Ysum1_inst : adder port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => Ysum0(2*i), B => Ysum0(2*i+1), Q => Ysum1(i) ); end generate AdderLevel1_gen; Ysum1_inst : dummyAdder port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => Ysum0(2*(nCoef1_c-1)), Q => Ysum1(nCoef1_c-1) ); AdderLevel2_gen : for i in 0 to nCoef2_c-2 generate Ysum2_inst : adder port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => Ysum1(2*i), B => Ysum1(2*i+1), Q => Ysum2(i) ); end generate AdderLevel2_gen;

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Ysum2_inst : dummyAdder port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => Ysum1(2*(nCoef2_c-1)), Q => Ysum2(nCoef2_c-1) ); Ysum3_inst : adder port map( GLOBAL_CLK => GLOBAL_CLK, GLOBAL_RESET => GLOBAL_RESET, A => Ysum2(0), B => Ysum2(1), Q => Y_I ); end speed; TEST BENCH FOR THE FILTER LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.ALL; ENTITY filter_tb IS END filter_tb; ---------------------------------------------------------------- ARCHITECTURE test OF filter_tb IS COMPONENT fir is generic ( Coef_Width_g : integer := 8; NTAP_g : integer := 9 ); port ( GLOBAL_CLK : in std_logic; GLOBAL_RESET : in std_logic; X_IN : in std_logic_vector(15 downto 0); SATURATION_ERR : out std_logic; Y_OUT : out std_logic_vector(15 downto 0)); END COMPONENT; FOR ALL : fir USE ENTITY work.fir(speed); -- Type Definitions TYPE filter_in_table IS ARRAY (0 TO 3134) OF std_logic_vector(15 DOWNTO 0); TYPE filter_out_table IS ARRAY (0 TO 3134) OF std_logic_vector(15 DOWNTO 0);

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-- Constants CONSTANT filter_in_force : filter_in_table := ( to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0), --other inputs for the filter to_stdlogicvector(bit_vector'(X"05b6"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"07f2"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"01d7"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"fee4"))(15 DOWNTO 0), to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0)); -- Signals CONSTANT clk_high : time := 5000000 ns; CONSTANT clk_low : time := 5000000 ns; CONSTANT clk_period : time := 10000000 ns; CONSTANT clk_hold : time := 10 ns; SIGNAL clk : std_logic; SIGNAL saturation_error : std_logic; SIGNAL reset : std_logic; SIGNAL filter_in : std_logic_vector(15 DOWNTO 0); SIGNAL filter_out : std_logic_vector(15 DOWNTO 0); BEGIN u_filter: fir generic map( Coef_Width_g => 8, NTAP_g => 9 ) port map( GLOBAL_CLK => clk, GLOBAL_RESET => reset, X_IN => filter_in, SATURATION_ERR => saturation_error, Y_OUT => filter_out); -- Block Statements clk_gen: PROCESS BEGIN clk <= '1'; WAIT FOR clk_high; clk <= '0'; WAIT FOR clk_low; END PROCESS clk_gen; reset_gen: PROCESS BEGIN reset <= '1'; WAIT FOR clk_period*2 + clk_hold; reset <= '0'; WAIT;

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END PROCESS reset_gen; filter_in_gen: PROCESS BEGIN filter_in <= filter_in_force(0); WAIT FOR clk_period*3 + clk_hold; filter_in <= filter_in_force(1); WAIT FOR clk_period; FOR n IN 0 TO 2407 LOOP IF n + 2 <= 2407 THEN filter_in <= filter_in_force(n + 2); END IF; WAIT FOR clk_period; END LOOP; ASSERT FALSE REPORT "**** Test Complete. ****" SEVERITY FAILURE; END PROCESS filter_in_gen; END test;

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APPENDIX D SYNTHESIS SCRIPTS The scripts for synthesis of the FIR filter using the STSCL library and standard CMOS library are given here. The scripts are written such that the designer can reuse them for synthesizing similar circuits only with making minor changes. CONTRAINTS FILE ################################################################################ # filter.constraints.tcl # # Synthesis constraints ################################################################################ set CLK_PERIOD 10000000 echo "################################################################################" echo "## ##" echo "## Loading constraints file 'filter.constraints.tcl' ##" echo "## ##" echo "## Clock period : CLK_PERIOD = $CLK_PERIOD ##" echo "## ##" echo "################################################################################" ## ## main clock create_clock -name "clk_c" -period $CLK_PERIOD -waveform { 0 5000000 } { GLOBAL_CLK } set_max_delay $CLK_PERIOD -from [all_inputs] -to [all_outputs] set_max_delay [expr 0.5 * $CLK_PERIOD] -from [all_inputs] -to [all_registers] set_max_delay [expr 0.5 * $CLK_PERIOD] -from [all_registers] -to [all_outputs] ## minimum area set_max_area 0 ## minimum power #set_max_leakage_power 0

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set_load [load_of ${TECH_LIB}/${LOADING_CELL}] [get_ports -filter {@port_direction == out}] set_driving_cell -library ${TECH_LIB} -lib_cell ${DRIVING_CELL} [get_ports -filter {@port_direction == in}] if { [info exists CLK_PERIOD] } { group_path -name in_paths -weight 1.0 -critical_range [expr 0.2 * $CLK_PERIOD] -from [all_inputs] -to [all_registers] group_path -name out_paths -weight 1.0 -critical_range [expr 0.2 * $CLK_PERIOD] -from [all_registers] -to [all_outputs] group_path -name reg_paths -weight 5.0 -critical_range [expr 0.2 * $CLK_PERIOD] -from [all_registers] -to [all_registers] } group_path -name dir_paths -weight 0.1 -critical_range 0.0 -from [all_inputs] -to [all_outputs]

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SCRIPT FOR SYNTHESIZING THE FIR FILTER USING THE STSCL CELL LIBRARY ####################################################################### ## setup ######################################################################## ## Configuration variables ## Technology / Cell library ## name of process set TECH_PROCESS umc_l180 ## name of cell library set TECH_LIB stscl ## revision of cell library set TECH_LIB_REV rev0 ## technology corner to use set TECH_CORNER tt_200m100p ## technology directory set TECH_DIR "$env(MCML_HOME)/libraries/${TECH_PROCESS}/${TECH_LIB}/${TECH_LIB_REV}" source "$env(MCML_HOME)/etc/setup_dc.tcl" echo "**** SETUP TECHNOLOGY $TECH_LIB CORNER $TECH_CORNER" lappend target_library "${TECH_DIR}/lib_s/liberty/${TECH_CORNER}/${TECH_LIB}-pg.db" #lappend physical_library "${TECH_DIR}/lib_s/liberty/${TECH_LIB}.pdb" lappend link_library "${TECH_DIR}/lib_s/liberty/${TECH_CORNER}/${TECH_LIB}-pg.db" set mw_reference_library "${TECH_DIR}/lib_s/milkyway/${TECH_LIB}_nn" set mw_tech_library "${TECH_DIR}/lib_s/milkyway/${TECH_LIB}_tech" ## Design ## design name set DESIGN fir set TOP_DIR "$env(MCML_HOME)/designs/${DESIGN}" set RTL_DIR "${TOP_DIR}/rtl" set RTL_FORMAT vhdl set RTL_FILES *.vhd set TOPLEVEL "${DESIGN}" ## parameters for RTL elaboration array set PARAMETERS {Coef_Width_g 8 NTAP_g 9} ## list of blocks, each is in a separate rtl file array set BLOCKS { fir rev0 } ## Output set OUTPUTDIR "./run/${DESIGN}.${TECH_LIB}/${TECH_CORNER}" set OUTPUTFILE "${TOPLEVEL}" ## Configuration source "$env(MCML_HOME)/etc/setup_dc.tcl" echo "**** SETUP TECHNOLOGY $TECH_LIB CORNER $TECH_CORNER"

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lappend target_library "${TECH_DIR}/lib_s/liberty/${TECH_CORNER}/${TECH_LIB}-pg.db" #lappend physical_library "${TECH_DIR}/lib_s/liberty/${TECH_LIB}.pdb" lappend link_library "${TECH_DIR}/lib_s/liberty/${TECH_CORNER}/${TECH_LIB}-pg.db" set mw_reference_library "${TECH_DIR}/lib_s/milkyway/${TECH_LIB}_nn" set mw_tech_library "${TECH_DIR}/lib_s/milkyway/${TECH_LIB}_tech" file mkdir work define_design_lib DEFAULT -path work #if { [shell_is_in_topographical_mode] } { #set use_pdb_lib_format true # set_utilization 0.8 # set OUTPUTDIR "${OUTPUTDIR}.topo" #} else { # set OUTPUTDIR "${OUTPUTDIR}.wl" #} #Assumption: shell is in the topographical mode set_utilization 0.8 set OUTPUTDIR "${OUTPUTDIR}.topo" if { ! [file isdir $OUTPUTDIR] } { exec mkdir -p $OUTPUTDIR } echo "" echo "========== SETUP ==========" echo "== DESIGN : $DESIGN" echo "== TOPLEVEL : $TOPLEVEL" echo "== LIBRARY : $TECH_LIB" echo "===========================" echo "" ## milkyway setup if { ! [file isdir "$OUTPUTDIR/milkyway"] } { exec mkdir -p "$OUTPUTDIR/milkyway" } set mw_design_library "${OUTPUTDIR}/milkyway/${OUTPUTFILE}" if { ! [file isdir $mw_design_library] } { create_mw_design $mw_design_library -tech_file "${mw_tech_library}.tf" } open_mw_lib $mw_design_library ################################################################################ ## read design files ################################################################################ ## build list of files to analyze #echo "Info: Scanning for RTL files to analyze (rtl_dir=${RTL_DIR}, design=${DESIGN})..." #set source_files {} #foreach {block} [array get BLOCKS] { # if { [file exists "${RTL_DIR}/${block}.vhd"] } { # echo "Info: Adding block '${block}'" # lappend source_files "${RTL_DIR}/${block}.vhd" # } else { # echo "Info: Ignoring block '${block}'" # } #}

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## read rtl files ## read_file -format ${RTL_FORMAT} -lib DEFAULT [glob -nocomplain "${RTL_DIR}/${RTL_FILES}"] analyze -format ${RTL_FORMAT} -lib DEFAULT [glob -nocomplain "${RTL_DIR}/${RTL_FILES}"] #current_design ${TOPLEVEL} ## ## parameter definitions ## if { [info exists PARAMETERS] } { echo "INFO: Elaborating block ${DESIGN} with parameters [array get PARAMETERS]" set params {} foreach {x y} [array get PARAMETERS] {lappend params "$x=$y"} elaborate $DESIGN -lib DEFAULT -parameters [join $params ","] } else { echo "INFO: Elaborating block ${DESIGN} without parameters" elaborate $DESIGN -lib DEFAULT } #current_design ${TOPLEVEL} ################################################################################ ## load constraints ################################################################################ set DRIVING_CELL INV_x8_0 set LOADING_CELL INV_x4_0/A source -echo -verbose "${DESIGN}.constraints.tcl" ################################################################################ ## insert bias / level converters ################################################################################ ## insert level converters #insert_level_converters -cell "${TECH_LIB}/S2DX32_0" -all_clocks #insert_level_converters -cell "${TECH_LIB}/S2DX17_0" -all_inputs #insert_level_converters -cell "${TECH_LIB}/D2SX8_0" -all_outputs ## insert bias circuit #insert_bias_circuit -cell "${TECH_LIB}/BIAS" -inst bias_generator ################################################################################ ## setup compile ################################################################################ set_cost_priority -delay set_fix_multiple_port_nets -all set_structure true -boolean true ## save elaborated database write -format ddc -hierarchy -output "${OUTPUTDIR}/${current_design}_elab.ddc" ungroup -small 1 uniquify ################################################################################ ## setup physical synthesis ########################################################################

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if { [shell_is_in_topographical_mode] } { set_preferred_routing_direction -layers {ME1 ME3 ME5} -direction horizontal set_preferred_routing_direction -layers {ME2 ME4 ME6} -direction vertical set_ignored_layers -min_routing_layer ME1 -max_routing_layer ME6 set_utilization 0.8 if { ![info exists env(RC_SCALE)] } { set RC_SCALE 1.05 } else { set RC_SCALE $env(RC_SCALE) } set_delay_estimation_options \ -min_unit_horizontal_capacitance_scaling_factor $RC_SCALE \ -min_unit_vertical_capacitance_scaling_factor $RC_SCALE \ -min_unit_horizontal_resistance_scaling_factor $RC_SCALE \ -min_unit_vertical_resistance_scaling_factor $RC_SCALE \ -max_unit_horizontal_capacitance_scaling_factor $RC_SCALE \ -max_unit_vertical_capacitance_scaling_factor $RC_SCALE \ -max_unit_horizontal_resistance_scaling_factor $RC_SCALE \ -max_unit_vertical_resistance_scaling_factor $RC_SCALE #source -echo -verbose "${TOPLEVEL}.floorplan.tcl" if { [sizeof_collection [all_clocks]] > 0 } { set_propagated_clock [all_clocks] } } else { ######################################################################## ## setup wireload models ######################################################################## ## to use P&R extracted wireloads if { [file exists "../par/run/${TOPLEVEL}.${TECH_LIB}/${OUTPUTFILE}.wl.flat"] } { read_lib "../par/run/${TOPLEVEL}.${TECH_LIB}/${OUTPUTFILE}.wl.flat" source "../par/run/${TOPLEVEL}.${TECH_LIB}/${OUTPUTFILE}.wl.flat.sdc" } report_wire_load } #set_optimize_registers true compile_ultra #set_optimize_registers false ## update level converters just in case # insert_level_converters -update -cell "honk_hi/S2DX32_0" -all_clocks #set_ungroup [get_designs * -filter "is_synlib_module==true"] #remove_unconnected_port -blast [get_cells -hier] #if { [shell_is_in_topographical_mode] } { # compile_ultra -incremental #} else { # compile -incremental -map_effort high -area_effort high #} write -format ddc -hierarchy -output "${OUTPUTDIR}/${OUTPUTFILE}.ddc" define_name_rules verilog -case_insensitive change_names -rules verilog -hierarchy write -format verilog -hierarchy -output "${OUTPUTDIR}/${OUTPUTFILE}.v" write_sdc -nosplit "${OUTPUTDIR}/${OUTPUTFILE}.sdc" write_sdf "${OUTPUTDIR}/${OUTPUTFILE}.sdf" write_milkyway -output ${OUTPUTFILE} -overwrite

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define_name_rules vhdl -case_insensitive change_names -rules vhdl -hierarchy write -format vhdl -hierarchy -output "${OUTPUTDIR}/${OUTPUTFILE}.vhdl" if { [shell_is_in_topographical_mode] } { write_physical_constraints -output "${OUTPUTDIR}/${OUTPUTFILE}.floorplan.tcl" } ## create reports redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.timing.rpt" {report_timing -path full_clock -delay max -nworst 10 -net -capacitance -sort_by slack} redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.area.rpt" {report_area -hierarchy} redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.reference.rpt" {report_reference -hierarchy} redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.power.rpt" {report_power} redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.constraint.rpt" {report_constraint -all_violators} redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.clock.rpt" {report_clock} redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.timing_requirements.rpt" {report_timing_requirements} ## create timing reports for individual path groups foreach_in_collection group [get_path_groups] { set group_name [get_attribute $group name] redirect -file "${OUTPUTDIR}/${OUTPUTFILE}.timing.${group_name}.rpt" \ "report_timing -group $group_name -path full_clock -nworst 10 -net -cap -sort_by slack" }

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SCRIPT FOR SYNTHESIZING THE FIR FILTER USING THE STANDARD CMOS LIBRARY analyze -library WORK -format vhdl {/home/beikahma/Projects/filter_CMOS/HDL/RTL/order4_9taps.vhd} elaborate FIR -architecture SPEED -library DEFAULT -parameters "Coef_Width_g = 8, NTAP_g = 9" set_operating_conditions -library fsa0m_a_generic_core_tc TCCOM create_clock -name "clk" -period 1e+07 -waveform { 0.000 5000000.000 } { GLOBAL_CLK } set_max_area 0 write -hierarchy -format ddc -output SYN/DB/fir_Coef_Width_g8_NTAP_g9_elaborated.ddc compile -map_effort high -area_effort high compile_ultra write -hierarchy -format ddc -output /home/beikahma/Projects/filter_CMOS/SYN/DB/fir_Coef_Width_g8_NTAP_g9_mapped.ddc report_area -nosplit change_names -hierarchy -rules vhdl -verbose write -hierarchy -format vhdl -output HDL/GATE/fir_Coef_Width_g8_NTAP_g9_mapped.vhdl write_sdf SYN/TIM/fir.sdf write_sdc -nosplit SYN/SDC/fir.sdc change_names -hierarchy -rules verilog -verbose write -hierarchy -format verilog -output HDL/GATE/fir_Coef_Width_g8_NTAP_g9_mapped.v

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APPENDIX E PLACEMENT AND ROUTING SCRIPT The script for placement and routing of the FIR filter using SoC encounter is given here. The script is written such that the designer can reuse it for the placement and routing of similar circuits only with making minor changes. source $env(MCML_HOME)/etc/setup_encounter.tcl ## Process if { ! [info exists env(PROCESS)] } { set env(PROCESS) umc_l180 } if { ! [info exists env(LIBRARY)] } { ## default stscl library ## set env(LIBRARY) stscl set env(LIB_REV) rev0 set env(CORNER) tt_200m100p } if { ! [info exists env(DESIGN)] } { set env(DESIGN) fir } if { ! [info exists env(DESIGN_REV)] } { set env(DESIGN_REV) rev0 } if { ![info exists env(TOPLEVEL)] } { set env(TOPLEVEL) $env(DESIGN) } set OUTPUTDIR "./run/$env(TOPLEVEL).$env(LIBRARY)" file mkdir $OUTPUTDIR set OUTPUTFILE $env(TOPLEVEL) set SYN_DIR "../syn/run/$env(TOPLEVEL).$env(LIBRARY)/$env(CORNER).topo" set_global timing_disable_clock_gating_checks true set env(USE_TOPO) 1 loadConfig [mcml::getConfigurationFile Default] ## Setup parasitics extraction setExtractRCMode -default if { ![info exists env(RC_SCALE)] } { set RC_SCALE 1.05 } else { set RC_SCALE $env(RC_SCALE) } if { ![info exists env(WL_SCALE)] } { set WL_SCALE 0.40 } else { set WL_SCALE $env(WL_SCALE) } setRCFactor -defcap $RC_SCALE -detcap $RC_SCALE -xcap $RC_SCALE ## Set dont_touches ## For toplevel only ##if { [llength [get_cells bias_generator]] } { ## puts "\n***\n***INFO: Setting dont_touches on the level converters !\n***\n" ## set_dont_touch [get_cells *_conv] ## set_dont_touch [get_cells *_conv_*] ## deleteBufferTree ## set_dont_touch [get_cells bias_generator]

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## dbForEachCellFTerm [dbgTopCell] termPtr { ## set_dont_touch [get_nets [dbFTermName $termPtr]] ## } ## set_dont_use [get_lib_cells $env(LIBRARY)/D2S*] ## set_dont_use [get_lib_cells $env(LIBRARY)/S2D*] ##} ## Save initial design saveDesign "$OUTPUTDIR/${OUTPUTFILE}.conf.enc" ## Setup Trial Route setTrialRouteMode -reset -highEffort -extendM1PinToM2 -ignoreDEFTrack -maxRouteLayer 4 timeDesign -prePlace -pathReports -drvReports -slackReports -numPaths 50 -prefix prePlace -outDir "${OUTPUTDIR}/${OUTPUTFILE}_reports" ## Setup floorplan set DEFAULT_WIDTH 1750 set DEFAULT_HEIGHT 1750 set DEFAULT_OFFSET 50 ## Setup floorplan if { ![info exists env(FP_OFFSET)] } { set fpOfs $DEFAULT_OFFSET } else { set fpOfs $env(FP_OFFSET) } if { ( ![info exists env(FP_WIDTH)] && ![info exists env(FP_HEIGHT)] ) } { ## extract floorplan size from synthesis results if { [file exists "${SYN_DIR}/${OUTPUTFILE}.area.rpt"] } { set area [exec sh -c "cat ${SYN_DIR}/${OUTPUTFILE}.area.rpt | grep -i 'Total cell area' | awk -F: '{ print strtonum(\$2) }'"] if { $area > 0 } { set AREA_FACTOR 1 set env(FP_WIDTH) [expr int(10*(1+int(sqrt($area*$AREA_FACTOR)/10.0)) + 2*$fpOfs)] set env(FP_HEIGHT) $env(FP_WIDTH) puts "################################################################################" puts "################################################################################" puts [format "## EXTRACTED FLOORPLAN SIZE : %5d x %5d ##" $env(FP_WIDTH) $env(FP_HEIGHT)] puts "################################################################################" puts "################################################################################" exec echo "$env(FP_WIDTH) x $env(FP_HEIGHT) = [expr $env(FP_WIDTH) * $env(FP_HEIGHT)]" > area.txt } } } if { ![info exists env(FP_WIDTH)] } { set fpWidth $DEFAULT_WIDTH } else { set fpWidth $env(FP_WIDTH) } if { ![info exists env(FP_HEIGHT)] } { set fpHeight $DEFAULT_HEIGHT } else { set fpHeight $env(FP_HEIGHT) }

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floorPlan -d $fpWidth $fpHeight $fpOfs $fpOfs $fpOfs $fpOfs set fpBox [dbFPlanBox [dbHeadFPlan]] set fpX [dbDBUToMicrons [dbBoxLLX $fpBox]] set fpY [dbDBUToMicrons [dbBoxLLY $fpBox]] set fpWidth [dbDBUToMicrons [dbBoxDimX $fpBox]] set fpHeight [dbDBUToMicrons [dbBoxDimY $fpBox]] if { [file exists $env(TOPLEVEL).io] } { loadIoFile $env(TOPLEVEL).io } ## Connect global nets globalNetConnect V_P -type pgpin -pin V_P -inst * -override -verbose globalNetConnect V_N -type pgpin -pin V_N -inst * -override -verbose globalNetConnect Vss -type pgpin -pin Vss -inst * -override -verbose globalNetConnect Vdd -type pgpin -pin Vdd -inst * -override -verbose ## Create rings editSelect -net * editDelete -selected addRing -around core -nets {Vdd Vss} -width_left 5.0 -width_right 5.0 -width_top 5.0 -width_bottom 5.0 -spacing_left 2.4 -spacing_right 2.4 -spacing_top 2.4 -spacing_bottom 2.4 -offset_left 4.8 -offset_right 4.8 -offset_top 4.8 -offset_bottom 4.8 -layer_left ME2 -layer_right ME2 -layer_top ME1 -layer_bottom ME1 -stacked_via_top_layer ME5 -stacked_via_bottom_layer ME1 addRing -around core -nets {V_P V_N} -width_left 3.6 -width_right 3.6 -width_top 4.0 -width_bottom 4.0 -spacing_left 2.4 -spacing_right 2.4 -spacing_top 2.4 -spacing_bottom 2.4 -offset_left 29.6 -offset_right 29.6 -offset_top 29.6 -offset_bottom 29.6 -layer_left ME2 -layer_right ME2 -layer_top ME1 -layer_bottom ME1 -stacked_via_top_layer ME5 -stacked_via_bottom_layer ME1 #set stripeWidth 18 #set stripeSpc 2.4 #set numStripes 1 #for { set i 1 } { $i <= $numStripes } { incr i } { # set stripeX [expr 0.1 * int( 10 * ([expr $i * ($fpWidth - 2 * $fpOfs ) / (1 + $numStripes)] - $stripeWidth - 0.5 * $stripeSpc) )] # puts "*** ADDING STRIPE $i AT $stripeX" # addStripe -nets {Vdd Vss} -width $stripeWidth -spacing $stripeSpc -layer ME4 -number_of_sets 1 -xleft_offset $stripeX #} ## Place Floorplan addHaloToBlock 21.6 2.4 21.6 2.4 -allBlock setPlaceMode -reset setPlaceMode -noTimingDriven -modulePlan placeDesign refinePlace addHaloToBlock 9.6 0 9.6 0 -allBlock sroute -stopStripeSCPin none -stopBlockPin boundaryWithPin -straightConnections { straightWithDrcClean straightWithChanges } setBlockPlacementStatus -name bias_generator -status fixed editPowerVia -add_vias timeDesign -preCTS ## Place design setBufFootPrint NBUF_0 setDelayFootPrint NBUF_0 setInvFootPrint INV_0 setPlaceMode -reset

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setPlaceMode -modulePlan -timingDriven -congHighEffort placeDesign saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_placed.enc" ########################################################## # set_disable_timing setOptMode -reset -noUsefulSkew -yieldEffort none -highEffort -maxDensity 0.95 -setupTargetSlack 0.0 -simplifyNetlist if { [info exists env(USEFUL_SKEW)] } { setOptMode -usefulSkew } optDesign -preCTS #optDesign -preCTS -incr timeDesign -preCTS -pathReports -drvReports -slackReports -numPaths 50 -prefix "preCTS" -outDir "${OUTPUTDIR}/${OUTPUTFILE}_reports" #report_timing -to toplevel/dec_out_reg\[*\]/D saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_placed_opt.enc" # creating the clock #createClockTreeSpec -output ${OUTPUTFILE}.ctstch -bufFootprint NBUF_0 -invFootprint INV_0 setCTSMode -useCTSRouteGuide -topPreferredLayer 4 -bottomPreferredLayer 2 -leafTopPreferredLayer 4 -leafBottomPreferredLayer 2 -optAddBuffer -noRouteClkNet #if { [info exists env(USEFUL_SKEW)] } { # specifyClockTree -clkfile [getSchedulingFile] #} #specifyClockTree -clkfile ${OUTPUTFILE}.ctstch clockDesign -specFile Clock.ctstch -outDir "${OUTPUTDIR}/${OUTPUTFILE}_reports" # saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_cts.enc" setExtractRCMode -default extractRC rcOut -spef "${OUTPUTDIR}/${OUTPUTFILE}_default.spef" setExtractRCMode -detail setRCFactor -detcap 1.0 -xcap 1.0 extractRC rcOut -spef "${OUTPUTDIR}/${OUTPUTFILE}_detail.spef" exec sh -c "spefCapCmp.pl -ref ${OUTPUTDIR}/${OUTPUTFILE}_default.spef -cmp ${OUTPUTDIR}/${OUTPUTFILE}_detail.spef 2>/dev/null ; exit 0" set result [exec grep {Suggested Capacitance Scale Factor} spefCapCmp.rpt] regexp {[\d.]+} $result rcFactor puts "*****************************************" puts "***** Extracted RC Factor : $rcFactor *****" puts "*****************************************" setRCFactor -detcap $rcFactor -xcap $rcFactor extractRC setCteReport setAttribute -net * -bottom_preferred_routing_layer 2 writeDesignTiming .timing_file.tif verifyGeometry verifyConnectivity -type regular -error 1000 -warning 50 freeTimingGraph

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globalDetailRouteBatch ### ### Re-generate cap scaling factors for detail routing ### setExtractRCMode -default extractRC rcOut -spef "${OUTPUTDIR}/${OUTPUTFILE}_default.spef" setExtractRCMode -detail setRCFactor -detcap 1.0 -xcap 1.0 extractRC rcOut -spef "${OUTPUTDIR}/${OUTPUTFILE}_detail.spef" exec sh -c "spefCapCmp.pl -ref ${OUTPUTDIR}/${OUTPUTFILE}_default.spef -cmp ${OUTPUTDIR}/${OUTPUTFILE}_detail.spef 2>/dev/null ; exit 0" set result [exec grep {Suggested Capacitance Scale Factor} spefCapCmp.rpt] regexp {[\d.]+} $result rcFactor puts "*****************************************" puts "***** Extracted RC Factor : $rcFactor *****" puts "*****************************************" setRCFactor -detcap $rcFactor -xcap $rcFactor setCteReport writeDesignTiming .timing_file.tif saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_routed.enc" ### generating the sdf file delayCal -sdf "${OUTPUTDIR}/${OUTPUTFILE}_routed.sdf" -idealclock ## writing verilog file saveNetlist "${OUTPUTDIR}/${OUTPUTFILE}_routed.v" -excludeLeafCell timeDesign -postRoute optDesign -postRoute -setup timeDesign -postRoute -pathReports -drvReports -slackReports -numPaths 50 -prefix postRoute -outDir "${OUTPUTDIR}/${OUTPUTFILE}_reports" saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_routed_opt.enc" saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_routed_opt_done.enc" mcml::saveDesignData -rev 0 -type s -design ${OUTPUTFILE} -netStat:plot ## Fix t-shape connections setNanoRouteMode -quiet \ -drouteWrongWayLayerCost {32 32 32 32 32} #droute::tshape::fixTShapeWires #optDesign -postRoute -setup -hold ## Delete remaining t-shapes droute::tshape::deleteTShapeWires ## Delete wrong-way wires ## droute::tshape::deleteWrongWayWires -layer {2 3 4} ## droute::tshape::deleteWrongWayWires -layer {2} saveNetlist "${OUTPUTDIR}/${OUTPUTFILE}_ss.v" -excludeLeafCell defOut "${OUTPUTDIR}/${OUTPUTFILE}_ss.def" -floorplan -routing -noTracks

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set output {} # split both # removed option : --no_split_ports \ catch { exec split_wires \ -l "$env(MCML_HOME)/libraries/$env(PROCESS)/$env(LIBRARY)/$env(LIB_REV)/lib_d/lef/$env(LIBRARY)_tech.lef" \ -i "${OUTPUTDIR}/${OUTPUTFILE}_ss.def" \ -o "/tmp/${OUTPUTFILE}_dd.def" } output puts $output ## catch { exec sh -c "cat /tmp/${OUTPUTFILE}_dd.def | sed 's/\\(VERSION\\s*\\)5\\.5/\\15.6/' | sed 's/\\(NAMESCASESENSITIVE\\s*\\)OFF/\\1ON/' > ${OUTPUTDIR}/${OUTPUTFILE}_dd.def ; rm /tmp/${OUTPUTFILE}_dd.def ; exit 0" } # removed option : -p [dbCellName [dbgTopCell]] \ catch { exec vss2dd \ -i Vdd,Vss,V_N,V_P \ -o "${OUTPUTDIR}/${OUTPUTFILE}_dd.v" \ "${OUTPUTDIR}/${OUTPUTFILE}_ss.v" } output puts $output saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_ss_done.enc" freeDesign set env(DIFFERENTIAL) 1 loadConfig [mcml::getConfigurationFile Default] clearGlobalNets globalNetConnect V_P -type pgpin -pin V_P -inst * -override -verbose globalNetConnect V_N -type pgpin -pin V_N -inst * -override -verbose globalNetConnect Vss -type pgpin -pin Vss -inst * -override -verbose globalNetConnect Vdd -type pgpin -pin Vdd -inst * -override -verbose globalNetConnect Vdd -type tiehi -inst * -verbose globalNetConnect Vss -type tielo -inst * -verbose floorPlan -d $fpWidth $fpHeight $fpOfs $fpOfs $fpOfs $fpOfs defIn "${OUTPUTDIR}/${OUTPUTFILE}_dd.def" addHaloToBlock 9.6 0 9.6 0 -allBlock sroute -noPadRings -noPadPins -jogControl { preferWithChanges differentLayer } -nets {Vdd Vss V_N V_P} -layerChangeTopLayer 3 # Route #droute::fixwires::fixWires #setNanoRouteMode drouteWrongWayLayerCost {32 32 32 32 32} #setNanoRouteMode -drouteWrongWayLayerCost {2 32 4 4 4} setNanoRouteMode \ -drouteFixAntenna false \ -routeWithEco true \ -routeBottomRoutingLayer 1 \ -routeTopRoutingLayer 6 \ -drouteEndIteration 6 #globalDetailRouteBatch

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saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_pass1_dd.enc" globalDetailRouteBatch saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_pass2_dd.enc" verifyConnectivity -noAntenna -report "${OUTPUTDIR}/${OUTPUTFILE}_reports/verifyConnectivity.rpt" checkDrc ## save final database saveDesign "${OUTPUTDIR}/${OUTPUTFILE}_final_dd.enc" ## save design data mcml::saveDesignData -rev 0 -type d -design ${OUTPUTFILE} -netStat:plot

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APPENDIX F VERILOG-A CODE FOR CONVERTING THE ANALOG OUTPUTS OF THE STSCL TEST CIRCUIT INTO DIGITAL HEXADECIMAL CODE ̀include "constants.vams" `include "disciplines.vams" module DataLogger(Ain, nAin, CLK, nCLK, Dout, gRef); //gRef is the Reference voltage input [0:15] Ain, nAin; output Dout; input CLK, nCLK, gRef; electrical [0:15] Ain, nAin; electrical CLK, nCLK, gRef, Dout; electrical [0:15] sAin; integer fileDesc; real sampCLK; real sampOut; real sampData [0:15]; analog begin @(initial_step) begin if (analysis("tran")) fileDesc = $fopen("./firADC_%D_%T.txt", "a"); end // if (analysis("tran")) begin sampCLK = V(CLK)-V(nCLK); V(Dout,gRef) <+ 0.0; @(cross(sampCLK, -1)) begin sampData[0] = ( V(Ain[0]) - V(nAin[0]) > 0.0) ? 1 : 0; sampData[1] = ( V(Ain[1]) - V(nAin[1]) > 0.0) ? 1 : 0; sampData[2] = ( V(Ain[2]) - V(nAin[2]) > 0.0) ? 1 : 0; sampData[3] = ( V(Ain[3]) - V(nAin[3]) > 0.0) ? 1 : 0; sampData[4] = ( V(Ain[4]) - V(nAin[4]) > 0.0) ? 1 : 0; sampData[5] = ( V(Ain[5]) - V(nAin[5]) > 0.0) ? 1 : 0; sampData[6] = ( V(Ain[6]) - V(nAin[6]) > 0.0) ? 1 : 0; sampData[7] = ( V(Ain[7]) - V(nAin[7]) > 0.0) ? 1 : 0; sampData[8] = ( V(Ain[8]) - V(nAin[8]) > 0.0) ? 1 : 0; sampData[9] = ( V(Ain[9]) - V(nAin[9]) > 0.0) ? 1 : 0; sampData[10] = ( V(Ain[10]) - V(nAin[10]) > 0.0) ? 1 : 0; sampData[11] = ( V(Ain[11]) - V(nAin[11]) > 0.0) ? 1 : 0;

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sampData[12] = ( V(Ain[12]) - V(nAin[12]) > 0.0) ? 1 : 0; sampData[13] = ( V(Ain[13]) - V(nAin[13]) > 0.0) ? 1 : 0; sampData[14] = ( V(Ain[14]) - V(nAin[14]) > 0.0) ? 1 : 0; sampData[15] = ( V(Ain[15]) - V(nAin[15]) > 0.0) ? 1 : 0; sampOut = (sampData[0] + 2*sampData[1]+ 4*sampData[2]+ 8*sampData[3]+ 16*sampData[4]+ 32*sampData[5]+ 64*sampData[6]+ 128*sampData[7]+ 256*sampData[8]+ 512*sampData[9]+ 1024*sampData[10]+ 2048*sampData[11]+ 4096*sampData[12]+ 8192*sampData[13]+ 16384*sampData[14]+ 32768*sampData[15]); // $fstrobe(fileDesc, "%f\t", sampOut); end V(Dout,gRef) <+ 0.2*(sampOut/65535.0); end // @(final_step) begin if (analysis("tran")) $fclose(fileDesc); end end endmodule