Detector Performance Improvements using Wafer Thinning and ...scipp.ucsc.edu/seminars/DISCO_UCSC.pdf · ©2010 DISCO CORPORATION All rights reserved OR How we destroy your perfectly

©2010 DISCO CORPORATION All rights reserved

DISCODetector Performance

Improvements using Wafer Thinning and Singulating

Techniques


ORHow we destroy your

perfectly good devices and what we are doing to fix

them.


3/24Standard Process Flow

Incident energy Incident energy Incident energy

Front-illuminated, n-channel on p-type, low-resistivitysilicon

Back-illuminated, n-channel on p-type, low-resistivity silicon

Thick, fully depleted,back-illuminated p-channel on n-type high resistivity silicon


Thinning: As Grown vs. Ground4/24

Stress maps


Subsurface Damage vs. Grit Size

0

1

2

3

4

5

6

7

8

0 5 10 15 20 25 30

Diamond Grit Size (µ)

Subs

urfa

ce D

amag

e (µ

)

Wafer Edge

Wafer Center

IF-01-1-5/10-B-K01

IF-01-1-5/10-V

IF-01-1-4/6-B-K01

RS-03-2-2/4-P

IF-01-1-8/20-V

IF-01-1-8/20-B-K01

IF-01-1-20/30-V

IF-01-1-20/30-B-K01

5/24


Subsurface Damage: Removal

#2000 Poligrind

Ultra Poligrind MCP/CMP

Around 200 nm

Around 50 nm

Etch

6/24


After Wet Etching

Note: Selective polish to stop at SiO2su surface

Bonding

Si ：2 to 5µm

Adhesive: 0.1 to 1µm

Process stop above oxidation

Thin layer final thickness （Si：10µm or less）Bonding

SOI Wafer BG → CMP

Epi / Bulk Wafer BG → CMP

SOI method

Epi/Bulk method

Issues

Method SOI EPI / Bulk

Approx.775 µm removal is required

Final thickness less than 10 µm is requiredＢＧ

Process STOP just above oxidation Good TTV(BG/CMP)

CMP End Point Detection

Cleaning High level cleaning (Particle and metal)

Enhanced thinning process accuracy

is needed

Thinning Process for BSI 7/24


Wafers Trap and Hold Defects/Metals

Cross-section of wafer following:1) 5 hr 1100 ºC anneal to out-diffuse oxygen to the surface.2) 9 hr 650 ºC anneal to nucleate precipitates in wafer bulk.3) CMOS simulation to grow precipitates.

Denuded Zone

Intrinsic Gettering

8/24


How Stress Relief Causes Failures

Device layerAtomic metal and crystal defects

Backgrind layer stress holds onto defects

Stress relieved back sideAllows defects to reach the active area

Backside Oxidized layer

9/24


10/24Cleaning Process for TSVs

DIW

DIWChelate liquid*

1. Brush Module 2. Spin Module

Wafer

DIWBTA

Metal

Si wafer

Brush

Si wafer

Slurry residue removal

Atomizing nozzle

Atomizing nozzle Cleaning

Both side brush cleaning (Chelate agent)

Small particle removal

Siウェーハ

Dry

Chelate liquid*

Hydrophilized surface

Chelate liquid*

Metal contamination removal

CuOx and metal complex is made and removal （No Cu etching）

Brush

Si wafer

Pen brush cleaning

（Chelate agent or DIW）

BTA Rinse

Si wafer

Cu surface and BTA are combined for anti-corrosion.

Si wafer

Particle/ BG debris removal


NCG Only Looks at the Device

Device WaferActive AreaAdhesive

120～770um

10um～

～5um

～5um

Probe

Carrier

11/24


12/24Thickness Uniformity for TSV/BSI

Z3

Sensor

Casing

Isolation valveWater supply

SludgeWater mist Wheel

Chuck table

Wafer

Laser beam

bf　TTV 0.55 af　TTV 0.5bf　TTV 0.79 af　TTV 3.04


13/24Standard Process Flow

Dicing


14/24

•Chipping Leads to:•Particles•Crack Initiation Points•Large distance between active areas

Crack also occurs ahead of the blade

Thin Wafers Chip Easily


DBG for Less Chipping: Thinner Kerf

1. Half cut dice2. Tape lamination3. Grind4. Stress relief5. Tape mount

1 432

5

4

X 50 X 200

Standard Dicing

DBG

X 50 X 200

15/24


16/24Narrow Kerf for RFID: SD

After expanding

200μm

Before expanding

20μm


17/24Stealth Dicing

• Stealth dicing (SD)• No Particles• Clean edges • Small distance between active areas

Short pulse laser

Focus lens

Wafer

SD layer

Process flow

Pick upExpandBreakingLaserMounting on tape Tape

transfer


18/24SD Results(t 90 um): Sharp Edge

350 um

Top side photo: after breaking and tape expansion

（Optical microscope）

SD layer

•Kerf is zero•Distance to active area ~8um•Kerf is zero•Distance to active area ~8um


19/24Non Linear Cutting of Multi Reticle Wafers

Laser output

Cut time per line

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFFOFF

Si

ONOFF

SD layer

Mechanism of HASEN cutting

LaserON

LaserOFF

LaserON

Example of HASEN cutting (Side view)

SD layer


20/24Non Linear Cutting of Arrays

Arrangement of wafer die


Process for Array Die

200 μm200 μm

L shape T shape

200 μm200 μm

断面

100 μm100 μm

Laser30 µm

Cut surface

The numbers of die increased

1 23 45 6

1 2

6 73 4 5

21/24


Fun Shapes with SD

• Processing of non rectangular die– By combining linear cuts polygons can be cut

• Application of HASEN cutting– Many different shapes of die can be processed, as long as it is a

combination of the straight lines

Polygon die

Hansen cutting22/24


Summary

• Front side or back side imagers• Stress control• Metals control• Thickness uniformity• Reducing space between detectors• Particles• Strength• Non-linear cutting

23/24


END

24/24

Documents

Detector Performance Improvements using Wafer Thinning and ...scipp.ucsc.edu/seminars/DISCO_UCSC.pdf · ©2010 DISCO CORPORATION All rights reserved OR How we destroy your perfectly