Upload
others
View
6
Download
0
Embed Size (px)
Citation preview
Detection of and Protection against
Plasma Charging Damage in
Modern IC Technology
Promotiecommissie Voorzitter: Prof. dr. A. Bagchi Univ. Twente / EWI Promotor: Prof. dr. ir. F. G. Kuper Univ. Twente / EWI Assistent-promotor: Dr. ir. C. Salm Univ. Twente / EWI Leden: Prof. dr. J. Schmitz Univ. Twente / EWI Prof. dr. ir. A. J. Mouthaan Univ. Twente / EWI Prof. dr. ir. H. Maes KU Leuven Belgium Dr. ind. ing. J. G. G. Ackaert AMI Semiconductor Belgium
The research described in this thesis was funded by the Dutch Technology Foundation
(STW). The research was carried out at Semiconductor Components (SC) group, MESA+
research institute/University of Twente, The Netherlands; Philips Semiconductors,
Nijmegen, The Netherlands; and AMI Semiconductor, Oudenaarde, Belgium.
Print: PrintPartners Ipskamp, Enschede, The Netherlands
© Zhichun Wang, Enschede, 2004
No part of this work may be reproduced by print, photocopy or any other means without the
permission in writing from the publisher.
ISBN 90-365-2079-7
DETECTION OF AND PROTECTION AGAINST
PLASMA CHARGING DAMAGE IN
MODERN IC TECHNOLOGY
PROEFSCHRIFT
ter verkrijging van
de graad van doctor aan de Universiteit Twente,
op gezag van de rector magnificus,
prof.dr. F.A. van Vught,
volgens besluit van het College voor Promoties
in het openbaar te verdedigen
op vrijdag 17 september 2004 om 15.00 uur
door
Zhichun Wang
geboren op 9 augustus 1973
te Hunan, China
Dit proefschrift is goedgekeurd door
de promotor Prof. dr. ir. F. G. Kuper en
de assistent-promotor Dr. ir. C. Salm
‘You have to have a dream so you can get up in the morning.’
-- Billy Wilder
To Liquan, Daniel and Michelle
CONTENTS Chapter 1 Introduction ........................................................................................1 1.1 Plasma basics................................................................................................................. 2
1.1.1 What is plasma?....................................................................................................... 2 1.1.2 The important role of plasma in IC technology ....................................................... 2 1.1.3 Problems of plasma process .................................................................................... 3
1.2 What is plasma charging damage?................................................................................. 4 1.3 History and future of plasma charging damage.............................................................. 5 1.4 Motivation of this work ................................................................................................. 7 1.5 Outline of the thesis ....................................................................................................... 8 1.6 References ..................................................................................................................... 9
Chapter 2 Mechanisms of Plasma Charging Damage during Plasma Etching...............................................................................................13
2.1 Introduction ................................................................................................................. 14 2.2 Plasma charging damage by the spatial nonuniformity of plasma ............................... 14 2.3 Electron shading effect ................................................................................................ 16 2.4 AC effects .................................................................................................................... 18 2.5 Summary...................................................................................................................... 18 2.6 References ................................................................................................................... 18
Chapter 3 Characterization of Plasma Charging Damage.............................21 3.1 Introduction ................................................................................................................. 22 3.2 Direct measurements of damage in the devices ........................................................... 22
3.2.1 Antenna test structures........................................................................................... 22 3.2.2 Measurement techniques for test structures ........................................................... 26
3.3 Plasma property measurements.................................................................................... 46 3.3.1 Langmuir probe ..................................................................................................... 46 3.3.2 Plasma damage monitor (PDM) tool ..................................................................... 47
3.4 Challenge in the future................................................................................................. 48 3.5 Conclusions ................................................................................................................. 49 3.6 References ................................................................................................................... 49
Chapter 4 Plasma Charging Damage Affected by Antenna Ratio.................53 4.1 Introduction ................................................................................................................. 54 4.2 Experimental................................................................................................................ 55 4.3 Relation between failure fraction and antenna ratio..................................................... 57
4.3.1 Relation between the charging current and antenna ratio ...................................... 57 4.3.2 Relation between yield loss and antenna ratio ....................................................... 60
4.4 Application to IC’s ...................................................................................................... 62 4.5 Conclusions ................................................................................................................. 62 4.6 References ................................................................................................................... 62
Contents ii
Chapter 5 Reliability Effects .............................................................................65 5.1 Introduction ................................................................................................................. 66 5.2 Plasma latent damage demonstrated by SL and ML test structures ............................. 67
5.2.1 SL and ML test structures...................................................................................... 67 5.2.2 Results and discussions of SL and ML test structures ........................................... 68
5.3 Reliability test on MOS transistors with different antenna ratios ................................ 71 5.4 Conclusions ................................................................................................................. 73 5.5 References ................................................................................................................... 73
Chapter 6 Design Strategy and Protection Scheme.........................................75 6.1 Introduction ................................................................................................................. 76 6.2 Temperature effect on protection diode....................................................................... 76
6.2.1 Introduction ........................................................................................................... 76 6.2.2 Experimental details .............................................................................................. 77 6.2.3 Results and discussion........................................................................................... 79 6.2.4 Summary................................................................................................................ 83
6.3 Self-balancing interconnect layout............................................................................... 83 6.3.1 Introduction ........................................................................................................... 83 6.3.2 Experimental details .............................................................................................. 84 6.3.3 Results and discussions ......................................................................................... 86 6.3.4 Mechanism ............................................................................................................ 89 6.3.5 Summary................................................................................................................ 92
6.4 Conclusions ................................................................................................................. 93 6.5 References ................................................................................................................... 93
Chapter 7 Plasma Charging Damage of Floating Metal-Insulator-Metal Capacitors..........................................................................................95
7.1 Introduction ................................................................................................................. 96 7.2 Experimental................................................................................................................ 97
7.2.1 MIM capacitor processing..................................................................................... 97 7.2.2 Test structures ....................................................................................................... 98 7.2.3 Measurement ......................................................................................................... 99
7.3 Results and discussion ................................................................................................. 99 7.3.1 AR(T/D) and AR(T/B)................................................................................................. 99 7.3.2 Impact of the antenna area................................................................................... 101 7.3.3 Impact of the antenna perimeter .......................................................................... 101 7.3.4 Source of the damage .......................................................................................... 102 7.3.5 Effect of diode protection.................................................................................... 104
7.4 Damage model ........................................................................................................... 105 7.5 Layout solutions......................................................................................................... 108
7.5.1 Using metal bridges to limit interconnection line connected to one of the two plates of the floating MIM capacitor ................................................................... 108
7.5.2 Using protection diodes to drain the charging from the dielectric of the floating MIM capacitor..................................................................................................... 108
7.5.3 Using first order self-balancing interconnect layout design................................. 110
Contents
iii
7.6 Design rules ............................................................................................................... 110 7.7 Conclusions ............................................................................................................... 110 7.8 References ................................................................................................................. 111
Chapter 8 Concluding Remarks.....................................................................113 8.1 Concluding remarks................................................................................................... 114
8.1.1 Detection of plasma charging damage................................................................. 114 8.1.2 Protection against plasma charging damage ........................................................ 115
8.2 Original contributions of this thesis ........................................................................... 117 8.3 References ................................................................................................................. 118
Summary .....................................................................................................119
Samenvatting .....................................................................................................121
Abbreviations and Acronyms.............................................................................123
List of Publications .............................................................................................125
Awards .....................................................................................................127
Acknowledgements..............................................................................................129
Contents iv
Chapter 1 Introduction
A short introduction into the world of plasma charging damage is given in this chapter. First, a general introduction concerning the plasma itself, the inevitable role and the challenge of plasma processes in the semiconductor industry are presented. Next, the characterization and the source of plasma charging damage are explained, followed by an overview of the history and the future of plasma charging damage. Finally, the motivation and the outline of the thesis are presented.
Chapter 1
2
1.1 Plasma basics
1.1.1 What is plasma?
Plasma is a mixture of ions (positive and negative), electrons and neutrals in a
quasi-neutral gaseous steady state, sustained by an energy source that balances the
loss of charged particles. Plasma is sometimes called the fourth state of matter,
other than gas, liquid and solid.
1.1.2 The important role of plasma in IC technology
Plasmas are key for enabling technology in modern ultra-large scale integrated
(ULSI) circuit manufacturing. Since the modern ULSI circuit consists of 107-108
transistors, the back-end-of-line (BEOL) metallization process with a multi-level
interconnection of these transistors is a major technological challenge. Figure 1.1
shows such a multi-level interconnection. The metallization encompasses intra-
level and inter-level connections, the so-called lines and via's. These structures are
fabricated by sequential deposition, patterning, etching and polishing of metal and
insulator layers. These advanced multi-level interconnections can only be made by
using high-density plasma-enhanced deposition and etching techniques.
10 µm
Figure 1.1: Scanning electron microscope (SEM) graph of a partially completed SRAM array containing 6 device memory cells. The insulator oxide films have been removed. Courtesy of AMI Semiconductor.
Introduction
3
The plasma allows chemical reactions to occur at low temperature. It is being
used in the semiconductor industry intensively for deposition and patterning
purposes. High density plasma equipment enables an improved gap filling into the
narrow trenches and allows anisotropic etching that is needed to define submicron
metal lines with vertical side walls. Because of these advantages, the number of
plasma processing steps increases with each generation of technology. In state of
the art silicon integrated circuit (IC) manufacturing process, plasma is used in
more than 20 critical steps. The following are some chemical reaction examples in
plasma deposition and plasma etching. In the case of plasma enhanced chemical
vapour deposition (PECVD), some precursor gases react on the wafer surface thus
producing a layer, for example SiH4(gas) + 2O2(gas) SiO2(solid) + H2O(gas).
This chemical reactions result in an inter-metal dielectric (IMD). For etching, solid
material has to be converted into a gaseous state, for example the reaction
2Al(solid) + 3Cl2(gas) Al2Cl6(gas) is occurring when patterning a metal layer.
1.1.3 Problems of plasma process
Plasma processing is inevitable in modern IC technology, but it also generates a
number of problems because it is a very harsh environment to IC products. In order
to promote the throughput or to meet the critical requirements of deep-submicron
manufacturing, process tools with high plasma current density, such as high-
density plasma (HDP) reactors for etching and deposition applications, are
increasingly used. Exposing a wafer to these plasma steps can result in a wide
variety of damages to the material which good circuit performance relies upon.
Charging damage is one of the many types of damage that can happen.
As the wafer with ICs is exposed to the plasma, the net current density on the
wafer is of the order of 1-10 mA/cm2 and could cause a positive or negative stress.
Long interconnect lines leads can amplify this current to 1-10 A/cm2 at the device
[Kri98]. The collected net charges are fed to the gate where it is neutralized by the
current tunneling across the gate-oxide. The long interconnect lines, in a rough
sense, is a current multiplier that amplifies the tunneling current density across the
gate-oxide. The long interconnect lines acts as an amplifier and therefore called as
“antenna”. The effect of amplifying the tunnelling current density across the gate-
oxide is the so called “antenna effect”. Clearly, the area of the antenna exposed to
the plasma plays a role in determining the magnitude of the net charge collection.
The area ratio of antenna to the oxide under the gate is defined as “antenna ratio”
(AR). The typical AR range in modern IC processes is 10 to 1000. AR is an
Chapter 1
4
important parameter, which determines the severity of the damage. For identical
device and plasma process, the larger the AR, the more severe damage the device
will suffer. The device charging time is from 5 to 100 seconds with temperature in
the region of 50 to 4000C [Che01].
Plasma generates an unintended high-field which stresses and degrades the
underlying thin gate oxide layer of the metal-oxide-silicon (MOS) transistors and
non-volatile memories (NVM) such as electrically-erasable-and-programmable-
read-only-memories (EEPROMs) [Kri96]. Plasma charging damage also degrades
the insulator of metal-insulator-metal (MIM) capacitors. MOS, NVM and MIM
capacitors are major elements which form IC’s. Therefore the yield and reliability
of these products are degraded by plasma charging damage [And97, Har98, Luc98,
and Gup97]. How to detect, control and reduce plasma charging damage is a
challenge in modern IC technology. Interest in plasma charging damage has
persisted to the present day, where it still remains a troublesome reliability issue,
as reflected by the many publications and conference sessions devoted to it each
year.
1.2 What is plasma charging damage?
Plasma charging damage refers to the unintended high-field stressing of the
gate-oxide in MOS during plasma processing.
A high electric field develops across the gate and substrate of a metal-oxide-
semiconductor (MOS) during plasma processing, forcing the charges through the
metal lines and the underlying gate oxide. Figure 1.2 illustrates the process.
Introduction
5
M1
M2
M3
M4 metal interconnects
gate oxide
transistor transistor transistor
Plasma Current
a b c i
M4
d
a b c d
Figure 1.2: Schematic view of discharging paths during plasma etching of metal4 (M4).
This high electrical field that stresses the underlying gate oxide during plasma
processing basically comes from three sources. First is the nonuniform global
distribution of plasma potential across the wafer [Kaw85, Fan92], second is the
charge filtering (shading) due to microscopic topography on the wafer [Has93,
Has94], and third is the AC effects due to the nature of RF discharge that sustains
the plasma [Che00a]. Early observations pointed plasma nonuniformity as the root
cause of damage. This led to improvements in process tools, significantly reducing
the importance of global plasma nonuniformity as the root cause of the problem. In
recent years with every new generation, the IC dimensions have shrunk and the
aspect ratios have increased. At the same time the more uniform plasmas have
eliminated global plasma non-uniformity as a cause for plasma charging. For these
modern processes, electron shading (ES) has emerged as the major cause of
charging damage [Vah97]. Countless papers have confirmed this ES effect and its
fundamental nature. The mechanism of ES will be explained in details in Chapter
2. The stress voltages due to AC effects are quite small in most cases and cannot
cause damage by themselves. They do, however, add to the magnitude of stress
voltages developed by either nonuniform plasma potential or topographic filtering
of charge or the sum of both.
1.3 History and future of plasma charging damage
When plasma processing was first introduced in silicon IC manufacturing, the
research on plasma damage was focused on physical damage to crystalline silicon
by energetic ions and electrical damage to silicon dioxide (SiO2) and its interface
Chapter 1
6
by energetic photons. Later on, the plasma charging damage emerged and became
more and more important as the IC industry migrates towards ever-finer geometry.
Plasma charging damage was first reported in the early 1980’s [Yos83, Wat84].
At that time, the gate-oxide was over 20 nm thick. To cause significant degradation
in such thick oxide, voltages in excess of 20 V are required. Such a large voltage
can only come from extremely nonuniform plasma, a rarity even at that time. As
technology advances, the gate-oxide thickness shrinks, so does the voltage
required to damage it. The observation of plasma charging damage increases
steadily over time. The 0.35 µm and the 0.25 µm generations of technology seem
to suffer the most from plasma charging damage. From the 0.35 µm technology
generation on ward, most plasma processing systems had changed from batch type
processing to single wafer processing. Typical single wafer processing plasma has
a density of about 100 times higher than the typical batch processing plasma.
Additionally, for these technologies, the gate-oxide thickness was reduced to 6 to 8
nm, and the voltage required to damage them is in the range of 7 to 9 V [Che01].
The combined effect of the lower required damage voltage and the migration to
high-density plasma leads to a widespread plasma charging damage problem. Since
then significant progress has been made in the understanding of the mechanisms of
plasma charging damage, as well as the methods of damage detection [Che00a].
One would expect that damage becomes worse for the 0.18 µm technology
generation and below where the gate oxide thickness shrinks to 3 nm or less.
Interestingly, the opposite appears to be the case [Par97, Shi93]. It appears that the
sensitivity to charging damage peaks at certain oxide thickness. The transition
point at which the sensitivity goes from increasing to decreasing is dependent on
how severe that charging is. A theoretical prediction was given in [Lin98]. The
decrease of plasma charging damage on ultra-thin oxide can be explained by the
following reasons. First, as the gate oxide is very thin, the leakage trough the thin
oxide increases due to direct tunnelling which tends to discharge electrostatic
charge build-up [Ala97]. Secondly, as the oxide thickness reduces, the voltage that
supports a given tunnelling current reduces as well. Furthermore, the impact of a
given density of oxide defects on the transistor’s parameter decreases (due to the
increase in gate capacitance). Additionally, as gate-oxide gets below 5 nm, defects
that contribute to transistor parameter shift can be permanently annealed by the
normal forming gas anneal condition [Pan01]. However, it is argued in [Che00b]
that plasma charging damage might still be present for ultra-thin gate oxides, but
there is a measurement dilemma to reveal it, observe it and measure it. This is still
an open issue.
Introduction
7
As described by Moore´s law [Moo75], the MOSFET gate dimensions have
reduced from 10 µm in the 1970´s to a present day size of 0.1 µm. For decades
SiO2 has been used as the gate dielectric material for standard MOS technology.
One of the problems with scaling MOS beyond the 0.1 µm technology, is the
increasing leakage current through the gate dielectric. The traditional SiO2 gate
dielectric will reach fundamental leakage limits for an effective electrical thickness
below 2.3 nm [Tho98]. To enable MOS scaling in the future, solutions will have to
be found and technologies will have to be altered. As predicted by the recently
published 2002 Technology Roadmap [Sem02], high-k dielectric is going to
replace SiO2 as the gate dielectric for MOS. How will a high-k dielectric as the
gate-dielectric respond to plasma charging damage?
It was predicted in [Che01, Sue01] that plasma charging damage will become a
very serious problem again as high-k material starts to replace SiO2 as gate
dielectric. The main advantage of high-k dielectric is low leakage current for the
same operation voltage compare to traditionally SiO2 gate dielectric with identical
electrical thickness. For a given plasma charging current, the stress voltage across
a high-k gate-dielectric will be much higher than SiO2. Even if the high-k dielectric
is as robust as SiO2, it will suffer a much more severe plasma charging damage
than SiO2. The problem is that so far all the reliability data indicates that high-k
dielectrics are far less robust than SiO2 [Che01].
We expect that the strategies developed in this thesis can still be used for the
future high-k gate dielectric.
1.4 Motivation of this work
The ultimate objective of this work is to find ways to reduce the plasma
charging damage. For this reason, first a better understanding of the mechanism
should be achieved and an evaluation method of the damage induced by plasma
charging should be built up. Based on the evaluation of different impacts of the
layout aspect, a semi-empirical and physical model has been developed. This
knowledge is translated into design strategies and design rules which can be
immediately implemented in the computer-aided design tools used for circuit
design and circuit layout. Therefore the plasma charging damage can be prevented
already in the design phase of the IC.
Chapter 1
8
1.5 Outline of the thesis
This thesis focuses on the plasma charging damage in the context of BEOL
plasma processing. First we focus on a good description and a better understanding
of the effects of plasma processing and of the loss of MOS reliability.
Subsequently, using this basic understanding, we will study the impact of layout
aspects to the degradation of elementary MOS structures and MIM capacitors like
increased gate leakage and reliability loss. The results of these assessments are
translated into solutions, strategies and design rules to reduce the plasma charging
damage. The organization of the thesis is as follows.
In Chapter 2, two main mechanisms of plasma charging damage are briefly
discussed. One is the plasma nonuniform mechanism, the other is the electron
shading (ES) and extended electron shading (EES) mechanism.
In Chapter 3, different test structures and experimental techniques for plasma
charging damage evaluation are described. Plasma charging damage is usually
manifested by the degradation of electrical parameter of the gate oxide and the
device such as increased gate leakage current (Ig), shifted threshold voltage (Vth),
increased interface trap density (Dit) etc., and the reliability loss such as decreased
time-to break-down (tbd), charge-to-breakdown (Qbd), hot-carrier lifetime etc..
Hence, the measurement techniques for evaluation these parameters are presented,
such as current-voltage (IV) measurement, quasi-static capacitance-voltage
(QSCV) measurement, high frequency CV (HFCV) measurement, constant current
stress (CCS), and hot carrier stress.
Besides the existing and traditional measurement techniques, a new slow trap
profile (STP) will be introduced. Moreover, a clear correlation is found between
low levels of gate leakage and both hot carrier (HC) degradation and oxide
breakdown. We, for the first time, demonstrate that the value of the gate leakage
current is not only a failure indicator but also a good indicator of the reliability of
the gate oxide. Additionally, a stepped-voltage testing method is used to reveal
latent as well as actual plasma damage, for a wide range of gate oxide quality in a
very fast way.
Chapter 4 deals with the effect of antenna ratio on plasma charging damage. A
quantitative relation between plasma process-induced oxide failure fraction and
antenna ratio (AR) is built up. The model fits the experiment data very well. Based
on this model, yield loss data obtained on large AR test structures can be used to
extrapolate the yield loss of smaller AR structures which occur more often in real
Introduction
9
circuits. It provides an important link between research structures and the real IC
product.
The reliability effect and the latent damage of plasma charging damage are
discussed in Chapter 5. Apparent reliability loss is observed. Moreover, a simple
experimental method directly demonstrates the pure plasma process-induced latent
damage on gate oxide without any impact of additional defects generated by
normal constant current stress (CCS) revealing technique.
In Chapter 6, the temperature effect on the protection diode is investigated.
Additionally, a novel first order self-balancing interconnect layout design is
proposed for reducing plasma charging damage in modern CMOS processes. If the
layout of the interconnect lines is such that the spacing between the interconnect
lines is alternately wide and narrow, the plasma charging damage is reduced,
because such designed layout locally collects both negative and positive charges
and the charges can counterbalance each other.
In Chapter 7, the mechanism of charging damage of metal-insulator-metal
(MIM) capacitors as well as possible protection schemes are discussed. The
difference of the size of the interconnects that are connected to the two plates of
the capacitor, leads to a potential difference across the insulator between the two
plates. Based on the experimental results, a model is developed which describes
the relation between the damage and the ratio of the area of the exposed antennas
that are connected to the plates of the MIM capacitors. This model enables the
anticipation of plasma charging damage in MIM capacitors. Design rules are
proposed to use in order to prevent the potential charging damage. Furthermore,
layout solutions to reduce charging damage are suggested [Ack01].
Finally, a summary of the work and recommendation for coping with plasma
charging damage are presented in Chapter 8.
1.6 References
[Ack01] J. Ackaert, Z. Wang, E. Backer, and P. Coppens, “Plasma damage in floating metal-insulator-metal capacitors”, Proc. of 8th Intern. Symp. on the Physical & Failure Analysis of Integrated Circuits (IPFA), p. 224, 2001.
[Ala97] M. Alavi, S. Jacobs, S. Ahmed, C. H. Chem and P. McGregor, “Effect of MOS device scaling on process induced gate charging”, Proc. of 2nd P2ID, p. 7, 1997.
[And97] P. Andrews and A. Blaum, “CMOS-circuit protection against PPID for yield enhancement”, Proc. of 2nd P2ID, p. 167, 1997.
[Che00a] K. P. Cheung, “Plasma charging damage”, Springer-Verlag, London, ISBN 1-85233-144-5, 2000.
Chapter 1
10
[Che00b] K. P. Cheung, P. Mason and D. Hwang, "Plasma charging damage of ultra-thin gate-oxide --- The measurement dilemma", Proc. of 5th P2ID, p. 10, 2000.
[Che01] K. P. Cheung, “Plasma charging damage in deep-submicron CMOS technology and beyond”, Proc. of Int. Conf. Solid-State & Integrated Circuit Technol., p. 315, 2001.
[Fan92] S. Fang and J. P. McVittie, “A model and experiments for thin oxide damage from wafer charging in magnetron plasmas”, IEEE El. Dev. Lett., vol. 13, p. 347, 1992.
[Gup97] I. J. Gupta, K. Taylor, D. Buck and S. Krishnan, “Antenna damage from a plasma TEOS deposition reactor: relationship with surface charge and RF sensor measurements”, IRW report, p. 26, 1997.
[Har98] E. B. Harris, “Charging damage in Metal-Oxide-Metal capacitors”, Proc. of 3rd P2ID, p. 15, 1998.
[Has93] K. Hashimoto, “New phenomena of charge damage in plasma etching: heavy damage only through dense-line antenna”, Jpn. J. Appl. Phys., Part 1, vol. 32, p. 6109, 1993.
[Has94] K. Hashimoto, “Charge damage caused by electron shading effect”, Jpn. J. Appl. Phys., vol 33, p. 6013, 1994.
[Kaw85] Y. Kawamoto, Tech. Digest, Dry Process Symp., p. 132, 1985.
[Kri98] S. Krishnan and A. Amerasekera, “Antenna protection strategy for ultra-thin gate MOSFETs”, Proc. of IEEE Int. Rel. Phys. Symp. (IRPS), p. 302, 1998.
[Lin98] B. Linder and N. Cheung, “Calculating plasma damage as a function of gate oxide thickness”, Proc. of 3rd P2ID, p. 42, 1998.
[Luc98] J. M. Luchies, P. Simon, F. Kuper and W. Maly, “Relation between product yield and plasma process induced damage”, Proc. of 3rd P2ID, p. 7, 1998.
[Moo75] G. E. Moore, “Progress in digital integrated electronics”, Int. electron devices meeting technical digest, pp. 11-13, 1975.
[Pan01] L. Pantisano and K. P. Cheung, “Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?”, IEEE Trans. Dev. Mat. Reliab., p. 109, 2001.
[Par97] D. Park and C. Hu, “Plasma charging damage on ultra-thin gate oxides”, Proc. of 2nd P2ID, p. 15, 1997.
[Sem02] Semitech Inc., “The national technology roadmap for semiconductors 2002 update”, http://public.itrs.net/Files/2002Update/2002Update.pdf, 2003.
[Shi93] H. Shin, K. Noguchi and C. Hu, “Modeling oxide thickness dependence of charging damage by plasma processing”, IEEE Dev. Lett., vol. 14, no. 11, p. 509, 1993.
[Sue01] J. S. Suehle, E. M. Vogel, M. D. Edelstein, C. A. Richter, N. V. Nguyen, I. Levin, D. L. Kaiser, H. Wu and J. B. Bernstein, “Challenges of high-k gate dielectrics for future MOS devices”, Proc. of 6th P2ID, p. 90, 2001.
Introduction
11
[Tho98] S. Thompson, P. Packan and M. Bohr, “MOS scaling: transistor challenges for the 21st century”, Intel Technology Jornal Q3, http://www.intel.com, 1998.
[Vah97] V. Vahedi, N. Benjamin and A. Perry, “Topographic dependence of plasma charging induced device damage”, Proc. of 2nd P2ID, p. 41, 1997.
[Wat84] T. Watanabe and Y. Yoshida, “Dielectric breakdown of gate insulator due to reactive ion etching”, Solid State Technol., p. 263, 1984.
[Yos83] Y. Yoshida and T. Watanabe, Tech. Digest, Dry Process Symp., p. 4, 1983.
Chapter 1
12
Chapter 2 Mechanisms of Plasma Charging Damage during Plasma Etching
In this chapter, the mechanisms of plasma charging damage during plasma etching are summarized. Among those mechanisms, the damage caused by the Electron Shading (ES) effect is discussed, because it becomes the major cause of plasma charging damage.
Chapter 2
14
2.1 Introduction
Plasma charging damage refers to the unintended current stressing of the gate-
oxide in metal-oxide-semiconductor (MOS) during plasma processing. A high
electric field develops between the gate and the substrate of a MOS during plasma
processing, forcing charge through the metal lines and the underlying gate oxide. It
took a lot of effort of researchers all over the world to understand the mechanism
due to the complexity of the plasma environment and its interaction with patterned
semiconductor surfaces [Gia98].
Basically, the stress voltage that develops between the gate and the substrate of
a MOSFET during plasma processing has three possible sources:
• The spatial nonuniformity of plasma potential across the wafer
[Kaw85, Fan92, Che94].
• Electron shading (ES) effect due to microscopic topography on the
wafer [Has93, Has94].
• AC effects due to the nature of the RF discharge that sustains the
plasma [Fan92].
2.2 Plasma charging damage by the spatial nonuniformity of plasma
Plasma nonuniformity can be caused by a number of facts, including
nonuniform magnetic fields, hollow cathode effects (hole in the electrodes), and
gas flow at high pressures. Using surface charge monitors, nonuniform charging
and presumably plasma nonuniformity has been observed in most reactor
configurations including barrels [Tsu87], reactive ion etching (RIE) [Kub91],
magnetrons[Kaw85], electron cyclotron resonance (ECR) [Sam91], and plasma
mode parallel plate. This spatial nonuniformity of plasma leads to a local
imbalance between electron and ion currents from the plasma. The imbalance of
local particle currents from the plasma leads to gate charging and subsequent gate
oxide degradation.
Mechanisms of plasma charging damage during plasma etching
15
Gate oxide Conductor
Si sub.
Main etch
End point
Over etch
Resist Resist Resist Resist
Ji
Resist ResistResistResist
JiJe Je Je
Je Ji Je Ji Je
ResistResistResist Resist
Ji Je Je Ji Ji
JiJe
Jtn
Ji
Je
Gate oxide Conductor
Si sub.
SiO2 Conductor
Si sub. JtnJtnJtnJtn
Figure 2.1: Schematic diagram of plasma charging
The damage mainly occurs at the end point and during the over-etch. Here we
take a nonuniform plasma with high ion current density in the centre region and
higher electron current density at the edge for example. As illustrated in Figure
2.1, during the main etching, the patterned antenna surface is connected together as
a whole conductive film. The imbalance of ion and electron currents into each
trench in the centre of the wafer can be accommodated by excess plasma electrons
impinging at the edge of the wafer. At the endpoint and during over etch, however,
the antenna is isolated as an island. The electron supply from edges is cut off. To
minimize the current imbalance, the antenna potential must rise so that a fraction
of the ions arriving the antenna is deflected away while more electrons are
attracted through the trench entrance and the antenna sidewalls. As the potential
difference across the buried gate oxide increases, electron tunnelling from the
substrate also begins to contribute to balancing the current to antenna. Large
tunnelling currents can stress the oxide leading to reliability problems or even
breakdown [Hwa99].
Chapter 2
16
2.3 Electron shading effect
Since a lot of efforts have been done to improve the plasma tools, the
nonuniformity of plasma potential has been eliminated as the main cause of the
plasma charging. Meanwhile, the IC dimensions have shrunk and the aspect ratios
have increased with every new generation. For these modern processes, electron
shading (ES) has emerged as the major cause of charging damage, in which
electrons are shaded by negatively charged photoresist from the bottoms of
trenches and vias, resulting positive charges are accumulated there and therefore
stress the underlying gate oxide.
The electrons and ions have a significant difference in incident angular
distributions [Hwa97]. Electrons are decelerated while ions get accelerated in the
thin positively charged sheath, resulting in broad electron and narrow ion angular
distributions. This difference implies that most of the ions impinge onto a wafer
surface perpendicularly while most of the electrons arrive with oblique incident
angles. A representative distribution is illustrated in polar format in Figure 2.2.
[Gia98].
Figure 2.2: Schematic depiction of the electron and ion angular distribution functions at the sheath edge and at the wafer surface [Gia98].
During etching, the photoresist is negatively charged. The electrons are repelled
by the photoresist. For a dense antenna structure as illustrated in Figure 2.3, the
electrons moving in all directions can hardly enter into a narrow trench. (The word
antenna refers to a conductor exposed to the plasma, such as a metal layer or a
poly-Si layer during plasma etching). The electron shading (ES) effect leads to less
Mechanisms of plasma charging damage during plasma etching
17
electrons impinging into the trench between the antenna lines for neutralization,
where a transitory metal remains because of the microloading effect. Thus the
excess positive charge causes the damage. [Has93]. This is the conventional ES
effect on dense antenna structures.
�
positive charging
---- - - - - - -
---- - - - - - -
---- - - - - - -
---- - - - - - -
---- - - - - - -
---- - - - - - -
++ ++ ++ ++ ++ Antenna
gate
-� -
+�
-+�+�
-�
+�
+�+�
+�
+�
--
-�
-
- +�+�+�
-�-
- -
-+�
+� +�--�
+�+�
-
+�
+�+�
+�
+�
---
-�
-�+�+�
+�-
-
- -�
-+�
+�+�
---
-
-
-
-�+�
+�
+�
+�+�
+�
+� +�
+�
+�--
--
--
-+�
+�
+�+�
+�
+�
+�
- -
-
-� -
-�
plasma
photoresist
Figure 2.3: Schematic view of the conventional ES effect on a dense antenna structure at a moment near the endpoint of metal or poly-si main-etching.
Antenna
Photoresist
- --++
-
+
++
+
+
- -
-
-
- + + +
- -
- -
-+
+ +- -
++
-
+
++
+
+
---
-
- ++
+-
-
- -
-+
++
---
-
-
-
-+
+
+
++
+
+ +
+--
--
--
-+
+
++
+
+
+- -
-
- -
-
Plasma
gate
+ +
++
---- - - - - - -
- - - -
- - - -
---- - - - -- - -
-- -
--- -
---- - - - - - - -
-- -
- -- -
negative charging
Figure 2.4: Schematic view of a conventional ES effect on a sparse antenna structure during metal or poly-si over-etching.
Besides this conventional ES effect, an extended electron shading effect (EES)
has been discovered later [Has98]. Due to the fact that the fingers of the antenna
are far away from each other, the electrons now can reach the sidewall and the
bottom of the trench easily. During over-etching, since the transitory conductor
Chapter 2
18
layer in the trench has been cleared, the ions impinging on the thick oxide and stay
there. Only the sidewall of the antenna is exposed to plasma and catches electrons.
Therefore, the gate is negatively charged, as illustrated in Figure 2.4. The
comparison between ES and EES is summarized in Table 2.1.
Table 2.1: Comparison of conventional ES effect and EES effect
ES EES
Polarity of charging positive negative
Damage phase Near the endpoint of main-etching of dense antennas
During over-etching of sparse antennas
2.4 AC effects
The stress voltages due to AC effects are quite small in most cases and cannot
cause damage by themselves. They do, however, add to the magnitude of stress
voltages developed by either nonuniform plasma potential or ES effect or the sum
of both.
2.5 Summary
In this chapter, the mechanisms of plasma charging damage during plasma
etching have been discussed. Whatever the source of the plasma damage, the local
imbalance of ion and electron currents is the key reason. Among these
mechanisms, the damage caused by Electron Shading (ES) effect is mainly
discussed, because it becomes the major cause of plasma charging damage. It is
also most relevant to other chapters in this thesis. The derived relation between
plasma damage and antenna ratio (AR, the area ratio of the antenna and the gate
oxide of the MOS transistor), in chapter 4, is based on the plasma damage caused
by the ES effect. In chapter 6, the self-balancing layout is proposed to protect the
plasma damage caused by the ES effect.
2.6 References
[Che94] K. P. Cheung and C. P. Chang, “Plasma-charging damage: a physical model”, J. Appl. Phys., vol. 75(9), p. 4415, 1994.
Mechanisms of plasma charging damage during plasma etching
19
[Fan92] S. Fang and J. P. McVittie, “A model and experiments for thin oxide damage from wafer charging in magnetron plasmas”, IEEE Electron Dev. Lett., vol. 13(6), p. 347, 1992.
[Gia98] K. P. Giapis and G. S. Hwang, "Pattern-dependent charging and the role of electron tunneling", Jpn. J. Appl. Phys., vol. 37, p. 2281, 1998.
[Has93] K. Hashimoto, “New phenomena of charge damage in plasma etching: heavy damage only through dense-line antenna”, Jpn. J. Appl. Phys., Part 1, vol. 32, p. 6109, 1993.
[Has94] K. Hashimoto, “Charge damage caused by electron shading effect”, Jpn. J. Appl. Phys., vol. 33, p. 6013, 1994.
[Has98] A. Hasegawa, F. Shimpuku, M. Aoyama, K. Hashimoto and M. Nakamura, “Direction of topography dependent damage current during plasma etching”, Proc. of 3rd P2ID, p.168, 1998.
[Hwa97] G. S. Hwang and K. P. Giapis, “On the origin of the notching effect during etching in uniform high density Plasmas”, J. Vac. Sci. Technol. B, vol. 15(1), p. 70, 1997.
[Hwa99] G. S. Hwang and K. P. Giapis, “On the dependence of plasma-induced charging damage on antenna area”, Proc. of 4th P2ID, p. 21, 1999.
[Kaw85] Y. Kawamoto, Proc. of the 7th Symposium on Dry Process, Tokyo, p. 132, 1985.
[Kub91] M. Kubota, K. Harafuji, A. Misaka, A. Yamano, H. Nakagawa and N. Normura, “Simulational study for gate oxide breakdown mechanism due to non-uniform electron current flow”, Int. electron devices meeting technical digest (IEDM), p. 891, 1991.
[Sam91] S. Samukawa, Ext. Abstr. 38th Meeting, the Japan Society of Applied Physics, p. 499, 1991.
[Tsu87] K. Tsunokuni, K. Nojiri, S. Kuboshima and K. Hirobe, “The effect of charge build up on gate oxide breakdown during dry etching”, Extended Abstract of 19th International Conference on Solid State Devices Materials, Tokyo, Aug., p. 195, 1987.
Chapter 2
20
Chapter 3 Characterization of Plasma Charging Damage
In this chapter, commonly used test structures and experimental techniques for plasma charging damage evaluation are described. Besides the existing and traditional measurement techniques, a slow trap profile (STP) test is described. Moreover, a clear correlation is found between low levels of gate leakage and both hot carrier (HC) degradation and oxide breakdown. This correlation suggests that the gate leakage current can be used to monitor device reliability after plasma stress, thereby saving a lot of measurement time. Additionally, a stepped-voltage testing method is used to reveal latent as well as actual plasma damage, for a wide range of gate oxide quality in a very fast way.
Chapter 3 22
3.1 Introduction
Since the 1980s [Wad84, Tsu87, Sho89], degradation of gate oxides in MOS
devices due to electrical charging induced by plasma processing has been observed
and reported. A lot of effort has been spent to understand the phenomena [Shi91,
Fan92] and to find methods to monitor the charging damage [Shi93, Mur94,
Gab97]. The measurements of plasma charging damage can roughly be separated
into two categories. One category is to measure the damage directly in the devices.
The other is to measure the properties of the plasma, which causes charging
damage.
The main focus of this chapter is the direct measurement of plasma charging. In
section 3.2, common test structures and different experimental techniques for
plasma charging damage evaluation are described. Plasma charging damage is
usually manifested by the degradation of electrical parameters of the gate oxide
and the device such as increased gate leakage current (Ig), shifted threshold voltage
(Vth), increased interface trap density (Dit) etc, and the reliability loss such as
decreased time-to-breakdown (tbd), charge-to-breakdown (Qbd), hot-carrier (HC)
lifetime etc. In this chapter, the measurement techniques for evaluation of these
parameters, such as current-voltage (IV) measurement, quasi-static capacitance-
voltage (QSCV) measurement, high frequency CV (HFCV) measurement, oxide
breakdown, and hot carrier stress are presented. Besides the existing and
traditional measurement techniques, a slow trap profile (STP) techniques is
described. Moreover, the relation between low levels of gate leakage current and
both HC degradation and oxide breakdown is studied.
In section 3.3, a short discussion on measurements to analysis plasma
properties is also presented. In section 3.4, the challenge of plasma charging
damage measurement is discussed. Conclusions are given in the end of the chapter.
3.2 Direct measurements of damage in the devices
3.2.1 Antenna test structures
3.2.1.1 General test structures
In the most studies of plasma charging damage, test structures are based on
elementary devices like MOSFETs, capacitors or memories. Because there are still
Characterization of plasma charging damage
23
a lot of issues about plasma charging damage on individual devices not fully
understood, very few studies have been presented on integrated circuits.
The test structures used in our study are MOSFETs and capacitors. Antennas
are connected to the gate of the MOSFET or to the two plates of the capacitors.
The antenna is a conductive surface which is exposed to plasmas during
processing. It collects charges from the plasma, explaining the name “antenna”.
The antennas are designed in different shapes and sizes in order to simulate the
variations of interconnect layout. Plate-shaped antenna and finger-shaped are two
common designs. A sample with a metal 2 antenna is shown in Figure 3.1, which is
used for monitoring the damage of the processes including plasma clean, plasma
etching and plasma deposition during metal 2 manufacturing. A protection diode is
connected to metal layers above the antenna in order to avoid the influence of
other plasma processes after metal 2 manufacturing. It is a sample of metal 2 (M2)
antenna structure. The antenna can also be put on other metal layers or poly-Si
layer. Normally, a series of test structures with different antenna size, different
inter-finger space, and different level are designed in order to get a full picture of
the plasma charging damage during all the plasma processes.
M2
M2
Protection diode
P+
N-well (float.) P sub.
M3
Transistor Protection diode
P+
N-well (float.)P sub.
M3
Transistor
Figure 3.1: Schematic layout of antenna test structures with a metal 2 (M2) plate-shaped antenna and a finger-shaped antenna. A protection diode is connected on metal 3 layer to protect the gate oxide from plasma charging damage above M2 layer.
The connections to the bond-pads should be bridged. That means the
connections to the bond pad should be made via the last metal level, as shown in
Figure 3.2. Without bridging, the charging effect of the bond-pad could affect the
test structure and overwhelm the antenna effect.
Chapter 3 24
M1
M5 M4 M3
bond-pad
device
antennaPoly-Si
active
M2
active protection
diode bridging
Figure 3.2: Desired design of bond-pad connection.
In this thesis, antenna structures with different gate oxide thickness and
different antennas have been made in a 0.18 µm or 0.35 µm CMOS backend-of-
line process. Afterwards, the charging sensitive antenna test structures have been
measured and analyzed.
3.2.1.2 Antenna test structures with transient fuse (T-fuse)
Two kinds of structures with a transient fuse (T-fuse) are used to distinguish
the damage from different plasma etching phases (main etching phase versus over-
etching phase). Structure A is with T-fuse between the gate and antenna and
Structure B is with T-fuse between the antenna and protection diode or ground.
M2
Transistor
(a)
M2
Protection diode
P+
P sub.
M2
Transistor
T-fuse
(b)
T-fuse
or ground
T-fuse
Figure 3.3: Top view of the structure during main etching. The conductivity across the T-fuse is maintained.
Characterization of plasma charging damage
25
M2
Transistor
(a)
M2
Protection diode
P+
P sub.
M2
Transistor
T-fuse
(b)
T-fuse
or ground
T-fuse
Figure 3.4: Top view of the structure during over etching. The remains of metal or poly-Si between the lines are clear, and the T-fuse is automatically disconnected.
The T-fuse consists of a few metal/poly-Si lines. The conductivity across the T-
fuse is maintained during the main etching (Figure 3.3), because the metal/or poly-
Si in the trenches between the lines is not completely cleared. Structure A receives
plasma charging damage, because the antenna is connected to the gate. However,
Structure B with a T-fuse between the antenna and protection diode or ground is
protected, because most of the charges go trough the protection diode to ground
instead of through the gate oxide. During over etch, the remains of metal or poly-
Si between the lines are cleared and the T-fuse is automatically disconnected
(Figure 3.4). In this phase, Structure A is free from plasma charging damage
because the antenna is disconnected. However, Structure B suffers from plasma
charging damage because the connection to the protection diode or the ground is
stopped. Table 3.1 summarizes the conclusions that can be drawn from the
experimental results of these T-fuse structures.
Table 3.1: summary of the relation of experimental results of T-fuse structures and the plasma process phase which causes charging damage.
Structure A Structure B Damage occurs during
fail good main etching only
good fail over etching only
fail fail both main etching and over etching
Chapter 3 26
3.2.1.3 Other special structures
Structures with an antenna connected to the drain or source sometimes are also
used to simulate the device that has long interconnects to drain or source. Not only
transistors but also capacitors with an antenna attached are used as test structures,
as seen in chapter 7. Moreover, in order to investigate the plasma charging damage
to a circuit, simple circuit like ring-oscillators can also be used. A wafer called a
large range of antenna structures is commercially available under the name
“SPIDER” [Aum98].
3.2.2 Measurement techniques for test structures
After manufacturing, the antenna test structures are measured. From the
degradation of the antenna test structures, we can assess the extent of plasma
charging damage, identify the problem process step, and try to understand the
mechanism of the plasma charging damage. Table 3.2 summarizes the
characterization techniques and the information that can be obtained from the
measurements.
Table 3.2: Characterization techniques.
Techniques Information
Stress induced leakage current
(SILC) Leakage current
CV characteristics Density of the traps, fixed charge
and energy band
STP (Slow Trap Profile) Energy distribution of slow traps
Initial gate leakage (Ig,leak)
measurement Break down or soft break down
Oxide breakdown Bulk oxide damage
Hot carrier stress Oxide and interface quality
Among the above mentioned measurement techniques, initial gate leakage
(Ig,leak) measurement is the most commonly used technique, because it is fast,
simple and useful. Oxide breakdown and hot carrier are accurate measures of the
gate oxide integrity. However, they are not often used because they are very time
consuming. Stress induced leakage current (SILC), CV characteristics and STP
(Slow Trap Profile) are used on capacitor structures for more detailed information
about defects.
Characterization of plasma charging damage
27
3.2.2.1 SILC, QSCV, HFCV, STP and CCS measurements
In this section, stress induced leakage current (SILC), flat band voltage (Vfb),
interface trap density (Dit), and slow trap density (Dst) have been characterized by
current-voltage (IV) measurement, quasi-static capacitance-voltage (QSCV)
measurement, high frequency capacitance-voltage (HFCV) measurement, and slow
trap profile (STP) measurement. Constant current stress (CCS) is used to simulate
the plasma charging. It will be shown that a certain electrical stress current can
produce the same damage as a plasma exposure. This confirms that electrical stress
is the cause of plasma charging damage. Some work has been done before [Ata95,
Gua99], but these characteristics have not been studied simultaneously to
investigate the plasma charging damage in previous works. The tests in this section
require large area structure, in order to be sensitive to small variations.
The test samples are metal-oxide-semiconductor (MOS) capacitors, with 12 nm
or 7 nm thermally grown gate oxide on a p-type (100) silicon substrate. N-type
poly-Si gates were used as antenna in this work. The poly-Si gate and thin gate
oxide are square, with the same area of 0.6 µm2. The antenna ratio (AR) is defined
as the ratio of the area of the antenna exposed to the plasma and the area of the
active thin gate oxide. For our samples the antenna ratio, AR = 1 (note that large
oxide area structures always have a low antenna ratio. Some of the samples were
exposed to an inductive coupled plasma (ICP) for 1 min, 5 min, or 15 min to
investigate the plasma charge damage as a function of time. For simplicity and
avoiding chemical interactions, an argon plasma is used. The exposure conditions
are listed in Table 3.3. Before the exposure, a spatial Langmuir probe
measurement was conducted to obtain the spatial variation of various parameters
of the plasma [Auc89]. The plasma conditions are listed in Table 3.4. Samples not
subjected to plasma exposure are called fresh samples in this work.
Table 3.3: Exposure conditions.
ICP input Power 1000 W
Substrate Biasing 0 V
Substrate Temperature 25.0 0C
Ar throughput 50.0 sccm
Gas pressure 1.00 Pa
Chapter 3 28
Table 3.4: Plasma conditions.
Floating potential around 15 V
Plasma potential around 31 V
Potential difference( Vp-Vf) around 16 V
Electron temperature around 4 eV
Electron density around 8×109 cm-3
Ion density 2.0 to 2.4×1010 cm-3 Ion current density 0.35 to 0.42 mAcm-2
A. Stress-induced-leakage-current (SILC) measurement
Stress-Induced Leakage Current (SILC) is the increase in low-voltage level
leakage through thin silicon dioxide (SiO2) layers, after the oxide has been
subjected to an electrical stressing. Stress-Induced Leakage Current (SILC) was
first observed by Maserjian et al. [Mas82] in the early eighties. They observed that
the gate leakage current at low and medium oxide fields (Eox < 7 MV/cm)
increased with increasing electrical stress. This phenomenon is now commonly
known as an indication of the degradation of thin oxide layers which have been
subject to electrical stress [Ngu87, Nar88, Rof91, Moa92, Pat94].
During plasma processes, microscopic defects are generated in the oxide by the
plasma-induced discharging current. In general, microscopic defects are associated
with localized electronic states that can trap or emit a charge carrier. Dependent on
their location, the states exhibit different behaviour (see Figure 3.5). Those located
at the Si/SiO2 interface ("interface traps") can exchange charge carriers with the
silicon. States located in the oxide ("bulk oxide traps") are less likely to do so;
however, they can capture charge carriers injected into the oxide layer. A series of
overlapping states may form a path for continuous charge flow from the silicon
substrate to the gate ("leakage currents"). After stressing, more defects are
generated and thereby the leakage current increases.
Characterization of plasma charging damage
29
Si SiO2
Interface state
Si SiO2
Bulk oxide traps
Si SiO2
Path for leakage current Figure 3.5: Electronic states in the MOS system can be categorized according to their location. States in the proximity of the Si/SiO2 interface are designated "interface states", those located further away "bulk oxide traps". A series of overlapping states provides a path for charge transport from substrate to the gate ("leakage currents").
IV measurements were performed with a HP 4156 A, precision semiconductor
parameter analyser. Figure 3.6 shows the IV curves for different plasma exposure
times. From this figure, it is observed that with increasing plasma exposure time
the leakage current also increases and the IV curve shifts positively. It indicates
that longer exposure causes more defects in the gate oxide due to a longer time of
current stressing.
1.0E-14
1.0E-13
1.0E-12
1.0E-11
1.0E-10
7.0 7.5 8.0 8.5 9.0 9.5 10.0
-Vg (volt)
-I (
A)
15min plasma exposure
5min plasma exposure
1min plasma exposure
Fresh sample
15min5min1minFresh
Figure 3.6: SILC increasing with plasma exposure times.
B. CV measurement
The most important defects generated by plasma charging are interface states
[Car93, Nij94] and bulk oxide neutral electron traps. Both of these defects strongly
affect the device characteristics. Charge carriers trapped at such defects in the
oxide layer induce a permanent electric field that shifts the threshold voltage of the
Chapter 3 30
MOSFET and affects the efficiency of charging and discharging the floating gate
(write/erase) for memories. Interface states strongly reduce the channel
transconductance and distort the QSCV and HFCV characteristics.
QSCV and HFCV curves were measured from strong inversion to accumulation
with a voltage scanning step of 50 mV by a HP4140B pA meter/DC voltage source
and a HP4175A multi-frequency LCR meter. A frequency of 100000 Hz was used
during the HFCV measurements. A comparison of QSCV curves of the fresh
samples and different plasma exposed samples is shown in Figure 3.7. The longer
plasma exposure samples show a higher degree of degradation. In the depletion
region, an increase of the minimum capacitance with the exposure time is
observed. Since the interface traps can contribute to the total device capacitance,
the increase in depletion capacitance is a measure for the increasing number of
interface traps. From Figure 3.8 , it was observed that the HFCV curves of plasma
exposed samples shift negatively compared to the fresh samples. The shifts of
HFCV indicate a negative shift in the flat band voltage (Vfb) and an increase in
positive oxide trapped charges (Qot). As illustrated in Figure 3.9, it is clear that the
longer the sample is exposed to the plasma, the more the flat band voltage (Vfb)
shifts negatively and the more positive oxide trapped charges (Qot) are generated.
The Not in Figure 3.9 is the oxide trapped charge area density, [ions/cm2]. For
convenience of comparing, the value of fresh sample is also stated in the figures
indicated as “0 min plasma exposed” samples. It is clear that the 7 nm oxide
samples show less Vfb shift and less Not creation than the 12 nm oxide samples. The
shifts in Vfb and Not for the 7 nm samples are within the error margins of the
measurement technique, and negligible for practical applications. From Figure 3.9
it is clear that for decreasing oxide thickness the plasma damage will be more
difficult to access using these characterization methods.
Characterization of plasma charging damage
31
0.0E+00
2.0E-10
4.0E-10
6.0E-10
8.0E-10
1.0E-09
1.2E-09
1.4E-09
1.6E-09
1.8E-09
-3 -2 -1 0 1 2
Vg(volt)
C (F
)
15min plasma exposure
5min plasma exposure
1 min plasma exposure
Fresh sample15min5min1minFresh
Figure 3.7: The comparison of QSCV between fresh samples and different plasma exposed samples (tox = 12 nm).
0.0E+00
2.0E-10
4.0E-10
6.0E-10
8.0E-10
1.0E-09
1.2E-09
1.4E-09
1.6E-09
1.8E-09
-3 -2 -1 0 1 2
Vg (volt)
C (
F)
15min plasma exposure5min plasma exposure1min plasma exposureFresh sample
15min, 5min, 1min, Fresh
Figure 3.8: The comparison of HFCV between fresh samples and different plasma exposed samples (tox = 12 nm).
Chapter 3 32
Plasma exposure time (min)
0 5 10 15 20
Vfb
shi
ft (
V)
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
Not (
cm-2
)
-2e+11
0e+0
2e+1112nm
12nm
7nm
7nm
Figure 3.9: Flat band voltage shift and the area density of oxide trapped charge as a function of the plasma exposure time for two oxide thicknesses (tox = 7 nm & 12 nm).
C. Interface trap density (Dit) calculation
There are two methods commonly used to calculate Dit based on QSCV and
HFCV measurements. In the first method, the interface trap density (Dit) over the
band gap was extracted by comparing the measured QSCV with the theoretical
curve [Sch90]. In this method, the QS capacitance in depletion-inversion is given
by Equation (3.1) as
( ) ( )itsox
qs CCCC
++=
11
1 (3.1)
where Cs is the semiconductor capacitance. The interface trap capacitance, Cit, is
related to the interface trap density by Dit = Cit/q, giving
= sqsox
qsoxit C
CC
CC
qD
1 (3.2)
Therefore, in order to determine Dit, Cqs and Cs must be known. Cqs is measured as
function of gate voltage and Cs is calculated as a function of surface potential ( S).
Note that Cqs is measured as function of gate voltage. Hence the relation between
S and Vg is needed. Berglund proposed [Ber66]
+= 2
1
)1(g
g
V
V gox
qss dV
C
C (3.3)
Characterization of plasma charging damage
33
where is an integration constant given by the surface potential at Vg = Vg1.
The determination of Dit from QSCV is quite time-consuming. However, it is
not always necessary to get Dit as a function of energy level. For example, for
process monitoring it is often sufficient to obtain Dit at one point on the CV curve
and then compare them device-to-device or run-to-run [Sch90]. Therefore, a
second method to calculate Dit can be used based on the difference in HFCV and
QSCV.
0.0
0.2
0.4
0.6
0.8
1.0
-5 -4 -3 -2 -1 0 1 2 3 4 5
Vg (V)
C/C
ox
C qs
C hfC/Cox
Figure 3.10: QSCV and HFCV curves showing the offset C/Cox due to interface traps.
The Dit can be calculated at the point where the technique is most sensitive: the
minimum of Cqs. The minimum capacitance (Cqs) corresponds to a surface
potential ( S) in the light inversion region near midgap, that is F< S<2 F ( F is
Fermi potential). In our case, there is a hump right in that point, as shown in Figure
3.10. We choose that point to calculate Dit, because it is easily identifiable. Thus,
the Dit at that point can be extracted by
=oxhf
oxhf
oxqs
oxqsoxit CC
CC
CC
CC
q
CD
11 (3.4)
It can be observed in Figure 3.11 that the Dit data calculated from Equation (3.2)
and Equation (3.4) at same energy point are consisted with each other.
Chapter 3 34
0.0E+00
1.0E+11
2.0E+11
3.0E+11
4.0E+11
0 5 10 15 20
Plasma exposure time (min)
Dit
(ev-1
cm-2
)
Dit calculated from QSCV
Dit calculated from QSCV & HFCV
Figure 3.11: The comparison of Dit data calculated from QSCV only and from QSCV & HFCV for samples with tox = 12 nm.
0.0E+00
1.0E+11
2.0E+11
3.0E+11
4.0E+11
0.35 0.45 0.55 0.65 0.75
E-Ev (ev)
Dit (e
V-1
cm-2
) 15min
5min
1min
Fresh
Figure 3.12: Energy distribution of interface trap density comparing fresh and plasma exposed samples with tox = 12 nm.
With exposed time increasing, the interface trap density through almost the
whole band increases. Calculating the density of interface states as a function of
Characterization of plasma charging damage
35
the energy level for the sample with tox = 12 nm, gives the results presented in
Figure 3.12. Particularly, there is a hump around 0.65 eV with respect to valence
band energy. It was reported that the state with an energy level of 0.65 eV is
caused by hydrogen atoms attached to oxygen atoms. This hydrogen related
defects can occur at the interface as fast state, and it also can occur near the
interface as slow state [Dru96].
D. Slow trap profile (STP) measurement
Besides the interface traps, the occurrence of trapping centres near the Si-SiO2
interface with time constants ranging from milliseconds to years (“slow traps”) has
been known for many years [Lef88]. The slow traps are believed to be responsible
for surface-induced 1/f noise, random telegraph signals, and threshold voltage
shifts in deep submicron MOSFETs [Tan95, Tan96]. They exchange charge with
the silicon via tunnelling mechanisms that depend on their energy level with
respect to the surface Fermi level in the silicon. Figure 3.13 [Tan97] illustrates this
process for the case of a poly-Si MOS capacitor being swept from flat band to
strong inversion, showing the movement of electrons and holes and the resulting
current transient. At flat band, interface traps and slow traps below the Fermi level
(EF) are filled with electrons and those above are empty (low temperature
approximation). As the device is stepped into strong inversion, holes are swept
away from the interface in a few picoseconds, forming the space charge region.
Following this, minority carriers are generated in the depleted silicon and move to
the interface to form the inversion layer and any fast interface traps, now below the
Fermi level, are filled with electrons. All these processes normally occur within
the space of a few milliseconds during strong inversion, and will be termed "fast"
in the context of this thesis. They are given the collective time constant, 1, on the
band diagram and produce the initial current spike in the current transient. Due to
the shift in surface Fermi level in the silicon and the band bending in the oxide,
slow traps now find themselves at a lower energy relative to the Fermi level. As a
result, electrons tunnel through the oxide energy barrier from the silicon
conduction band and fast interface traps at a rate which depends on the density of
electrons at the interface, the density of slow traps, the barrier height, and the
tunneling distance. This process is given the collective time constant, 2, and
results in the slower part of the transient.
Chapter 3 36
EC EI EF EV
Oxide p-Si
+ ++ +
Fixed oxide charge Slow
traps Fast Interface traps
1
2
1
t
i 2
1
Figure 3.13: Energy band diagrams showing a MOS capacitor under charge movement (sweeping the bias toward strong inversion). The resulting charge transient is comprised of an initial portion, 1, and a slower portion, 2, due to the tunneling of electrons to slow traps [Tan97].
The slow trap profiles were measured from accumulation to inversion at 50
mV/s. A slow trap profiler applies a series of voltage steps to the device and
records the resulting charge transients due to slow traps near the Si-SiO2 interface.
By a digital IO interface box, and IO card which was plugged into an IBM PC, the
three parameters were digitized. The gate voltage (Vg), time since the voltage step
(response time, ), and integrated substrate charge (Qsub), form the basis for the
slow trap profile. The gate voltage (Vg), time since the voltage step (response time,
), and integrated substrate charge (Qsub), the slow trap distribution, Dst[V-1s-1cm-2],
at each point in the gate voltage and instant in time is obtained by
)/( AtVqQD subst = , (3.5)
where q is the electronic charge, V is the voltage step, t is time interval over
which the charge is integrated, and A is the area of gate oxide in the MOS
capacitor.
Characterization of plasma charging damage
37
Ev+0.65eV
(a)
Ev+0.65eV
(b)
Figure 3.14: (a). The slow trap profiles of fresh samples and (b) 15 min plasma exposed samples.
Chapter 3 38
0.0E+00
5.0E+09
1.0E+10
1.5E+10
2.0E+10
0 5 10 15
Plasma exposure time (min)
slo
w t
raps
/cm
2
Figure 3.15: The comparison of slow trap area density (integrated under the small hump region) of different samples.
As shown in the slow trap profiles of Figure 3.14 (a) and (b), it can be observed
that the slow traps around the energy level of 0.65 eV increases after plasma. (The
energy level in figures is derived from the quasi-static CV curve [Tan96]).
Meanwhile, a significant number of slow traps between –0.5 V to 2 V with various
response times occur. In order to compare the small hump with different plasma
exposure times, the slow trap area density in that region with response time up to
200 ms is obtained by integrating the volume under the small hump. As shown in
Figure 3.15, with increasing exposure time, first the slow trap area density
increases fast and then the increase rate tends to decrease.
E. Constant current stress (CCS) measurement
It was reported that a constant current stress could reproduce the damage
caused by plasma charging [Shi91]. Both can cause trapped charges in the oxide
and at the Si-SiO2 interface; therefore deform the CV curve of the gate oxide. By
comparing the increased interface trap density caused by an CCS and 5 min plasma
exposure, we can obtain the stressing current density that produces the same
amount of damage as the plasma does at the same period of time.
Some fresh samples were subjected to constant current stress (CCS). These
samples were stressed (in accumulation) by passing different levels of negative
constant current through the gate for 5 min. The Dit difference caused by CCS was
compared to the Dit value of the fresh samples before CCS. Figure 3.16 shows the
Characterization of plasma charging damage
39
increase of Dit as a function of the electrical stress current density. The data match
the Log trend line very well. The Dit difference caused by 5 min electrical stressing
of Jst = -0.25 mA/cm2 is close to the Dit caused by 5 min plasma exposure,
1.83×1011 eV-1cm-2. In other words, electrical stressing at Jst = -0.25 mA/cm2 can
reproduce the same amount damage as the Ar plasma exposure in our experiments.
1.0E+10
1.0E+11
1.0E+12
0 0.25 0.5 0.75 1 1.25 1.5 1.75
negative stress current density (mAcm-2)
Dit
incr
ease
(e
V-1
cm-2
)
Dit difference caused by CCS
Dit difference caused by 5minplasma exposure
Figure 3.16: The dependence of Dit difference caused by CCS on the density of the constant current (tox = 12 nm).
Next, the fresh samples and the samples with different plasma exposure time
were subjected to CCS as well. The stressing condition is Jst = -1 mA/cm2 for a
period of 5 min after stressing. The interface trap densities of different samples
were compared. As shown in Figure 3.17, the interface trap density of fresh sample
increases by 3.8×1011 eV-1cm-2,while the interface trap density of 15 min plasma-
exposed sample increases by 1.9×1011 eV-1cm-2.
If we make the assumption that the damage created (increase in Dit) depends on
the injected charge (Qinj) but is independent on the current density, the following
holds: 5 min electrical stress at Jst = -1 mAcm-2 gives the same Dit as 20 min
electrical stress at Jst = -0.25 mAcm-2. (Though qualitatively equivalent, more
experimental data would be needed for a quantitative comparison.) In that case, we
can shift the Dit data stressed for 5 min at -1 mAcm-2 to the Dit data for initial+20
min exposure time in Figure 3.17. It is observed that the Dit data of fresh and
plasma-exposed samples with 0 min, 1 min, 5 min, and 15 min exposure time and
the extended Dit data with equivalent 21 min, 25 min, and 35 min exposure time fit
Chapter 3 40
the same 2nd order polynomial trend line. The trend is that the damage is going to
saturate, as the exposure time becomes longer.
0.0E+00
1.0E+11
2.0E+11
3.0E+11
4.0E+11
5.0E+11
6.0E+11
7.0E+11
0 5 10 15 20 25 30 35 40
Plasma exposure time (min)
Dit (
ev-1
cm-2
)
after CCS
plasma exposure
extented value from CCS
CCS
extend
Figure 3.17: comparison of interface trap density (Dit) of different samples before and after CCS.
3.2.2.2 Gate leakage current (Ig,leak), Hot carrier (HC) stress, oxide breakdown (BD) measurements and their correlation
The initial (before intentional stress) gate-leakage current (Ig,leak) at low oxide-
field is the current preferred method of plasma charging damage measurement in
the ultra-thin gate-oxide regime [Jia98, Sri97, Kri98]. In this section, we will
explain why it is most popular measurement method and how it works.
Hot carrier (HC) stress and charge-to-breakdown measurements are also
introduced in this section. They are accurate measures of the gate oxide quality
[Bhu99]. However, they are not often used in monitoring damage because they are
very time consuming.
The results of the hot carrier (HC) stress and oxide breakdown have been
compared with the gate leakage current (Ig,leak) measured at low oxide-field. A
clear correlation is found between low levels of gate leakage and both HC
degradation and oxide breakdown. In this section, it will be demonstrated that the
value of the gate leakage current is not only a failure indicator but also a good
indicator of the reliability of the devices.
Characterization of plasma charging damage
41
Additionally, a new stepped voltage breakdown method was developed to
reveal latent as well as actual plasma damage, for a wide range of gate oxides in a
very fast way. Compared to constant voltage stress, this stepped voltage stress
shows better sensitivity in evaluating plasma charging damage.
Test structures were processed in a 0.35 µm CMOS process. The test
structures are transistors with W × L = 0.35 µm × 2 µm. The gate oxide thickness
is 7.5 nm. The charging tester consists of a MOSFET with a finger-shaped metal
antenna connected to the gate on the first or the second metal level. The antennas
are patterned with a medium density plasma system. Oxide is deposited on top of
the antennas with a high-density plasma (HDP) system. The antenna ratio (AR),
which is defined as the ratio between the area of the antenna connected to the
transistor and the active area of the transistor itself are 1000, 10000, and 100000.
To investigate the impact of the electron shading effects, comb shaped antennas
with spacing of 0.6 µm and 5 µm are compared. The protection diode is connected
to the gate at a subsequent level, in order to protect the gate oxide from damage
produced by plasma process steps following patterning the antenna.
A. Initial gate leakage (Ig,leak) measurement
The initial (before intentional stress) gate-leakage current (Ig,leak) at low oxide-
field is the current preferred method of plasma charging damage measurement in
the ultra-thin gate-oxide regime [Jia98, Sri97, Kri98]. It is a fast and simple
measurement with good sensitivity to plasma charging damage of ultra-thin gate-
oxide [Gab97].
As the gate-oxide gets thinner, the impact of a given area density of oxide
defects on the transistor’s parameter decreases due to the increase in gate
capacitance. Additionally, as gate-oxide gets below 5 nm, defects that contribute to
transistor parameter shift can be permanently annealed by the normal forming gas
anneal condition [Pan01]. The transistor parameters are no longer sensitive to
plasma charging damage for thin gate-oxide. However, the plasma charging
damage is not gone. The mode of failure due to plasma charging damage has
changed from device and circuit performance degradation to gate-oxide breakdown
reliability degradation [Lin98]. The preferred method for plasma charging damage
measurement changes from transistor parameter shift to initial gate leakage
measurement [Che98].
For the small size transistors typically used in plasma charging damage study,
this initial gate leakage measurement is not measuring stress-induced leakage
current (SILC). Rather, it is measuring post soft breakdown conduction current
Chapter 3 42
[Che99]. When soft breakdown occurs, a finite current jump will result [Mir00,
Ala99]. If the measurement voltage is not too small, this current jump magnitude is
typically in the nA range or larger, and is independent of the device area. The
explanation for this area independent conduction is that the conduction spot is
much smaller than the device area and conducts much more current than the total
direct tunnelling current. Most measurement system with a noise floor at 100 pA
or lower would have no problem capturing all the soft broken devices [Che00a].
Any detectable gate leakage larger than nA is an indication of a broken gate-oxide. In our study, gate leakage (Ig,leak) of the antenna test structures was measured by
applying a gate voltage of Vg = 3.6 V. An antenna test structure can be considered
to fail when the Ig,leak measured through its gate oxide exceeds 0.1 nA, indicating
that soft or hard breakdown occurred. The 0.1 nA is selected as failure criterion
based on the leakage current distribution, as shown in Figure 3.18. The devices
with Ig,leak higher than 0.1 nA, diverge from the intrinsic slope, indicating extrinsic
damage induced by plasma charging. Special precautions in the measurement setup
have to be taken to reach high enough accuracy with the low-level leakage
measurements.
-5
-4
-3
-2
-1
0
1
2
3
-13 -12 -11 -10 -9 -8 -7 -6
Log [Ig,leak (A)]
ln[-
ln(1
-F)]
Ig,leak failcriterion
Log[Ig,leak (A)]
Figure 3.18: Distribution of gate leakage current. The devices with Ig,leak higher than 0.1 nA, diverge from the intrinsic slope, indicating extrinsic damage induced by plasma charging.
Characterization of plasma charging damage
43
B. Hot carrier (HC) life time and its correlation to gate leakage (Ig,leak)
Hot carrier (HC) stress was also performed on PMOSFETs. The PMOSFET
was stressed at Vd = -6.5 V, Vg = -1.9 V. This Vg was chosen to maximize bulk
current Ib [Sch90]. The HC lifetime, which is defined as the time the MOSFET
takes for a 10 mV Vt shift, is compared with the initial Ig,leak with Vg = 3.6 V
measured on the same devices. The HC lifetime of PMOSFETs are shown in Figure 3.19 for devices with
metal 1 antennas and Figure 3.20 for device with metal 2 antennas. For failing
devices with Ig,leak above 0.1 nA, the HC lifetime is degraded several decades. For
the survived devices with Ig,leak below 0.1 nA, the leakage current value is related
to the HC lifetime. The devices with Ig,leak in the range of 1 to 10 pA have longer
lifetimes, while the others with Ig,leak in the range of 10 pA to 0.1 nA value have
clearly shorter lifetimes. A clear correlation is also observed with the size of the
antenna connected to the gate of the transistor: increasing the antenna size by a
decade, the Ig,leak increases and the HC lifetime decreases by more than a decade.
0.01
0.1
1
10
100
1000
10000
1.0E-13 1.0E- 12 1.0E-11 1.0E-10 1.0E-09 1.0E-08 1.0E- 07 1.0E-06 1.0E-05
Ig,leak [A]
HC L
ifeti
me [
s]
RefAR=1K,s=5umAR=10K, s=5umAR=100K, s=5umRefAR=1K, s=0.6umAR=10K, s=0.6umAR=100K, s=0.6umFail criterion
100K
1K
10K
Ref
0.01
0.1
1
10
100
1000
10000
1.0E-13 1.0E- 12 1.0E-11 1.0E-10 1.0E-09 1.0E-08 1.0E- 07 1.0E-06 1.0E-05
Ig,leak [A]
HC L
ifeti
me [
s]
RefAR=1K,s=5umAR=10K, s=5umAR=100K, s=5umRefAR=1K, s=0.6umAR=10K, s=0.6umAR=100K, s=0.6umFail criterion
100K
1K
10K
Ref
Ref
AR=10000
AR=100000
AR=1000
Ig,leak fail criterion
Ig,leak (A)
HC
life
time
(s)
Figure 3.19: HC lifetime as function of gate leakage current measured at 3.6 V on the same devices with metal 1 finger antenna.
Chapter 3 44
0.01
0.1
1
10
100
1000
10000
100000
1000000
1.0E-13 1.0E-12 1.0E-11 1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05
Ig.leak [A]
HC
Lif
etim
e [s
]
RefAR=1K, s=5umAR=10K, s=5umAR=100K, s=5umRefAR=1K, s=0.6umAR=10K, s=0.6umAR=100K, s=0.6umFail c riterion
100K10K
1K
Ref
0.01
0.1
1
10
100
1000
10000
100000
1000000
1.0E-13 1.0E-12 1.0E-11 1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05
Ig.leak [A]
HC
Lif
etim
e [s
]
RefAR=1K, s=5umAR=10K, s=5umAR=100K, s=5umRefAR=1K, s=0.6umAR=10K, s=0.6umAR=100K, s=0.6umFail c riterion
100K10K
1K
Ref
Ref
AR=1000
AR=10000 AR=100000
Ig,leak fail criterion
Ig,leak (A)
HC
life
time
(s)
Figure 3.20: HC lifetime as function of gate leakage current measured at 3.6 V on the same devices with metal 2 finger antenna.
The strong correlation with the antenna ratio is considered as a signature for
plasma damage being the cause of the degradation [Sho89, Shi91].
C. Oxide breakdown and its correlation to gate leakage (Ig,leak)
The oxide breakdown measurement was performed with a stepped voltage
stress on more than one thousand devices. The gate oxide was stressed on 3.5 V,
corresponding with 4.7 MV/cm for 1 second (step 1), 4.0 V or 5.3 MV/cm for 1
second (step 2), 4.5 V or 6.0 MV/cm for 1 second (step 3) and so on until 7.0 V or
9.3 MV/cm for 1 second (step 8). Between each step the gate leakage is measured.
The results are plotted as a function of the initial Ig,leak with Vg = 3.6 V. This testing
method was developed to reveal latent as well as actual damage, for a wide range
of gate oxide quality in a very fast way. Moreover, Oxide time-to-breakdown (tbd)
was measured with 5.5 V constant voltage stress for maximum 450 sec. These two
measurement methods have been compared.
The results of breakdown measurement performed with a stepped voltage stress
are compared with the gate leakage current on the same devices in Figure 3.21 for
devices with metal 1 antenna and in Figure 3.22 for devices with metal 2 antennas.
All the reference structures without extra antenna connected to the gate have an
initial leakage below 0.1 nA and none of them shows oxide breakdown. The
antenna devices that are as good as reference devices and with low initial Ig,leak
Characterization of plasma charging damage
45
value also not break down. For the antenna devices with initial Ig,leak higher than
0.1 nA, there is a clear linear trend between Ig,leak and the breakdown field.
4.0
5.0
6.0
7.0
8.0
9.0
1.0E-14 1.0E-12 1.0E-10 1.0E-08 1.0E-06
Ig,leak (A)
brea
kdow
n fie
ld (
MV
/cm
)
M1, AR=100K,s=5um
Reference
good devices damaged devices
M1, AR = 100000 s = 5 µm
Ig,leak (A)
Figure 3.21: Breakdown field as function of initial gate leakage current measured on NMOSFETs with M1 finger antenna.
4.0
5.0
6.0
7.0
8.0
9.0
1.0E-14 1.0E-12 1.0E-10 1.0E-08 1.0E-06
Ig,leak (A)
brea
kdow
n fie
ld (
MV
/cm
)
M2, AR=100K,s=5um
Reference
good devices damaged devices
M2, AR = 100000 s = 5 µm
Ig,leak (A)
Figure 3.22: Breakdown field as function of initial gate leakage current measured on the same NMOSFETs with M2 finger antenna.
Moreover, Oxide time-to-breakdown (tbd) was measured with 5.5 V constant
voltage stress for maximum 450 sec. The devices are separated into tow groups.
Some of the devices breakdown immediately as shown in Figure 3.23, the others
don’t breakdown at all till 450 sec. The devices that break down immediately are
damaged devices and those that don’t breakdown are good devices. However, the
stress voltage we select is unfortunately too high for the plasma-damaged devices,
but too low for the good devices. Therefore it can separate neither of the two
Chapter 3 46
groups. Though a good selection can separate one group, it is not possible to
separate the other group. Considering the fact that the antenna test structures have
different antennas and therefore the devices must suffer from different extent
damage or latent damage, it is not possible to select a good stress voltage to
evaluate oxides over a wide range of quality.
0.01
0.1
1
10
100
1000
-14 -12 -10 -8 -6
Ig,leak (A)
time-
to-b
reak
dow
n (s
)
M2, AR=100K,s=5um
good devices
damaged devices
good devices
M2, AR = 100000 s = 5 µm
Ig,leak (A)
Figure 3.23: Oxide time-to-breakdown as function of initial gate leakage current measured on the same NMOSFETs with M2 finger antenna.
The testing method with a stepped voltage stress brings more resolution over a
wide range of oxide quality. This method is promising especially in most of the
cases where we don’t know how much latent damage the devices receive from the
plasma processing, and then it is hard to select a suitable constant stress voltage.
3.3 Plasma property measurements
3.3.1 Langmuir probe
One of the most common methods of diagnosing a plasma system is to use a
Langmuir probe. It is commercially available and is widely used by plasma
processing equipment vendors as well as process-development engineers. The
Langmuir probe can in principle measure the electron temperature (Te), electron
density (ne), positive ion density (ni), plasma potential (Vp) as well as the floating
potential (Vf). It can measure all of these quantities as a function of position and
therefore map the distribution directly.
Characterization of plasma charging damage
47
Distance to the center of the wafer [mm]
-60 -40 -20 0 20 40 60
Dit(
ev-1
cm-2
)
1.5e+11
2.0e+11
2.5e+11
3.0e+11
ion
dens
ity
(cm
-3)
1.5e+10
2.0e+10
2.5e+10
3.0e+10
Plas
ma
pote
ntia
l (V
)
20
25
30
35
Spatial Variation of Dit
Spatial Variation of Ion Density
Spatial Variation of Plasma Potential
Figure 3.24: The spatial variation of interface trap density, plasma ion density, plasma potential across the wafer (tox = 12 nm).
In our study of plasma-exposed MOS capacitors (see section 3.3.2), the spatial
variation of plasma ion density (ni) and plasma potential (Vp) was measured by a
Langmuir probe. The results are presented in Figure 3.24, with the comparison of
the spatial variation of interface trap (Dit) density across the 5 min plasma-exposed
MOS capacitor. It is found that the interface trap density and plasma potential are
almost independent on the position, while the ion density is higher in the centre of
the wafer than that at the edge of the wafer. Apparently the damage on the gate
oxide is not strongly related to ion density. The damage can therefore be related to
plasma potential or a plasma characteristic we did not monitor.
3.3.2 Plasma damage monitor (PDM) tool
Plasma damage monitor (PDM, by Semiconductor Diagnostics Inc.) is a
contactless and damage-free measurement to determine the amount of charge built
up in an oxide layer by plasma [Fin96, Kar97, Saa00]. 1000 nm thermal oxide
layer is grown on blank test Si wafers. Before and after the treatment of the test
process step, the potential over the oxide layer can be measured by PDM. The
potential difference ( Vpdm) reflects the charging contribution of this test process
step. This PDM tool has been used to detect the process step that causes the
charging problem in chapter 7.
Chapter 3 48
3.4 Challenge in the future
As the gate-oxide gets thinner, the current available methods are incapable to
provide sufficient sensitivity from the viewpoint of damage impacting gate-oxide
reliability [Che00a].
The transistor parameter shifts are not anymore a good indicator when the
oxide is thinner than 5 nm. First, as the gate-oxide gets thinner, the defect
generation rate for a given level of plasma charging damage reduces, because the
voltage that supports a given tunnelling current reduces as well. When the oxide is
stressed at lower voltage, the defect generation rate per tunnel electron is greatly
reduced, caused among others by a difference in tunnelling mechanism (direct
tunnelling sets in around 3.5 nm). Secondly, as the gate-oxide gets thinner the
impact of a given density of oxide defects on the transistor parameters decreases as
well due to the increase in gate capacitance. Additionally, as gate-oxide thickness
gets below 5 nm, the defects that contribute to transistor parameter shifts can be
permanently annealed by the normal forming gas anneal condition [Pan01].
The current commonly used gate leakage (Ig,leak) measurement method also has
many shortcomings. For gate-oxide thinner than 5 nm, the preferred method for
plasma charging damage measurement changes from transistor parameter shift to
initial gate leakage measurement. More precisely the measured Ig,leak is the sum of
direct tunnelling current and post soft breakdown conduction current. When the
gate-oxide is thick, the portion of direct tunnelling current is negligible. As the
gate-oxide gets thinner, the fraction of direct tunnelling current gets larger and
overwhelms the Ig,leak, especially in a large device.
Another problem is the small size of the test structures. For plasma charging
damage studies, antennas are used to amplify the sensitivity to damage. The larger
the antenna ratio (AR, the ratio between the antenna area and the gate oxide area)
is, the more sensitive the test structure is. To accommodate the large AR and keep
the test structure size reasonable at the same time, the transistor size must be very
small. The problem of using very small devices is that it requires a huge number of
devices to be tested in order to obtain sufficient statistics that can indicate whether
the level of charging damage is too severe or not. This measurement dilemma is
due to the severe area and failure fraction scaling properties of thin oxide
breakdown [Che00b].
Characterization of plasma charging damage
49
3.5 Conclusions
In this section we summarized the results of the current-voltage (IV)
measurement, capacitance-voltage (CV) measurement and CCS measurement. To
study the plasma charging damage, we compared fresh samples with samples
subjected to an ICP plasma for various time intervals. The plasma charging
damage causes the distortion quasi-static capacitance-voltage (QSCV) and the shift
of high frequency CV (HFCV) shift, indicating the increase of interface state
density (Dit) and fixed oxide charge density. Moreover, a slow trap profiling
technique [Tan95, Tan96] was used to monitor the density, energy location and
response time of slow interface traps. With increasing exposure time, slow trap
density in the near interface region increases. If the expose time is long enough, it
appears to saturate.
From comparison between interface state generation caused by electrical
constant current stressing and by plasma exposure, we have found that electrical
stressing at Jst = -0.25 mAcm-2 can reproduce the same amount of damage as the
plasma exposure in our experiment. Combining equivalent plasma exposure times
and real exposure times follows one 2nd order polynomial fit.
A clear correlation is found between low levels of gate leakage and both HC
degradation and oxide breakdown. We demonstrate that the value of the gate
leakage current is not only a failure indicator in the region about 1 nA but also a
good indicator of the reliability of the devices in the region between 1 pA and 1
nA. Thus, from the value of gate leakage current, one can estimate the reliability of
the devices, saving precious measurement time.
The oxide breakdown measurement with a stepped voltage stress is a
perspective testing method to reveal latent as well as actual damage, for a wide
range of gate oxide quality in a very fast way.
3.6 References
[Ala99] M. A. Alam, B. Weir, J. Bude, P. Silverman and D. Monroe, “Explanation of soft and hard breakdown and its consequences for area scaling”, Int. electron devices meeting technical digest (IEDM), p. 449, 1999.
[Ata95] E. Atanassova, “Thin-oxide MOS damage caused by wafer charging in magnetized helium plasma”, Thin Solid Films, vol. 264, p. 72, 1995.
[Auc89] O. Auciello and D. L. Flamm, “Plasma diagnostics”, Academic Press, 1989.
[Aum98] P. K. Aum, R. Brandshaft, D. Brandshaft and T. Dao, “Controlling plasma charge damage in advanced semiconductor manufacturing—challenge of small feature
Chapter 3 50
size device, large chip size, and large wafer size”, IEEE Transactions on Electron Devices, vol. 45, no. 3, p. 722, 1998.
[Ber66] C. N. Berglund, “Surface states at steam-grown silicon-silicon dioxide interfaces”, IEEE Transactions on Electron Devices, vol. 13, p. 701, 1966.
[Bhu99] B. Bhuva, P. Mongkolkachit, N. Bui, and S. Kerns, “A study of effects of plasma-induced charging damage on hot-carrier lifetime using pre-stressed data”, Proc. of 4th PPID, p. 69, 1999.
[Car93] E. Cartier, J.H. Stathis and D.A. Buchanan, "Passivation and depassivation of Si dangling bonds at the Si/SiO2 interface by atomic hydrogen", Appl. Phys. Lett. 63, p. 1510, 1993.
[Che98] K. P. Cheung, C. T. Liu, C. P. Chang, J. I. Colonell, W. Y. C. Lai, C. S. Pai, H. Vaidya, R. Liu, J. T. Clemens and E. Hasegawa, "Charging damage in thin gate oxides -- better or worse?", Proc. of 3rd P2ID, p. 34, 1998.
[Che99] K. P. Cheung, P. Mason and J. T. Clemens, “Measuring plasma charging damage in ultra-thin gate-oxide”, 1st European Symp. Plasma Process Induced Damage, p. 88, 1999.
[Che00a] K. P. Cheung, P. Mason and D. Hwang, "Plasma charging damage of ultra-thin gate-oxide --- The measurement dilemma", Proc. of 5th P2ID, p. 10, 2000.
[Che00b] K. P. Cheung, “Plasma charging damage”, Springer-Verlag, London, ISBN 1-85233-144-5, 2000.
[Dru96] K. G. Druijf, J. M. M. Nijs, E. Drift, E. H. A. Granneman, and P. Balk, “Slow states in vaccum ultraviolet irradiated metal-oxide-silicon systems”, J. Appl. Phys., 79 (3), p. 1505, 1996.
[Fan92] S. Fang and J. P. McVittie, “A model and experiments for thin oxide damage from wafer charging in magnetron plasmas”, IEEE El. Dev. Lett., vol. 13, p. 347, 1992.
[Fin96] A. Findlay, L. Jastrzebski, J. Lagowski, K. Nauka, J. Lowell, J. Bertrand, A. Hoff, T. Esry, G. Brown, and C. Laughlin, Semicon Taiwan’96 Technical Conference, 1996.
[Gab97] C. T. Gabriel and J. L. Educate, “Application of damage measurement Techniques to a study of antenna structure charging”, Proc. of 2nd PPID, p. 91, 1997.
[Gua99] H. Guan, Y. H. Zhang, B. B. Jie, He-YD, M. F. Li, Z. Dong, J. Xie, JLF Wang, A.C. Yen, G. Sheng, and W. Li,, “Nondestructive DCIV method to evaluate plasma charging damage in ultrathin gate oxides”, IEEE El. Dev. Lett., vol. 20, p. 238, 1999.
[Jia98] J. Jiang, O. O. Awadelkarim and J. Werking, “A sensitive characterization parameter for plasma induced damage detection in ultrathin oxide submicron transistors”, J. Vac. Sci. Technol. A, vol.16, no. 3, p. 1664, 1998.
[Kar97] Y. Karzhavin, K. Lao, W. Wu, and C. Gelatos, “Plasma induced charging evaluation using SCA and PDM tools”, Proc. of 2nd P2ID, p. 143 1997.
[Kri98] S. Krishnan, K. Brennan and G. Xing, “Leakage current due to plasma induced damage in thin gate oxide MOD transistor”, Proc. 3rd P2ID, p. 201, 1998.
Characterization of plasma charging damage
51
[Lef88] H. Lefevre and M. Schulz, “The Si-SiO2 system”, edited by P. Balk (Elsevier, Amsterdam), p. 273, 1988.
[Lin98] H. C. Lin, M. F. Wang, C. C. Chen, S. K. Hsien, C. H. Chien, T. Y. Huang, C. Y. Chang, and T. S.Chao, “Characterization of Plasma Charging Damage in Ultrathin Gate Oxides”, Proc. of IEEE Int. Rel. Phys. Symp.(IRPS), p. 312, 1998.
[Mas82] J. Maserjian and N. Zamani, “Behavior of the Si/SiO2 interface observed by Fowler-Nordheim tunneling,”, J. Appl. Phys., vol. 53, p. 559, 1982.
[Mir00] E. Miranda, J. Sune, R. Rodriguez, M. Nafria, X. Aymerich, L. Fonseca and F. Campabadal, “Soft breakdown Conduction in Ultrathin (3–5 nm) gate dielectrics”, IEEE Transactions on Electron Devices, vol. 47, no. 1, p. 82, 2000.
[Moa92] R. Moazzami and C. Hu, “Stress-induced current in thin silicon dioxide films”, IEDM Tech. Dig., p. 139, 1992.
[Mur94] S. Murakawa and J.P McVittie, “Direct measurement of surface charging during plasma etching”, Part I. Japanese Journal of Applied Physics, 33(7B), p. 4446, 1994.
[Nar88] K. Naruke, S. Taguchi, and M. Wada, “Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness”, IEDM Tech. Dig., p. 424, 1988.
[Ngu87] T. N. Nguyen, P. Olivo, and B. Ricco, “A New Failure Mode of Very Thin (<50 Å) Thermal SiO2 Films," Proc. Int. Rel. Phys. Symp.(IRPS), p. 66, 1987.
[Nij94] J.M.M. de Nijs, K.G. Druijf, V.V. Afanas'ev, E. v.d Drift, and P. Balk, "H-induced donor-type Si/SiO2 interface states", Appl. Phys. Lett. 65, p. 2428, 1994
[Pan01] L. Pantisano and K. P. Cheung, “Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?”, IEEE Trans. Dev. Mat. Reliab., p. 109, 2001.
[Pat94] N. K. Patel and A. Toriumi, “Stress-induced leakage current in ultrathin SiO2 films”, Appl. Phys. Lett., vol. 64, no. 14, p. 1809, 1994.
[Rof91] R. Rofan and C. Hu, “Stress-Induced Oxide Leakage”, IEEE Electron Device Lett., vol. 12, no. 11, p. 632, 1991.
[Saa00] H. M’Saad, S. Desai, D. Witty, C. Hamon, S. Cho, and F. Moghadam, “Plasma-induced defect generation on silicon surfaces in HDP-CVD processing”, Proc. of 5th P2ID, p.42, 2000.
[Sch90] D. K. Schroder, “Semiconductor Material and Device Characterization”, Wiley-Interscience, New York, 1990.
[Shi91] H. Shin, C. C. King, T. Horiuchi, and C. Hu, “Thin Oxide Charging Current During Plasma Etching of Aluminum”, IEEE Electron Device Letters, vol. 12, no. 8, p. 404, 1991.
[Shi93] H. Shin and C. Hu, “Monitoring plasma-process induced damage in thin oxide”, IEEE Transaction on Semiconductor Manufacturing, vol. 6, no. 2, p.96, 1993.
[Sho89] F. Shone, K. Wu, J. Shaw, E. Hokelek, S. Mittal and A. Haranahalli, “Gate oxide charging and its elimination for metal antenna capacitor and transistor in VLSI CMOS double layer metal technology”, Proc. of Symposium on VLSI Technology, p. 73, 1989.
Chapter 3 52
[Sri97] A. Sridharan, J. Oh, C. R. Viswanathan, T. Brozek and J. Werking, “Leakage current due to plasma induced damage in thin gate oxide MOS transistors”, Proc. of 2nd P2ID, pp. 29-32, 1997.
[Tan95] P. Tanner, S. Dimitrijev and H. B. Harrison, “Technique for monitoring slow interface trap characteristics in MOS capacitors”, El. Lett., vol. 31, p. 1880, 1995.
[Tan96] P. Tanner, S. Dimitrijev, Y. T. Yeow, and H. B. Harrison, “Measurement of Plasma etch Damage by a New Slow Trap Profiling Technique”, IEEE El. Dev. Lett., vol. 17, p. 515, 1996.
[Tan97] P. Tanner, “The New Slow Trap Profiling Technique”, Ph.D. thesis, Griffith University, Australia, 1997.
[Tsu87] K. Tsunokuni, K. Nojiri, S. Kuboshima and K. Hirobe, “The effect of charge build up on gate oxide breakdown during dry etching”, Extended Abstract of International Conference on Solid State Devices and Materials, p. 195, 1987.
[Wad84] T. Wadanabe and Y. Yoshida, “Dielectric breakdown of gate insulator due to reactive ion etching”, Solid State Technology, P. 263, 1984.
Chapter 4 Plasma Charging Damage Affected by Antenna Ratio
In this chapter, yield data of antenna structures have been correlated to the AR in a 0.18 µm complementary-metal-oxide-semiconductor (CMOS) technology process. A model, which describes the quantitative relation between plasma process-induced oxide failure fraction and antenna ratio (AR), is presented. The model fits the experimental data very well. This model enables us to predict the yield loss of smaller AR structures that are difficult to measure but occur more often in real circuits. A designer is finally able to predict the plasma charging induced yield loss of the circuit, if the AR distribution of the circuit is available. With this investigation, AR design rules can be set more accurately to a specific layout of the circuit.
Chapter 4
54
4.1 Introduction
An antenna is a conductive layer which is attached to the device and is exposed
to plasma. In this chapter, we will discuss the situation when it is attached to the
gate of MOS (metal-oxide-silicon) transistor. During processing, both electrons
and positive ions from the plasma are impinging on the exposed antenna.
Depending on the charge balance condition, the electron flux might not equal the
ion flux, net positive or negative charges are therefore collected by the antenna.
The collected net charges are fed to the gate where it is neutralized by the current
tunneling across the gate-oxide, as shown in Figure 4.1. Clearly, the size of the
antenna exposed to the plasma plays a role in determining the magnitude of the net
charge collection rate and therefore the tunneling current. The antenna, in a rough
sense, is a current multiplier that amplifies the tunneling current density across the
gate-oxide. This is the so called “antenna effect”. The area ratio of the antenna to
the oxide under the gate is the “antenna ratio”.
FN tunneling current or direct tunneling current
Electrons and ions
FOX FOX
Figure 4.1: Schematic diagram of antenna effect
Conventional antenna charging theory predicts that the net current drawn from
the plasma is proportional to the charge collecting area of the antenna and the
damage of the transistor is proportional to antenna ratio (AR). The AR is therefore
an important parameter for plasma charging damage effects [Chi97]. Design rules
are commonly set in the semiconductor industry in order to limit the AR in the ICs
[Gab00a].
Plasma charging damage affected by antenna ratio
55
In production, charging damage is usually monitored by drop-in or scribe-line
charging-damage test structures. Normally, these test structures have larger AR’s
than product ICs. The reason for using large AR testers is to increase the charging
damage to a detectable level. In real IC manufacturing, the AR values of the
products seldom exceed 1500 [Luc98]. It makes no sense to test large AR
structures if one cannot use the results of the degradation of large AR testers to get
information of the products with small AR. Therefore, an investigation was
performed to extrapolate the degradation of small AR devices from results obtained
with large AR charging test structures.
In order to extrapolate the degradation of large AR testers to that of small AR
devices, the relation between AR and plasma damage is required. Recent papers
[Hwa99, Bos00] showed data suggesting a much weaker than proportional AR
dependence on plasma damage. However, a model, that can quantitatively describe
plasma damage dependence on the AR, has not been found yet. In this paper, a
model is proposed to describe the relation between the AR and the plasma damage.
4.2 Experimental
More than one hundred wafers have been subjected to an experimental 0.18 µm
CMOS backend-of-line process in this study. The charging sensitive antenna
structures of these wafers have been measured and analyzed. The antenna
structures consist of a PMOS transistor with a finger-shaped metal 2 antenna
connected to the gate. The antenna is not placed in the device active area. A
protection diode is connected to metal 3, in order to protect the gate oxide from
damage produced by plasma process steps following the metal 2 step, as shown in
Figure 4.2. This is commonly used finger antenna structure as described in
Chapter 3. The gate oxide thickness of the tester is 3.5 nm. The antenna ratio
varies from 1000 to 50000.
Chapter 4
56
M2
Protection diode
P+
N-well (float.)P sub.
M3
Transistor
Figure 4.2: Schematic layout of antenna test structures with metal 2 (M2) finger-shaped antenna. A protection diode is connected on metal 3 layer to protect the gate oxide from plasma charging damage above M2 layer.
After processing, the gate leakage current (Ig,leak) of the gate oxide is measured.
If more than 1 nA current is been detected, the device is considered to be failed
(hard breakdown or soft breakdown). The leakage current failure fraction indicates
the extent of the charging damage. Figure 4.3 depicts the leakage current failure
fraction of the antenna structures as function of the antenna ratio. It appears that
the increase of the failure fraction with the antenna ratio is nonlinear.
0%2%4%6%8%
10%12%14%16%18%
0 20000 40000 60000
Antenna ratio
failu
re fr
act
ion
reference
Antenna structures
Figure 4.3: Antenna ratio dependence on failure fraction of antenna structures. The failure fraction of the reference transistor (without antenna) is depicted for comparison.
Plasma charging damage affected by antenna ratio
57
4.3 Relation between failure fraction and antenna ratio
In this section, a theoretical model to explain the experiment results is proposed
and discussed.
4.3.1 Relation between the charging current and antenna ratio
The FN current (I) injected into the gate oxide of the tester during the plasma
process increases with the AR [Ma96]. The relation of the stress current and the AR
is discussed in this section.
The failure fraction (F) depends on the charge (Q) forced through the gate
oxide, and the charge (Q) is linked to the current (I) forced to the gate oxide.
Therefore, according to the failure fractions of antenna structures with different
AR’s, we can calculate what the stress currents have been.
The failure fraction (F) of capacitors as a function of charge forced through
oxide can be expressed by a Weibull distribution. This relation can be rewritten as
[Bos00],
1
%63 )]1ln([ FQItQ == (4.1)
where %63Q is the charge flown through the oxide inducing failure in
%631 1e devices and t is the critical plasma process time when the charging
is induced.
We define here I1 and I2 as the FN currents flowing in the gate oxide of the
tester with antenna ratios, respectively, AR1 and AR2. The ratio between I1 and I2
can be then expressed as
1
1
2
1
2
1
2
1
2
)1ln(
)1ln(====
F
F
Q
Q
tI
tI
I
I (4.2)
where F1 and F2 are the failure fraction of devices with antenna ratio AR1 and AR2
respectively, is the Weibull slope of the distribution.
In the above argument we have assumed that the %63Q was independent of the
stress current I. However, in reality this is not the case. The dependence of the
current I can be adequately described by
10%63
KIKQ = , (4.3)
Chapter 4
58
where the parameters 0K and 1K depend on oxt (gate oxide thickness) and can be
defined from a separate experiment [Bos00]. The inclusion of the %63Q current
dependence results in a modified Equation (4.2):
)1(
1
1
2 1
)1ln(
)1ln( K
F
F +
= (4.4)
Consequently, the corrected will be smaller than .
The failure fraction of antenna structures with different AR’s are obtained from
experiment data. By Equation (4.4), the ratio between I1 and I2 , the stress
currents from antenna structures with different AR’s is calculated. The data is
presented in Table 4.1. It is observed that when the antenna ratio increases by 10
times, the tunnelling current through the gate oxide increases by an almost
constant value, independently of the AR.
Table 4.1: Analysis of stress current increase with an increase of antenna ratio.
AR1 AR2 AR2/AR1 I2/I1
1000 10000 10 1.1
3000 30000 10 1.2
5000 50000 10 1.2
An assumption is now made based on the experimental data. Let us define
1AR , 2AR , 3AR ,…, kAR , as one series of antenna ratios with
)( jiARAR ji << , and: 1I , 2I , 3I ,…, kI as the corresponding charging current
series. Increasing the AR by a factor of , results in an increase of the current by a
constant factor of . is only determined by the antenna material and plasma
process.
From
=1
2
AR
AR , =2
3
AR
AR, … , =
1k
k
AR
AR ,… (4.5)
follows
=1
2
I
I , =
2
3
I
I, …, =
1k
k
I
I. …. (4.6)
From Equation (4.5), we get
11 ARAR k
k = (4.7)
Plasma charging damage affected by antenna ratio
59
and
1
lnln)1(AR
ARk k= . (4.8)
Hence
1
lnln
11
AR
ARk k= . (4.9)
From Equation (4.6), we also get
1
)1(II
k
k = . (4.10)
Then by substituting Equation (4.9) into Equation (4.10), the following equation
can be obtained
1
ln
ln
1
1
AR
AR
k
k
II = . (4.11)
Defining ln
1
=B Equation (4.11) can be rewritten as
( ) Bk
BAR
ARk AR
ARIBII
k ln
ln
11
1ln
1
11 == . (4.12)
Defining
B
ARIC
ln
11
1= (4.13)
and
Bln= , (4.14)
Equation (4.12) can be rewritten as
)( kk ARCI = . (4.15)
Since k is an arbitrary index, Equation (4.15) can be written in general as
)(ARCI = . (4.16)
Equation (4.16) shows that the relation between the charging current and antenna
ratio is a power law function. In this function, C and are constants ( is related
to the antenna material and a specific plasma process). Also the data presented in
[Nog00, Shi93] suggest a similar power law function between charging current and
AR.
Chapter 4
60
4.3.2 Relation between yield loss and antenna ratio
The yield loss (failure fraction) due to the plasma damage can be expressed as
=%63
exp1Q
QF . (4.17)
By substituting Equations (4.1) and (4.3)into Equation (4.17), the following
equation can be obtained
( )= +1
0
1exp1 KIK
tF . (4.18)
By Equations (4.16) and (4.18), we obtain
)1()(
0
)1(
0
11
1)1ln(
++
+
=
=
KKt
K
ARCK
t
IK
tF
. (4.19)
Defining
)1(
0
1+= KCK
tD (4.20)
and
)1( 1 += Kn , (4.21)
Equation (4.19) becomes
nARDF )()1ln( = . (4.22)
In this function, D is a constant that depends on the gate oxide thickness, the
plasma process and the antenna material. D and n can be obtained by fitting the
experimental results of charging testers with a series antenna structures. In this
experiment, 46.0n and 001.0D .
Figure 4.4 shows that the model fits the measured data very well. The failure
fraction at small AR values can be extrapolated by using the proposed model. It is
very useful for circuit designers. For instance, when AR equals 100 in the process
under study here, we predict a 0.9% failure fraction. This is sensibly high.
Plasma charging damage affected by antenna ratio
61
-5.5-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0
10 100 1000 10000 100000
Antenna ratio
ln[-
ln(1
-F)]
experiment
model
y=0,4578ln(x)-6,8634
Figure 4.4: The simulated and measured failure fraction as function of antenna ratio (AR).
Furthermore, the yield loss data of finger antenna structures from other
published literature [Gab00a, Car00] can also be fitted by using our model, as
shown in Figure 4.5.
-10
-8
-6
-4
-2
0
10 100 1000 10000 100000
Antenna ratio
ln[-
ln(1
-F)]
N-Channel PolyFinger Antenna
N-Channel MetalFinger Antenna
P-Channel PolyFinger Antenna
P-Channel MetalFinger Antenna
model
100000
Figure 4.5: Analysis of yield loss data taken from literature [Gab00a]. The analysis of the data from [Car00] gives similar results.
All the yield loss data in this chapter comes from finger antenna testers. It is
possible that the proposed model does not fit other kind of antenna very well. For
instance, the yield loss data of block antenna presented in [Gab00a] does not
follow this model. The reason probably is that finger antenna and block antenna
structures have different plasma charging mechanisms. Electron shading effect is a
dominant plasma damage mechanism with finger antenna structures but not with
block antenna structures.
Chapter 4
62
In addition, the plasma enhanced dielectric deposition was identified as the root
cause of this charging damage [Sca02]. The yield loss data from [Gab00a] is also
due to plasma deposition charging [Gab00b]. It is not clear yet that whether our
model can fit the plasma damage by other plasma processes.
4.4 Application to IC’s
Integrated circuit (IC) consists of a number of transistors with different AR. It
will fail as soon as one transistor fails. We define here that the failed fraction of
one transistor with antenna ratio ARk as FARk, which can be calculated by Equation
(4.22). The yield of one transistor is then (1- FARk). Now the plasma charging
affected yield (Y) of the whole IC can be calculated by using Equation (4.23)
( )=
=p
kARk
FY1
1 , (4.23)
where p is total number of the transistors. Note that only the part of the transistor
plasma charging effect is considered here, and our model is based on FN tunneling
failure mechanism.
4.5 Conclusions
In this chapter, based on the experimental results, a model has been proposed to
quantitatively correlate yield loss to AR. It has been shown that this model fits very
well the experimental results when finger-shaped antennas are used. By using this
model, one can predict the plasma process induced failure fraction as function of
antenna ratio. Based on this model, the failure fraction data obtained on large AR
antenna test structures can be extrapolated to the failure fraction of smaller AR
structures. Therefore, the transistor plasma charging yield of the circuit can be
calculated based on the AR distribution of the circuit. Our investigation is very
helpful to set AR design rule more accurately to a specific layout of the circuit.
4.6 References
[Bos00] G. Van den bosch, M. Creusen, R. Degraeve, B. Kaczer, and G. Groeseneken, “Anomalously weak antenna ratio dependence of plasma process-induced damage”, Proc. of 5th P2ID, p. 6, 2000.
[Car00] J. P. Carrère, J. C. Oberlin, and M. Haond, “Topographical dependence of charging and new phenomenon during inductively coupled plasma (ICP) CVD process”, Proc. of 5th P2ID, p. 164, 2000.
Plasma charging damage affected by antenna ratio
63
[Chi97] L. H. Chih, C. C. Hsing, W. M. Feng, H. T. Yuan, and C. C. Yen, “Model for photoresist-induced charging damage in ultra-thin gate oxides”, Proc. of 3rd P2ID, p. 247, 1997.
[Gab00a] C. T. Gabriel and E. de Muizon, “Quantifying a simple antenna design rule”, Proc. of 5th P2ID, p. 153, 2000.
[Gab00b] C. T. Gabriel, and R. Y. Kim, “Transient fuse structures: the role of metal etching vs. dielectric deposition”, Proc. of 5th P2ID, p. 168, 2000.
[Hwa99] G. S. Hwang and K.P. Giapis, “On the dependence of plasma-induced charging damage on antenna area”, Proc. of 4th P2ID, p. 21, 1999.
[Luc98] J. M. Luchies, P. Simon, F. Kuper, and W. Maly, “Relation between product yield and plasma process induced damage”, Proc. of 3rd P2ID, p. 7, 1998.
[Ma96] S. Ma and J.P. McVittie, “Prediction of plasma charging induced gate oxide tunneling current and antenna dependence by plasma charging probe”, Proc. of 1st P2ID, p. 20, 1996.
[Nog00] K. Noguchi, A. Matsumoto and N. Oda, “A model for evaluating cumulative oxide damage from multiple plasma processes”, IEEE Int. Reliability Phys. Symp. (IRPS), p. 364, 2000.
[Sca02] A. Scarpa, M. Diekema, C. van der Schaar, H. Valk, A. Harke and F. G. Kuper, “Process dependent antenna ratio rules for HSQ and FSG back-ends of (embedded flash) 0.18 µm CMOS technology” Proc. of 7th P2ID, p. 138, 2002.
[Shi93] H. Shin and C. Hu, “Monitoring plasma-process induced damage in thin oxide”, IEEE Trans. Semicond. Manufact., vol. 6, no. 2, p. 96. 1993.
Chapter 4
64
Chapter 5 Reliability Effects
The impact of plasma process-induced latent damage on the reliability of an IC is the subject of this chapter. First, a simple experimental method is used to demonstrates the pure plasma process-induced latent damage on gate oxide directly. With this method, the impact of additional defects generated by normal constant current stress (CCS) revealing technique is excluded. Secondly, the reliability tests of hot carrier (HC) stress and oxide breakdown demonstrate the relation of reliability loss of MOS transistors and the antenna ratios.
Chapter 5
66
5.1 Introduction
For very-large-scale-integration (VLSI) manufacturing of integrated circuits
(ICs), the use of high-density plasma-enhanced deposition and anisotropic etching
techniques is required. However, this kind of plasma techniques can cause
tunnelling currents to flow through thin gate oxides, resulting in charge built-up,
generation of new oxide traps and generation of interface states. Plasma charging
damage degrades many transistor parameters [Shi92, Nog94, Fan92]. It is not
difficult to imagine products that are sensitive to these parameters would suffer
yield loss and reliability degradation. It is generally accepted that plasma charging
damage to gate oxides can impact chip yield and reliability [And97, Har98, Luc98,
Gup97]. However, reliability data are rarely reported in the literature because they
are sensitive information. As a result, this is the one area of the plasma charging
damage field with little information that could be shared. Studies here focuse on
the impact of plasma latent damage to elementary transistor structures.
The latent damage induced by a plasma process has been identified as an
increased number of neutral electron traps and hole traps in the oxide and
passivated interface states [Bro97, Kin94]. It is indicated by electrical properties
shifting as function of antenna area or shape after constant current stress (CCS),
which is the typical property of plasma charging damage. Recently, many research
groups over the world have made a lot of efforts to evaluate the plasma process-
induced latent damage [Bro97, Pan00]. Normally, a high-field CCS is used to
reveal or re-awaken this hidden and inactive damage [Pan99]. However, this high-
field CCS also generates additional new defects in the gate oxide simultaneously.
In this chapter, a simple experimental method is proposed to directly
demonstrate the pure latent damage without any impact of additional defects
generated by CCS revealing technique. Single-layer (SL) antenna test structures
are used to evaluate plasma charging damage of each stand-alone plasma process
step. And the cumulative plasma charging damage of a few plasma processes is
evaluated by multi-layer (ML) antenna test structures. The test structure is
considered to suffer plasma charging damage when there is an antenna present
during a certain plasma process. Therefore, the number of layers determines how
many plasma process steps are used to introduce damage to the structures. The
used SL test structure and ML test structure and the experimental results are
presented in section 2. Moreover, the reliability test of hot carrier (HC) stress and
oxide breakdown with varying antenna ratios are presented in section 3.
Reliability effects
67
5.2 Plasma latent damage demonstrated by SL and ML test structures
5.2.1 SL and ML test structures
In this study, some wafers with SL test structure and ML test structure have
been subjected to a 0.35 µm CMOS backend-of-line process. After that, the
charging sensitive antenna structures [Ack99] of these wafers are evaluated. The
gate leakage current (Ig,leak) failure fraction and the wafer maps of SL and ML
antenna structures are compared, and the results are discussed.
Poly gate
M2
M3
Protection diode
active
Figure 5.1: Schematic layout of metal2 (M2) SL antenna structure with a finger-shaped M2 antenna. A protection diode is connected on metal3 layer to protect the gate oxide from plasma charging damage above M2 layer. This structure is supposed to only suffer damage during M2 process.
M3 V2 M2 V1 M1 Con
Poly Gate
Figure 5.2: Cross-section of a Poly-Si, Contact, metal1, via1, metal2, via2, and metal3 (Poly+Con+M1+V1+M2+V2+M3) ML antenna structure. This structure is supposed to suffer plasma charging damage during the whole process.
Chapter 5
68
In Figure 5.1 and Figure 5.2, the schematic of the SL and ML test structures
used in our study are depicted. The antenna ratio (AR) of all poly-si and metal
comb antenna is 10000. The AR is defined as the ratio between the area of the
antenna connected to the transistor and the active area of the latter. Contact or via
antenna has 1000 contacts or 1000 vias on a small plate.
5.2.2 Results and discussions of SL and ML test structures
The measurement results of the gate leakage current (Ig,leak) are presented in
Figure 5.3 and Figure 5.4. A test structure with the value of Ig,leak > 1 nA is
considered as a failure. The Figure 5.3 shows the wafer maps of failures of SL
structures after single plasma process and the Figure 5.4 shows the wafer maps of
failures of ML structures after two or more plasma processes. A plasma process in
this paper means the process to manufacture one layer such as M1, M2, and via 1.
As shown clearly in Figure 5.3 and Figure 5.4, the number of failed devices
increases fast with the number of antenna layers (plasma processes). The number
of damaged devices from Poly+Con+M1 structures, for example, is more than the
sum of the damaged devices from Poly+Con and the single-layer M1 antenna
structures. Compared with the damage that M1 plasma process induced to SL
antenna structure, the same M1 plasma process causes more failures on the multi-
layer structures that had already received plasma damage during the previous
Poly+Con steps.
Reference Poly Con M1 -11 -11 -11 -11 -11 -11 -11 -11
-12 -11 -12 -11 -11 -11 -11 -11 -11 -10 -11 -11 -11 -11 -11 -11
-11 -11 -11 -11 -11 -11 -11 -12 -11 -11 -11 -12 -13 -12 -12 -11 -11 -11 -11 -11 -11 -11 -12 -11
-11 -11 -11 -11 -11 -12 -11 -11 -6 -6 -6 -11 -11 -7 -11 -11 -11 -10 -11 -12 -11 -11 -11 -11
-11 -11 -12 -11 -11 -11 -11 -11 -11 -6 -11 -11 -11 -11 -10 -11 -6 -11 -11 -11 -11 -11 -11 -11
-11 -11 -11 -11 -11 -11 -11 -12 -10 -11 -10 -10 -8 -11 -11 -11 V1 M2 V2 M3-10 -10 -11 -12 -11 -11 -11 -11
-10 -9 -10 -10 -11 -11 -11 -11 -11 -10 -11 -11 -11 -11 -11 -11
-11 -10 -11 -11 -11 -10 -11 -11 -11 -11 -11 -12 -10 -9 -9 -11 -11 -11 -11 -12 -11 -11 -12 -11
-11 -9 -10 -9 -10 -10 -11 -11 -11 -11 -11 -11 -10 -10 -10 -10 -10 -11 -11 -12 -11 -11 -11 -11
-10 -10 -11 -10 -10 -11 -7 -11 -11 -11 -11 -11 -11 -11 -11 -11 -10 -10 -7 -11 -11 -11 -11 -11
-11 -12 -12 -10 -6 -11 -11 -11 -10 -11 -11 -11 -7 -12 -11 -11 Figure 5.3: Wafer map of Ig,leak of SL antenna structures. The value presented in the map is the log value of Ig,leak (A). Dark-red area indicates the failure (Ig,leak > 1 nA).
Reliability effects
69
Poly+Con Poly+Con+M1 Poly+Con+M1+V1-11 -11 -11 -11 -11 -11
-11 -11 -11 -11 -11 -6 -8 -11 -11 -7 -10 -7
-11 -11 -6 -6 -11 -11 -11 -11 -7 -7 -11 -11 -11 -10 -6 -6 -7 -6-11 -6 -6 -6 -6 -11 -10 -9 -6 -6 -6 -11 -10 -10 -7 -6 -7 -10
-7 -7 -11 -12 -11 -11 -11 -11 -6 -6 -7 -11 -11 -12 -7 -6 -11 -6
-6 -11 -11 -12 -6 -11 -6 -11 -11 -6 -11 -6
Poly+Con+M1+V1+M2 Poly+Con+M1+V1+M2+V2 Poly+Con+M1+V1+M2+V2+M3-6 -10 -6 -6 -6 -6
-10 -10 -10 -6 -11 -7 -11 -11 -6 -7 -6 -6
-6 -10 -6 -6 -10 -6 -9 -10 -6 -6 -10 -6 -7 -10 -10 -6 -9 -6
-10 -9 -6 -7 -7 -6 -10 -11 -6 -7 -11 -6 -6 -7 -7 -6 -7 -6
-10 -6 -6 -6 -6 -11 -10 -9 -6 -6 -11 -6 -11 -11 -6 -7 -6 -6
-6 -6 -12 -6 -6 -6 -6 -6 -11 -10 -10 -6 Figure 5.4: Wafer map of Ig,leak of ML antenna structures. The value presented in the map is the log value of Ig,leak (A). Dark-red area indicates the failure (Ig,leak > 1 nA).
In order to quantitatively compare the plasma damage to different structures,
the failure fraction is used in this paper. The failure fraction is defined as the
number of failed devices divided by the total number of investigated devices. In
the following, equations will be derived, which can extract the additional failures
caused by a certain plasma process step in ML antenna structures. Without the loss
of any generality, the Poly+Con+M1 ML structure and M1 SL structure are used
in the following derivations. Define 1MconPolyY ++ as the yield of Poly+Con+M1
structures, conPolyY + as the yield of Poly+Con structures, and MLMY ,1 as the yield of
M1 plasma process for the ML antenna structures. Since
MLMconPolyMconPoly YYY ,11 ×= +++ (5.1)
and
MLMMLM YF ,1,1 1= , (5.2)
therefore
conPoly
MconPolyMLM F
FF
+
++=1
11 1
,1 , (5.3)
where 1MconPolyF ++ is the failure fraction of Poly+Con+M1 structures, conPolyF + is
the failure fraction of Poly+Con structures, and MLMF ,1 is the M1 plasma process
induced failure to ML antenna structures. Because 1MconPolyF ++ and conPolyF + can
be obtained from the experiment, MLMF ,1 can be calculated. Hence, with equation
Chapter 5
70
(5.3), one plasma process induced extra failure fraction to ML antenna structures
can be extracted from the failure fractions of two corresponding ML antenna
structures.
The failure fraction comparison of different antenna structures is presented in
Table 5.1. F ‘one process’,SL is one plasma process induced failure fraction to single-
layer antenna structures. F ‘multi- procesess’,ML is a serial plasma processes induced
failure fraction to Multi-layer antenna structures. In the Table 5.1, F ‘one process’,SL
and F ‘multi-procesess’,ML are experimental data. F ‘one process’,ML is one plasma
process induced extra failure fraction to ML antenna structures, which is extracted
from the failure fractions of two corresponding ML antenna structures with
equation (5.3).
In Table 5.1, 1MconPolyF ++ = 40% and conPolyF + = 32%, with equation (5.3), we
can get MLMF ,1 = 12%. Therefore, in our case, 12% of the devices that are not
damaged during poly and contact plasma processes are damaged during M1 plasma
process. However, the same M1 plasma process causes only 0.4% failure on the
SL antenna structures. The reason for this phenomenon is plasma process-induced
latent damage.
After the poly and contact plasma process, 32% of the total devices failed and
the other 68% of the total devices are survived. A failure is defined as Ig,leak > 1
nA. Any increase in Ig below this value is hence not detected as a failure, but it
does not mean the device does not receive any damage. Those 68% devices do not
show failure, but they are much weaker because of the latent damage generated by
plasma processes. Therefore, they are more susceptible to subsequent M1 plasma
process. On the other hand, SL antenna structures have only one antenna. The
devices are fresh and have not suffered plasma damage from antecedent plasma
processes. They are more robust. This is the reason why the failure fraction of the
M1 plasma process to ML antenna structure is much higher that to SL antenna
structure.
With Equation (5.3), the failure fraction of other plasma processes to ML
antenna structure are also calculated and listed in Table 5.1. The comparison of
these values to the failure fraction of the same plasma process to the SL antenna
structure also show the existence of the plasma-induced latent damage. Moreover,
due to the existence of latent damage in ML structures, the value of F ‘one process’,ML
is higher than that of F ‘one process’,SL in the Table 5.1.
Reliability effects
71
Table 5.1: Failure fraction comparison
F ‘one process’,SL F ‘multi- procesess’,ML F ‘one process’,ML (caculated)
Fpoly,SL 17% Fpoly,ML 17% Fpoly,ML
Fcon,SL 10% Fpoly+con,ML 32% Fcon,ML 18%
FM1,SL 0.4% Fpoly+con+M1,ML 40% FM1,ML 12%
FV1,SL 1% Fpoly+con+M1+V1,ML 44% FV1,ML 7%
FM2,SL 6% Fpoly+con+M1+V1+M2,ML 66% FM2,ML 39%
FV2,SL 0.4% Fpoly+con+M1+V1+M2+V2,ML 65% FV2,ML -3% FM3,SL 4% Fpoly+con+M1+V1+M2+V2+V3,ML 86% FM3,ML 60%
In order to make the comparison more clear, the failure fraction of the same
plasma process to the SL structure and ML structure are depicted in Figure 5.5.
From the Figure 5.5, it can be observed clearly that the same plasma process
always causes more damage on ML antenna structures. The reason is that the ML
structures are suffered latent damage from antecedent plasma process.
-10%
0%
10%
20%
30%
40%
50%
60%
70%
poly con M1 V1 M2 V2 M3
Plasma process
Fa
ilu
re f
ract
ion
Failure fractionof singleprocess stepsextracted fromSL antennastructuresfailure fractionof one singleprocess stepsextracted fromML antennastrucutures
Figure 5.5: Comparison of one-plasma-process induced failure fraction between SL antenna structures and ML antenna structures. The small strange value of V2 is probably caused by the noise of the measurement.
5.3 Reliability test on MOS transistors with different antenna ratios
The test structures have been subjected to a 0.35 µm CMOS backend-of-line
process. The test structures are small transistors with W × L = 0.35 µm × 2 µm.
The gate oxide thickness is 7.5 nm. The charging tester consists of a MOSFET
Chapter 5
72
with a finger-shaped metal antenna connected to the gate on the first metal level.
The antenna ratio (AR), which is defined as the ratio between the area of the
antenna connected to the transistor and the active area of the latter are 1000,
10000, and 100000. The protection diode is connected to gate at subsequent level,
in order to protect the gate oxide from damage produced by plasma process steps
following the patterning antenna.
Hot carrier (HC) stress was performed on PMOS transistors. The PMOS
transistors were stressed at Vd = -6.5 V, Vg = -1.9 V. This Vg was chosen to the
maximize bulk current Ib. As well known, the HC mechanism of PMOS transistors
under Ib, max stress condition is the channel shortening effect due to electron
trapping near the drain region. This leads to increased drain current and reduced Vt
[Yao99]. The HC lifetime, in this study, is defined as the time when the PMOS has
a 10 mV Vt shift. The HC lifetime as function of AR is shown in Figure 5.6 (a) .
The transistor with larger AR failed earlier. The almost 1:1 ratio between HC
lifetime degradation and the antenna ratio is also reported by other publications
[Ran99].
Moreover, oxide time-to-breakdown (tbd) was measured with a 5 V constant
voltage stress. The results are presented in Figure 5.6 (b). The correlation between
tbd and AR is clear. The tbd of transistor with larger AR is shorter. The strong
correlation with the antenna ratio is considered as a signature for plasma damage
being the cause of the degradation [Sho89, Shi91].
1
10
100
1000
10000
100 1000 10000 100000 1000000
AR
fail
time
at -6
.5V
HC
str
ess
(s)
1
10
100
1000
100 1000 10000 100000 1000000
AR
tbd (
s)
(a) (b) Figure 5.6: (a) HC lifetime as function of antenna ratio (AR); (b) time-to-breakdown (tbd) as function of antenna ratio (AR)
Reliability effects
73
5.4 Conclusions
The presented experimental data clearly demonstrate the existence of latent
damage. The ML structures that were exposed, but did not fail from antecedent
plasma charging damage, are more susceptible to subsequent plasma process
compared with fresh SL structures that are free from antecedent plasma charging
damage. The strong correlation between the HC lifetime and time-to-breakdown
with the antenna ratio indicates that the plasma charging causes the degradation of
reliability. Hence, plasma process may generate not only active damage but also
latent damage,
5.5 References
[Ack99] J. Ackaert, E. De Backer, P. Coppens, and M. Creusen, “Plasma damage antenna test structure matrix description, application for optimization HDP oxide deposition, metal etch, Ar-preclean and passivation processing in sub-half micro CMOS processing”, Proc. of 1st European Symp. on Plasma Process Induced Damage, p. 70, 1999.
[And97] P. Andrews and A. Blaum, “CMOS-circuit protection against PPID for yield enhancement”, Proc. of 2nd P2ID, p. 167, 1997.
[Bro97] T. Brozek and C. R. Viswanathan, “Increased hole trapping in gate oxides as latent damage from plasma charging”, Semicond. Sci. Technol., vol. 12, p. 1551, 1997.
[Fan92] S. Fang and J. P. McVittie, “A model and experiments for thin oxide damage from wafer charging in magnetron plasmas”, IEEE El. Dev. Lett., vol. 13, p. 347, 1992.
[Gup97] I. J. Gupta, K. Taylor, D. Buck and S. Krishnan, “Antenna damage from a plasma TEOS deposition reactor: relationship with surface charge and RF sensor measurements”, IRW report, p. 26, 1997.
[Har98] E. B. Harris, “Charging damage in Metal-Oxide-Metal capacitors”, Proc. of 3rd P2ID, p. 15, 1998.
[Kin94] J. C. King and C. Hu, “Effect of low and high temperature anneal on process-induced damage of gate oxide”, IEEE Electron Device Lett., vol. 15, p. 475, 1994.
[Luc98] J. M. Luchies, P. Simon, F. Kuper, and W. Maly, “Relation between product yield and plasma process induced damage”, Proc. of 3rd P2ID, p. 7, 1998.
[Nog94] K. Noguchi and K. Okumura, “The effect of plasma-induced oxide and interface degradation on hot carrier reliability”, Proc. of IEEE Int. Rel. Phys. Symp. (IRPS), p 232, 1994.
Chapter 5
74
[Pan00] L. Pantisano, A. Paccagnella, G. Cellere, P. Colombo and M. G. Valentini, “Interface state creation due to low-field latent damage depassivation”, Proc. of 5th P2ID, p. 93, 2000.
[Pan99] L. Pantisano, A. Paccagnella, P. Colombo and M. G. Valentini, “Plasma damage impact on NMOS electrical characteristics during a CCS stress”, Proc. of 4th P2ID, p. 73, 1999.
[Ran99] S. Rangan “A model for channel hot carrier reliability degradation due to plasma damage in MOS devices”, Proc. of IEEE Intern. Reliability Physics Symposium (IRPS), 1999.
[Shi91] H. Shin, C. C. King, T. Horiuchi, and C. Hu, “Thin oxide charging current during plasma etching of aluminum”, IEEE Electron Device Letters, vol. 12, no. 8, p. 404, 1991.
[Shi92] H. Shin, C. C. King and C. Hu, “Thin oxide damage by plasma etching and ashing processes”, Proc. of IEEE Int. Rel. Phys. Symp.(IRPS), p 37, 1992.
[Sho89] F. Shone, K. Wu, J. Shaw, E. Hokelek, S. Mittal and A. Haranahalli, “Gate oxide charging and its elimination for metal antenna capacitor and transistor in VLSI CMOS double layer metal technology”, Symposium on VLSI Technology, p73, 1989.
[Yao99] P. Yao “Hot-carrier degradation study of high density plasma (HDP) oxide deposition process in deep-submicron NMOSFETS”, SPIE, vol. 3884, p. 116, 1999.
Chapter 6 Design Strategy and Protection Scheme
After a plasma process is identified to be the source of charging damage, the best practice is to reduce it. There are different methods to reduce plasma charging damage. One way is to change the plasma process or reactor design. The other way is to prevent plasma charging damage by design in the layout phase. The former method is highly process specific and cannot be generalized. In this chapter, we will discuss the method in the layout phase, which can be generally implemented in different plasma systems.
Chapter 6
76
6.1 Introduction
Plasma processes are widely used in the manufacturing of VLSI devices for
etching and deposition. However, it also induces charging damage to the devices.
After a plasma process is identified to be the source of charging damage, the best
practice is to reduce it. There are different methods to reduce plasma charging
damage. One way is to change the plasma process parameters such as the power,
the chamber pressure, or gap between the top electrode and the wafer. These tricks
come from trial and error types of trouble-shooting. They could not be
implemented to other different plasma systems. In this chapter, we will focus on
the other way to prevent charging damage in the design and layout phase charging
damage, which can be generally implemented to different plasma systems in the IC
manufacturing.
Generally, a maximum allowed antenna ratio design rule is used to limit the
plasma charging damage. Currently, computer-aided-design (CAD) tools cannot
automatically layout the circuit with the antenna rule as one of the constraints.
Antenna rule violation checking is done as a separate step after the layout is
completed. When antenna rule violation is found, the common method of handling
the problem is to insert a minimum size diode if space is available. In this chapter,
besides the discussion the effect of diode protection at high temperature, a novel
first order self-balancing interconnect layout design is proposed.
6.2 Temperature effect on protection diode
6.2.1 Introduction
In 1989, Shone et al. proposed protection diodes as a means of avoiding wafer
charging [Sho89]. The diodes are connected in parallel to the gate providing an
alternate leakage path for the plasma-induced current. Historically, the junction
breakdown voltage has had a lower value than the gate oxide breakdown voltage
and therefore, even a reverse bias has been effective in protecting gates. As the
thickness of the gate oxide is scaling down, the gate oxide breakdown voltage
strongly decreases. It was predicted that for oxides thinner than 11 nm, gated diode
provides little or no protection [Shi93]. However, later it was reported that the
protection by diodes is still effective for 2.1 nm ~ 3.2 nm thin gate oxide FETs
[Kri98]. Even reverse diodes with high junction breakdown voltage can still offer
some charging protection. This protection is due to their reverse bias leakage and
Design strategy and protection scheme
77
can be adequate if they have a large enough area [Par99]. Apparently the
protection diodes are more capable than what was anticipated. One of the
explanations of the enhancement of the efficacy of the protection diode is the
presence of light during plasma processing. During the plasma process the diode
reverse leakage current is enhanced by a photon generated current resulting from
the light emission of the plasma [Par99]. However, the light effect is strongly
affected by the metal on the top of the diode. If the diode is shielded from plasma
illumination by metal, the reverse current of the diode rapidly decrease by more
than one order of magnitude [Shi96]. As the integration density of the VLSI
technology continuously increases, the metal layers fabricated in the back-end
processes increases from 3 layers to 5 layers, and even more. Furthermore, tiling of
metal will block even more light, which makes it more likely that the protection
diodes are shielded by the metal and there is no plasma-assisted photoconduction
in these diodes.
In this section, the diode characteristics at high temperature is studied. During
the plasma etching the wafers can be heated to about 70°C and during the plasma
depositions processes, the ambient temperate is even 400 °C. Recently more and
more research groups report the plasma damage is mainly due to the deposition
process [Che00, Car00, Sca01]. Therefore, studying the diode characteristics at
high temperature becomes important for plasma damage protection prediction.
Since it is not possible in practice to measure the diode characteristics at 400 °C, a
commercial device simulator called SILVACO is used to investigate the diode
behaviour at elevated temperatures. The efficacy of different diodes is also
compared under both positive and negative voltage charging. Based on our
investigations, a strategic protection scheme for plasma charging damage is
proposed.
6.2.2 Experimental details
The test structures have been subjected to an experimental 0.18 µm CMOS
backend-of-line process. The test structures are small transistors with minimum
channel length and 3.5 nm gate oxide thickness. The charging tester consists of a
MOS transistor with a finger-shaped antenna connected to the gate. A protection
diode is connected to gate at the same level as the antenna in order to test its
protection efficacy, as shown in Figure 6.1.
Chapter 6
78
Poly gate
M2
M2
Protection diode
active
Figure 6.1: Schematic layout of tester with metal2 finger antenna. The protection structure is connected on the same level of antenna.
In our study, the test structures are protected by different drain-well diodes. The
schematic view of the different protection diodes is shown in Figure 6.2. The n+/p
diode and p+/n diode are normal diode. However, the double-sided diode is
floating n-well diode. The antennas of all test structures with protection at the
antenna level are finger antennas with narrow spacing (0.32 µm). Since the leakage
current of floating n-well protection diode (i.e. double-sided diode) is negligible at
room temperature, it can be used both for PMOSFET and NMOSFET. Considering
the working potential of the MOSFET, n+/psub and p+/nwell, so called single
diode can only be used for NMOSFET and PMOSFET respectively.
Moreover, antenna test structures with various spacing between the fingers of
the antennas (from 0.32 µm to 4 µm) have been designed, in order to investigate
the electron shading (ES) effect and the polarity of the plasma charging.
n+
pWell
p+
nWell
psub
p+
nwell
psub
(a) n+/p diode (b) p+/n diode (c) double-sided diode
Figure 6.2: Schematic overview of different protection schemes.
The IV characteristics of different diodes under positive as well as negative
voltage charging is compared by simulation. The antenna testers protected by
different diodes have been measured and analyzed. An antenna tester is considered
to fail when the leakage current (Ig,leak) measured through its gate oxide exceeds
Design strategy and protection scheme
79
0.1 nA, indicating that (soft or hard) breakdown occurred. The failure fraction of
the antenna testers protected by different diodes has been compared.
6.2.3 Results and discussion
6.2.3.1 Simulation results
The temperature dependence of the saturation current IS of a diode can be
determined by [Sno89]:
( ) ( ) ( )
( )=
01
01
2
2
101 TTNk
TTqE
TT
TITI g
N
ss exp/
(6.1)
where N is the emission coefficient, which is a model parameter, k is
Boltzmann's constant, q is the electronic charge, Eg is the energy gap which is a
model parameter. The temperature parameter is an exponential factor. The leakage
current of the double-sided diode is enormously influenced by the temperature, as
shown in Figure 6.3 and Figure 6.4. By increasing the temperate by 100 degrees,
the leakage current is about 1000 times higher.
1.0E-18
1.0E-16
1.0E-14
1.0E-12
1.0E-10
1.0E-08
1.0E-06
1.0E-04
-0.1 0.4 0.9 1.4
-V (V)
-I (
A)
25
125
200
300
400
Figure 6.3: Simulation of leakage current of the double-sided diode under negative bias at different temperatures (°C).
Chapter 6
80
1.0E-161.0E-151.0E-141.0E-13
1.0E-121.0E-111.0E-10
1.0E-091.0E-08
1.0E-071.0E-06
1.0E-051.0E-04
0 100 200 300 400 500
T(oC)
I (A
)
double-sided diode(positive biased)double-sided diode(negaitive biased)
Figure 6.4: The leakage current of the double-sided diode is evaluated by high temperature. Note that the current values presented in the figure are absolute values. The bias voltage is ± 0.75 V.
The IV characteristic of different diodes under both positive charge and
negative charge conditions are compared by simulation. The results are presented
in Figure 6.5 and Figure 6.6.
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
-0.1 0.4 0.9 1.4
V (V)
I (A
)
double-sided diode
n+/p single diode
Figure 6.5: Simulations of the single diode and double-sided diode current at 400 °C under positive bias.
Design strategy and protection scheme
81
1.0E-11
1.0E-09
1.0E-07
1.0E-05
1.0E-03
1.0E-01
-0.1 0.4 0.9 1.4-V (V)
-I (
A)
double-sided diode
n+/p single diode
Figure 6.6: Simulations of the single diode and double-sided diode current at 400 °C under negative bias.
The double-sided diode shows better efficacy in the case the gate of the
MOSFET is positively charging. The leakage current of double-sided diode is 100
times higher than that of reverse biased n+/p single diode. Under negative
charging, the n+/p single diode has higher current because it is forward biased.
The p+/n single diode has similar results. The leakage current of double-sided
diode is 100 times higher than that of reverse biased p+/n single diode. Under
positive charging, the p+/n single diode has higher current because it is forward
biased.
6.2.3.2 Experimental results
The antenna testers protected by different diodes have been measured. In Figure
6.7, the Ig,leak of the antenna testers protected by different diodes has been
compared.
0%
20%
40%
60%
80%
100%
-12 -10 -8 -6Log(Ig,leak (A))
Co
umm
ula
tive
pro
bab
ility
double-sided diode
n+/p diode
Figure 6.7: Distribution of the gate leakage current.
Chapter 6
82
The failed fraction of the antenna testers protected by different diodes has been
compared, as presented in Table 6.1. The results show that the antenna structures
protected by double-sided diode fail less than that protected by n+/p single diode.
Table 6.1: Failed fraction (%) of NMOS transistor with protection diode at the antenna level.
Antenna double-sided diode n+/p diode
Poly-Si
LIL
M2
0.20
2.45
0.25
11.60
10.98
2.45
LIL: Local interconnect level.
Double-sided diode: p+/nwell/psub
The failure fractions of antenna test structures with varying inter-finger spacing
are compared in Figure 6.8. It was reported that dense finger antennas collect
positive charging and the damage increases with the decrease of the inter-line
spacing due to ES effect; while the sparse finger antennas collect negative
charging and the damage increases with the increase of the inter-line spacing due
to extended ES effect [Car00, Has98]. In Figure 6.8 it is shown that the failure
fraction of antenna testers with inter-line spacing narrower than 1 µm increases
with the decrease of the inter-line spacing, indicating the antennas collects positive
charging; while the failure fraction of antenna testers with inter-line spacing wider
than 2 µm increases with the increase of the inter-line spacing, indicating the
antennas collect positive charging. The turn over trend can be clearly observed in
Figure 6.8.
0
5
10
15
20
25
0 1 2 3 4 5spacing (um)
Fai
lure
frac
tion
Figure 6.8: Dependence of damage on the spacing between fingers of the antenna.
Design strategy and protection scheme
83
6.2.3.3 The correlation between the diode simulation results and the experiment results of antenna structures
The simulation results at high temperature show that the leakage current of
double-sided diode is higher than that of single n+/p single diode under positive
voltage charging. This means that the double-sided diode could provide better
protection, if the antenna structure is under positive voltage charging in a high
temperature environment.
It is discussed in previous section that the antenna with inter-line spacing
narrower than 1 µm collects positive charges. The antennas of all test structures
with protection on the antenna level are finger antenna with narrow spacing (0.32
µm). Therefore the test structures with protection diodes used in this experiment
are under positive voltage charging. It is also detected that the charging damage is
caused by a plasma deposition process with high environment temperature around
400 °C [Sca01]. The experiment results show that the test structures protected by
double-sided diode fail much less than that protected by single n+/p diode. Hence,
the simulation results explain the experiment results very well.
6.2.4 Summary
The leakage current of different drain-well diodes for plasma-charging
protection has been simulated at high temperature. The simulation shows that the
high ambient temperature, especially during plasma deposition process,
enormously enhanced the efficacy of both single and double diodes in protecting
very thin gate oxides. The efficacy of different diodes has been compared by
simulation and experiment. The best protection scheme depends on the specific
charging polarity and temperature. For plasma deposition charging at high
temperature, the double-sided diode is recommended. Considering the fact that
plasma deposition is gaining importance, double-sided diodes are considered the
best choice in most cases.
6.3 Self-balancing interconnect layout
6.3.1 Introduction
The interconnect layout has a considerable effect on the charging damage
induced by plasma-process, since it affects the current-density stress levels
experienced by dielectric layers. It was reported that dense interconnect lines
Chapter 6
84
collect positive charges due to the electron shading (ES) effect [Has94] but sparse
interconnect lines collect negative charges due to the extended electron shading
effect (EES) [Has98]. In this section, a novel first order self-balancing interconnect
layout design is proposed to reduce plasma charging damage in design phase.
6.3.2 Experimental details
The test structures have been subjected to an experimental 0.35 µm CMOS
backend-of-line process. The test structures consist of small transistor with W x L
= 2 µm x 0.35 µm. The gate oxide thickness is 7.5 nm. The interconnect metal
lines are patterned with a medium density plasma system.
To simulate the interconnect lines, a finger-shaped conductor is designed and
connected to the gate of a MOS transistor The conductor collects the ions and
electrons from the plasma during the processing and is therefore called antenna.
The antenna ratio is defined as the area ratio of the antenna to the gate oxide. The
induced gate tunnelling current density is proportional to the antenna ratio.
In this study, two conventional finger-shaped antennas and one new dense-
sparse interlaced antenna were designed. The dense-line antenna and sparse-line
antenna are commonly used in the study of plasma charging damage. In this
experiment, they were designed with interspacing of 0.6 µm and of 5 µm
respectively. The new dense-sparse interlaced antenna was designed as such that
the spacing between the metal lines is alternately wide (5 µm) and narrow (0.6
µm). The schematic view of these structures is shown in Figure 6.9. The antenna
ratios of these charging testers are 10000 and 100000. The antennas are all in
metal 2 level.
Furthermore, a special structure combining 3 antennas with 3 transistors is
designed as a special case study. The schematic view is shown in Figure 6.10 (a).
Since they have 3 antennas and 3 transistors, they were called “TriMOS”
structures. One transistor is in the middle (“TriMOS-M”), one is on the left
(“TriMOS-L”), and another is on the right (“TriMOS-R”). The antenna ratio for
each transistor of this “TriMOS” structure is 10000. Another two structures are
also designed with minor modification based on this “TriMOS-L/M/R” structure.
Because their antennas are so similar to the above “TriMOS” structure, we still
give them a name with “TriMOS-” though these two structures do not have 3
transistors anymore. The one with two floating antennas is called “TriMOS-
floating”, the other with two grounded antennas is called “TriMOS-ground”. Note
that the floating antennas and grounded antennas are not connected to the MOS
Design strategy and protection scheme
85
structure. Therefore, the antenna ratio for these two modified “TriMOS” structure
is still 10000, the same with “TriMOS-L/M/R” structures. Note that the antennas
are all in the same level (Metal 2 level). The schematic view of these structures is
shown in Figure 6.10.
MOS-sparse
sparse antenna
b
dense antenna
a
MOS-dense
5µm
c
0.6µm
MOS-interlaced
dense-sparse interlaced antenna
Figure 6.9: Schematic view of structure (a) conventional dense-line antenna structure with interspacing of 0.6 µm, (b) conventional sparse-line antenna structure with interspacing of 5 µm (c) our new dense-sparse interlaced antenna structure with interspacing of 0.6/5 µm.
TriMOS-floating
5um
0.6um
line
b
floating floating
TriMOS-L TriMOS-M TriMOS-R
5um
0.6um 0.6um
a
5um
0.6um
line
ground ground
c
TriMOS-ground
Figure 6.10: Schematic view of (a) “TriMOS-L/M/R” structure (b) modified “TriMOS” structure with two floating antennas (c) modified “TriMOS” structure with two grounded antennas. Note that the antennas are all in the same level (Metal 2 level).
For some antenna structures, protection diodes are connected the gate at metal
3, in order to protect the gate oxide from damage produced by plasma process
steps following the metal 2 step. For other antenna structures, protection diodes are
not used. Therefore, we can verify the function of the protection diode.
Additionally, if we want to measure Qbd or Ebd of those antenna structures, we can
stress them at high voltage for, which is above the diode junction breakdown. Due
Chapter 6
86
to the limit of space, only NMOS transistors are used as test vehicle. However, we
believe that, for PMOS transistor the result and mechanism we discussed in the
following sections should be similar. Therefore, in the pictures and the context of
the flowing sections, NMOS is not particularly mentioned.
To detect plasma damage, the gate leakage current (Ig,leak) is measured by
applying a gate voltage of Vg = 3.74 V. A charging tester is considered to be failed
if the Ig,leak measured through its gate oxide exceeds 0.1 nA, indicating that (soft or
hard) breakdown occurred. The 0.1 nA is selected as failure criterion based on the
leak current distribution, as shown in Figure 6.11. The devices with Ig,leak higher
than 0.1 nA, diverge from the intrinsic slope, indicating extrinsic damage induced
by plasma charging.
0%
1%
10%
100%
-13 -12 -11 -10 -9 -8 -7 -6 -5
Log [Ig,leak (A)]
Cu
mm
ula
tive
pro
bab
ility
Figure 6.11: Distribution of gate leakage current.
6.3.3 Results and discussions
The failure fractions of normal MOS antenna structures and special “TriMOS”
structures with same antenna ratio (AR = 10000) have been listed in Table 1. In
this table, 0.6 µm spacing and 5 µm spacing stands for dense antenna structure
and sparse antenna structure respectively, while 0.6/5 µm spacing stands for dense-
sparse interlaced antenna structure. Apparently, the antenna structure with diode
protection failed much less than those without diode protection. The fractions of
the structure without diode protection are around 3 times higher than those with
diode protection.
Design strategy and protection scheme
87
Table 6.2: Failure fractions of normal MOS antenna structures and special “TriMOS” structures with same antenna ratio (AR = 10000)
Failure fraction of antenna structures
0.6 µm spacing
0.6/5 µm spacing
5 µm spacing
TriMOS-L
TriMOS-M
TriMOS-R
TriMOS-floating
TriMOS-grounded
With diode protection
6.7 NA 14.9 5.9 4.3 7.4 NA NA
Without diode protection
58.2 27 61.3 19.9 16 20.3 18.7 14.8
NA: structures are not available.
The failure fractions of MOS structures with new dense-sparse interlaced
antenna failed much less than those with conventional dense antenna and sparse
antenna, as shown in Figure 6.12. Note that there is no protection diode designed
for this dense-sparse interlaced antenna. The bond pad in the up level metal layer
works as an antenna and therefore introduces plasma charging damage to the
device too. The failure fraction we get, in fact is a sum effect of the all the process
steps start from metal 2. We can expect that the device with dense-sparse
interlaced antenna would fail much less if there is a diode to avoid the damage
produced by plasma process steps following the metal 2 step.
0
20
40
60
80
100
120
0.6 um 0.6/5 um 5 um
antenna structures
failu
re fr
actio
n (%
)
MOS with dense-sparse interlaced antenna failed much less.
Figure 6.12: Comparison of the failure fraction of MOS with dense-sparse interlaced antenna, dense antenna, and sparse antenna.
Chapter 6
88
0
10
20
30
40
50
60
70
0.6um TriMOS-L TriMOS-M TriMOS-R 5um
antenna structures
failu
re f
ract
ion
(%
)
with diodeprotection
without diodeprotection
TriMOS-M is the structure with lowest failure fraction.
Figure 6.13: Comparison of the failure fraction of normal antenna structures and “TriMOS-L/M/R” antenna structures.
The failure fractions of the special “TriMOS” structures have been compared to
the two conventional MOS charging structures with a single 0.6 µm or 5 µm
spacing finger antenna. All test structures have the same 10000 antenna ratio. The
conventional MOS charging structures both with 0.6 µm or 5 µm finger spacing,
failed more than any of the “TriMOS” structures. For the structures either with
diode protection or without diode protection, the middle antenna (“TriMOS-M”)
fails less than both the left antenna (“TriMOS-L”) and right antenna (“TriMOS-
R”). The conventional MOS structures with a 5 µm finger spacing antenna failed
more than those with a 0.6 µm finger spacing antenna. The result is presented in
Figure 6.13.
“TriMOS-floating” and “TriMOS-ground” structures are compared with
“TriMOS-M”, “TriMOS-L” and “TriMOS-R” in Figure 6.14. Please note that the
same range of y-axes is used for Figure 6.13 and Figure 6.14 for the purpose of
comparison. Since they have almost the same antenna features, their failure
fractions are quite close to “TriMOS-M” as what we expected. The failure fraction
of these “TriMOS” structures is about 40 percent less than the dense or sparse
antenna structures.
Design strategy and protection scheme
89
0
10
20
30
40
50
60
70
TriMOS-L TriMOS-M TriMOS-R TriMOS-floating
TriMOS-ground
antenna structures
fail
ure
fra
ctio
n (
%)
Figure 6.14: Comparison of the failure fraction of different “TriMOS” structures.
This result indicates that the plasma-induced damage could be reduced if the
interconnect lines are laid out like this way: one side of the line has narrow
spacing but the other side of the line has wide spacing as the antenna in “TriMOS”
structures or the dense-sparse interlaced antenna structure. Practically it might be
difficult to apply this trick for the global IC circuits, but it is quite useful locally
for specific transistors that are with quite high antenna ratios. By laying out the
interconnect lines like “TriMOS-L/M/R” structures or simply adding dummy lines
to the layout as in “TriMOS-floating” and “TriMOS-ground” structures, the risk
and extent of plasma charging damage will be dramatically reduced.
6.3.4 Mechanism
The electrons and ions have significant difference in incident angular
distributions [Hwa97]. Electrons are decelerated while ions get accelerated in the
thin positively charged sheath, resulting in broad electron and narrow ion angular
distributions. This difference implies that most of the ions impinge onto a wafer
surface perpendicularly while most of the electrons arrive with oblique incident
angles. A representative distribution is illustrated in polar format in Figure 6.15
[Gia98].
Chapter 6
90
Figure 6.15: Schematic depiction of the electron and ion angular distribution functions at the sheath edge and at the wafer surface.
As a result of geometric and electrical shading, ions are so directional that none
will hit the sidewalls on their way to the bottom. Electrons are so isotropic that
most will hit the sidewalls and will stick there.
The imbalance between ions and electrons determines the amount of plasma-
induced damage. How well they balance is related to the pattern of the antenna
fingers (dense or sparse) and the phase of etching (during etching or over etching).
The schematic view of dense antenna, sparse antenna, and “TriMOS-L/M/R”
antenna structures during etching and during over etching are illustrated in Figure
6.16 and Figure 6.17 respectively. Since the antenna sketch of dense-sparse
interlaced antenna structures, “TriMOS-floating” and “TriMOs-ground” structures
are quite similar to the “TriMOS-L/M/R” structures, the interpretation for the
reason that they failed less are same as that for the “TriMOS-L/M/R” structures, as
illustrated in Figure 6.16 (b) and Figure 6.17 (b). �
positive charging
---- - - - - - -
---- - - - - - -
---- - - - - - -
---- - - - - - -
----- -- -- -
---- - - - - - -
++ ++ ++ ++ ++ Antenna
gate
- -
+�
-+�+�
-
+�
+�+�
+�
+�
--
-
-
- +�+�+�
--
- -
-+�
+� +�--
+�+�
-�
+�
+�+�
+�
+�
---
-
- +�+�
+�-
-
- -
-+�
+�+
---
-
-
-
-+�
+�
+�
+�+�
+�
+� +�
+�
+�--
--
--
-+�
+�
+�+�
+�
+�
+�
- -
-
- -
-
plasma
(a). dense antenna structure
photoresist
- --+�+�
-
+
+�+�
+�
+�
--
-
-
- +�+�+�
--
- -
-+�
+� +�--
+�+�
-
+�
+�+�
+�
+�
---
-
- +�+�
+�-
-�
- -
-+�
+�+�
---
-
-
-
-+�
+�
+�
+�+�
+�
+� +�
+�--
--
--
-+�
+�
+�+�
+�
+�
+�
- -�
-
- -
-
plasma
(c). sparse antenna structure
+� +�
Antenna ++ ++ ++ ++
gate
- - - -
----- -- -- --
---
----
---- - - - - - - -
- - -
- - - -
---- - - - - - - -
- - -
- - - -
- -- - - - - -
almost no charging
photoresist
- --+�+�
-
+�
+�+�
+�
+�
--
-
-
- +�+�+�
--
- -
-+�
+� +�--
+�+�
-
+�
+�+�
+�
+�
---
-
- +�+�
+�-
-
- -
-+�
+�+�
---
-
-
-
-+�
+�
+�
+�+�
+�
+� +�
+�--
--
--
-+�
+�
+�+�
+�
+�
+�
- -
-
- -
-
plasma
gatealmost no charging
(b). “TriMOS” structure
+� +�
Antenna
almost no charging
++ ++
----- -- -- -
----- -- -- -
- -- -
- -- - -
---
----
++ ++ - - - -
----- -
----- -photoresist
TriMOS-L/R TriMOS-M
Figure 6.16: Schematic view of the structures during etching
Design strategy and protection scheme
91
�
(c). sparse antenna structure
Antenna
photoresist
-� -�-+�+�
-�
+�
+�+�
+�
+�
--
-�
-�
- +�+�+�
--
- -
-+�
+� +�-�-�
+�+�
-
+�
+�+�
+�
+�
--�-
-
-�+�+�
+�-�
-�
-� -�
-+�
+�+�
--�-
-
-
-
-�+�
+�
+�
+�+�
+�
+� +�
+�--
--
--
-+�
+�
+�+�
+�
+�
+�
-� -
-
- -�
-�
plasma
gate
+� +�
++
----- -- -- -
----
----
---- - - - - - - -
- - -
- - - -
---- - - - - - - -
- - -
- - - -
negative charging
almost no charging
---- - - - - - -
---- - - - - - -
---- - - - - - -
---- - - - - - -
----- -- -- -
---- - - - - - -
Antenna
gate
-� -
+�
-+�+�
-
+�
+�+�
+
+�
--
-
-�
- +�+�+�
--
- -�
-+�
+� +�-�-�
+�+�
-�
+�
+�+�
+�
+�
---
-
- +�+�
+�-�
-
- -
-+�
+�+�
--�-
-
-
-
-�+�
+�
+�
+�+�
+�
+� +�
+�
+�--�
-�-
--
-+�
+�
+�+�
+�
+�
+�
- -
-
- -�
-
plasma
(a). dense antenna structure
photoresist
-� -�-+�+�
-
+�
+�+�
+�
+�
--
-
-
- +�+�+�
--
- -�
-�+�
+� +�--�
+�+�
-�
+�
+�+�
+�
+�
---
-
- +�+�
+�-
-
- -
-+�
+�+�
-�--
-�
-
-
-�+�
+�
+�
+�+�
+�
+� +�
+�-�-�
-�-
--�
-+�
+�
+�+�
+�
+�
+�
- -
-�
- -
-
plasma
+� +�----- -- -- -
----- -- -- -
----- -- -- -
----- -- -- -
Antenna
gatea little negative charging
almost no charging
(b). “TriMOS” structure
--
---
--
---
photoresist
B1 A2 B2A1
TriMOS-L/R TriMOS-M
Figure 6.17: Schematic view of the structures during over etching
6.3.4.1 Dense antenna structure
During etching, the photoresist was negatively charged. The electrons are
repelled by the photoresist. The electrons moving in all directions can hardly enter
into that narrow trench. However, it is relatively easy for the ions to reach the
bottom. Hence the dense antenna collects positive charges during etching, as
shown in Figure 6.16 (a).
During over-etching the antenna does not collect positive charges anymore
since all conductive antenna material between the two fingers has disappeared.
Only the sidewall of the antenna is exposed to plasma. Because the fingers are so
close to each other, only few electrons reach the sidewall of the antenna. Hence,
the dense antenna collects no charges during over-etching, as shown in Figure 6.17
(a). The gate collects positive charges during etching and no charges during over-
etching.
6.3.4.2 Sparse antenna structure
During etching, because the fingers are far away from each other, the electrons
can reach the sidewall and the bottom of the trench. The vertically directed ions
only reach the bottom of the trench. Hence the sparse antenna collects more
negative charges than positive charges, as shown in Figure 6.16 (c).
During over-etching, since the conductive antenna material between the two
fingers has gone, the antenna does not collect positive charges anymore. Only the
sidewall of the antenna is exposed to plasma and catches electrons. Hence, during
over etching, the sparse antenna collects only negative charges as shown in Figure
6.17 (c). The gate collects negative charges both during etching and during over-
etching.
Chapter 6
92
6.3.4.3 The antenna of “TriMOS” structure
During etching, some sparse fingers collected negative charges and some dense
fingers collect positive. The antenna of the “TriMOS-M” and “TriMOS-L/R” are
still connected by the bottom thin metal layer. The collected ions and electrons
may partly balance each other. Hence, the “TriMOS-M” and “TriMOS-L/R” are
almost not charged, as shown in Figure 6.16 (b).
During over-etching, the bottom layer is clear. The antenna of “TriMOS-M”
and the antenna of “TriMOS-L/R” have been separated. The fingers of “TriMOS-
M” are in the same situation as the “standard alone” dense finger structure
mentioned above. It does not collect charges. Since the antenna of the “TriMOS-
M” collects very little charge both during etching and during over-etching, the
“TriMOS-M” suffers the smallest amount of plasma damage.
One side of the fingers of the “TriMOS-L/R” is in the same situation as dense
finger structure. The other side collects almost no charges during etching and no
charges for “TriMOS-M” but a little negative charges for the “TriMOS-L/R”
during over-etching in the same situation as sparse finger structure. On one side
the finger has narrow spacing, on the other side there is wide spacing. One side
collects no charges and the other side collects a few negative charges, as shown in
Figure 6.17 (b).
However note that only one side of the antenna of left/right MOS collects
negative charges, while both sides of the sparse antenna of the sparse antenna
structures collect negative charges. The sparse antenna structures suffer more
plasma damage than left/right MOS not only during the etching but also during the
over-etching. This fact explains why the “TriMOS-L/R” fails less than the
“standard alone” sparse antenna structures mentioned above. Hence, the “TriMOS-
L/R” is negatively charged.
6.3.5 Summary
Normal MOS antenna structures and special “TriMOS” structures with same
antenna ratio (AR = 10000) have been studied in this section. Compared to the
conventional dense and sparse antenna structures, the new dense-sparse antenna
structures, the “TriMOS-L/M/R” structures, the “TriMOS-floating” structures, and
the “TriMOS-ground” structures have much less failures. Since in those antenna
structures one side of the metal line has narrow spacing but the other side of the
line has wide spacing, both negative and positive charges are collected. These
charges balance each other. Therefore the plasma charging damage is reduced
Design strategy and protection scheme
93
The results indicate the plasma charging damage could be reduced in design
phase. In some specific area, the transistors are with quite high antenna ratios, by
laying out the interconnect lines like “TriMOS-L/M/R” structures and dense-
sparse structures or simply adding dummy lines to the layout as in “TriMOS-
floating” and “TriMOS-ground” structures, the risk and extent of plasma charging
damage will be dramatically reduced.
6.4 Conclusions
In this chapter, the strategy and protection scheme to reduce plasma charging
damage in design and layout phase is discussed. These practical solutions can be
generally implemented in different plasma system.
Base on our investigation of the temperature effect on the protection diode, we
report for the first time that the enhancement of the efficacy of diodes in protecting
very thin gate oxides is primarily due to the high ambient temperature during the
plasma processes. A strategic diode protection scheme for plasma charging
damage is proposed. The best protection scheme depends on the specific charging
polarity and temperature. For plasma deposition charging at high temperature, the
double-sided diode is recommended. Considering the fact that plasma deposition is
gaining importance, double-sided diodes are considered to be the best choice in
most cases.
Moreover, a novel first order self-balancing interconnect layout design is
proposed. If the layout of the interconnect lines is such that the spacing between
the interconnect lines is alternately wide and narrow, both negative and positive
charges are collected. Because these charges balance each other, the plasma
charging damage is reduced.
6.5 References
[Car00] J. P. Carrère, J. C. Oberlin, and M. Haond, “Topographical dependence of charging and new phenomenon during inductively coupled plasma (ICP) CVD process”, Proc. of 5th P2ID, p. 164, 2000.
[Che00] K. P. Cheung, “On the mechanism of plasma enhanced dielectric deposition charging damage”, Proc. of 5th P2ID, p. 161, 2000.
[Gia98] K. P. Giapis and G. S. Hwang, “Pattern-dependent charging and the role of electron tunneling”, Jap. J. Appl. Phys. , vol. 37, p. 2281, 1998.
[Has94] K. Hashimoto, “Charge damage caused by electron shading effect”, Jpn. J. Appl. Phys., vol 33, p. 6013, 1994.
Chapter 6
94
[Has98] A. Hasegawa, F. Shimpuku, M. Aoyama, K. Hashimoto and M. Nakamura, “Direction of topography dependent damage current during plasma etching”, Proc. 3rd P2ID, p. 168, 1998.
[Hwa97] G. S. Hwang and K. P. Giapis, “On the origin of the notching effect during etching in uniform high density Plasmas”, J. Vac. Sci. Technol. B 15(1), p. 70, 1997.
[Kri98] S. Krishnan, A. Amerasekera, S. Rangan and S. Aur, “Antenna device reliability for ULSI processing”, Int. Electron Device Meeting (IEDM) Technical Digest, p. 247, 1998.
[Par99] D. Park and C. Hu, “The prospect of process-induced charging damage in future thin gate oxides”, Microelectronics Reliability, p. 567, 1999.
[Sca01] A. Scarpa, L. van Marwijk, W. Peters, D. Boter and F.G. Kuper, “Yield and reliability effects of interlevel dielectric plasma enhanced deposition induced charging damage”, Proc. of 6th P2ID, p. 44, 2001.
[Shi93] H. Shin, Z. Ma and C. Hu, “Impact of plasma charging damage and diode protection on scaled thin oxide”, Int. electron devices meeting technical digest, p467, 1993.
[Shi96] H. Shin and C. Hu, “Thin gate oxide damage due to plasma processing”, Semicond. Sci. Technol., p. 463, 1996.
[Sho89] F. Shone, K. Wu, J. Shaw, E. Hokelet, S. Mittal and A. Haranahalli, “Gate oxide charging and its elimination for metal antenna capacitor and transistor in VLSI CMOS double layer metal technology”, Sym. VLSI Tech. Dig. Papers, p. 73, 1989.
[Sno89] C. M. Snowden, “Semiconductor device modeling”, New York: Springer-Verlag, 1989.
Chapter 7 Plasma Charging Damage of Floating Metal-Insulator-Metal Capacitors
In this chapter, the mechanism of plasma charging damage of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed. A range of test structures with different antennas have been used to investigate the mechanism of plasma charging damage of MIM capacitors. Based on the experimental results, a model is presented This model describes the relation between the damage and the area ratio of the antennas connected to the two plates of MIM capacitors. Design rules are proposed in order to prevent plasma charging damage. Furthermore, layout solutions to reduce plasma charging damage are suggested.
Chapter 7
96
7.1 Introduction
High performance mixed signal and RF circuits built in CMOS or BiCMOS
require integrated capacitors with high voltage independency, high quality factor,
good capacitor matching, precision control of capacitor values and low parasitic
capacitance along with high reliability and a low defect density. Conventional
high-density capacitors such as poly-substrate [Mcc81], poly-poly [Tay92] and
metal-poly [Kay88, Yin98] structures suffer from low voltage independency due to
voltage induced depletion effects as well as a large parasitic capacitance due to
their proximity to the substrate.
The metal-insulator-metal (MIM) capacitors used for this study have low
parasitic capacitance, especially when fabricated on metal 2 or higher, as well as a
high quality factor (Q) for RF circuit applications [Ste97]. In the work presented
here, high density MIM capacitors with capacitance densities of 1.0 to 2.0 fF/µm2
and silicon nitride dielectrics deposited by plasma-enhanced chemical vapour
deposition (PECVD), have been integrated into the back-end metallization layers
of a CMOS and a BiCMOS process flow. The capacitor breakdown voltage,
linearity and reliability meet mixed-signal circuit requirements. A defect density
less than 0.5 defects/cm2 has been achieved for the test structures with 2.0 fF/µm2
specific capacitance. A quality factor Q > 10 at frequencies of 1 and 2 GHz was
measured indicating its usefulness for RF applications [Dec00].
The dielectric in MIM capacitors is much thicker than the MOS gate oxide-
thickness and the antenna ratio [AR(T/D)] defined as the area ratio of top antenna
versus the dielectric area is typically low and even near unity. Because of the small
antenna ratios, one does not expect these capacitors to suffer from plasma charging
damage as rapidly as with thin gate oxides. However, previous studies found
thicker oxides to be very sensitive to plasma charging damage. It was argued that
thicker oxides require a higher voltage but less current to break down [Fan94].
Harris stated that MIM capacitors could be damaged only when the bottom plate is
grounded and the top plate is connected to a large conductor (antenna) that is
exposed to a plasma [Har98].
In this chapter however, we will demonstrate that floating MIM capacitors,
without any substrate contact are also very sensitive to plasma charging damage.
The interconnect lines connected to the top plate is referred to as top antenna, and
the interconnect lines connected to bottom plate is referred to as bottom antenna in
this chapter. The AR(T/B), area ratio of top antenna versus bottom antenna, is a more
critical parameter for floating MIM capacitor than AR(T/D), which is commonly
Plasma charging damage of floating Metal-Insulator-Metal capacitors
97
used in studying plasma charging damage in the gate oxide of MOS transistors.
Severe plasma charging damage occurs if the interconnect lines connected to the
two MIM capacitor plates have a large difference in area, though the AR(T/D) is low
and even near unity. The damage becomes larger with the increase of AR(T/B),
independent of which plate is connected to the largest antenna. The mechanism
and the protection schemes of plasma charging damage of floating MIM capacitors
are discussed in this chapter. Additional design rules are proposed, in order to
predict and automatically flag the possible charge-damage. Furthermore, layout
solutions to reduce the damage are suggested as well.
7.2 Experimental
7.2.1 MIM capacitor processing
The MIM capacitor is formed using a metal 1 layer as bottom plate, 20 to 60
nm silicon nitride as insulator and an additional thin metal 1.5 layer as top plate.
The top plate is connected to metal 2 by vias. Figure 7.1 and Figure 7.2 show a
schematic and a SEM cross-section of the MIM capacitor built on metal 1. A short
description of the process flow follows. First the bottom plate is formed by a
standard metal 1 deposition of a Ti/TiN-AlCu-TiN stack. The thin silicon nitride
film is deposited by PECVD followed by the deposition of the top metal plate (30
nm TiN , 200 nm AlCu , 30 nm TiN). Then, the top plate layer is patterned and
etched with a selective etch chemistry with etch stop on the insulator film.
Subsequently, the insulator film together with the bottom plate are patterned and
etched in sequence. The process flow continues with the standard CMOS back-end
flow sequence of inter-metal dielectric (IMD) deposition, via 1 formation, and
metal 2 patterning; followed by IMD deposition on metal 2, via 2 formation, and
metal 3 patterning; finally finished with passivation. The IMD depositions consist
of an SiO2 layer deposited by a medium density PECVD tool at 4000C. In order to
improve the particle performance of the process, a plasma power ramp down
(PPRD) step is added at the end of deposition process. This step prevents the
deposition on the chamber walls releasing and affecting the wafer surface.
The MIM capacitor is implemented using the above scheme in a CMOS back-
end flow with 1.1 µm metal pitch design rules [Ack01c].
Chapter 7
98
Intermetal
Dielectric
Metal 2
Si3N4
Metal 1
Metal 1.5
Via 1
Top antenna Bottom antenna
Figure 7.1: Schematic diagram of MIM capacitor integrated on metal 1 of a backend CMOS.
top plateSi3N4
Via 1
Metal 2
Metal 1 bottom plate
1 µ m
Figure 7.2: Cross-section SEM picture across a typical MIM capacitor. Note that the shallow via 1 provides the connection between the top plate of the capacitor to metal 2. Connection of bottom plate (metal 1) to metal 2 is provided by a deep via 1 not depicted here.
7.2.2 Test structures
More than 400 systematically arranged test structures have been designed and
processed in order to investigate and characterize the effect of charging during
processing on the yield and reliability of the MIM capacitors. MIM capacitors
have been designed with an area of 5 × 5 µm2, 20 × 20 µm2 and 20 × 5 × 5 µm2 in
parallel. Antennas with different features are connected to top and bottom plate, in
order to simulate the interconnect layout design of MIM capacitors. The area of
the antennas is designed in a range from 20 µm2 up to 120000 µm2 or consists only
of a small connection pad (1.36 µm2) to the next metal level. To investigate
Plasma charging damage of floating Metal-Insulator-Metal capacitors
99
possible ways of protection of the MIM capacitor during the processing, various
test structures with protection devices have been implemented including the use of
diodes and metal bridges. To investigate the antenna perimeter effect, antennas
have been designed both as fingers and as plates.
7.2.3 Measurement
Affected capacitors show a hard breakdown. To detect affected capacitors
leakage currents of the test structures are measured at 3.7 V (Vdd+10%) on the top
plate with a grounded bottom plate. The failure criterion is that a leakage current is
larger than 1 µA (Ileak > 1 µA). Fresh capacitors, even the largest capacitors never
reach this value, while affected capacitors exceed this value by a few orders of
magnitude. The failure fraction is the fraction of failed test structures out of the
measured samples. The breakdown voltage of the MIM capacitor dielectric is also
investigated. The yield of the product has been measured as well. The
experimental vehicle used for this study is a BiCMOS chip with MIM capacitors.
The results of the yield test have been split up into the different failure
mechanisms of the chip. Wafer maps are provided for each wafer and failure
mechanism.
A PDM tool from Semiconductor Diagnostics Inc. is used to detect the process
step that causes the charging problem. PDM is a contactless and damage-free
measurement to determine the amount of charge built up in an oxide layer
[MSa00] 1000-nm thermal oxide layer is grown on blank test Si wafers. Before
and after the treatment of the test process step, the potential over the oxide layer
can be measured by PDM. The potential difference ( Vpdm) reflects the charging
contribution of this test process step.
7.3 Results and discussion
7.3.1 AR(T/D) and AR(T/B)
As previously mentioned, AR(T/D) is defined as the area ratio of top antenna
versus dielectric of the floating MIM capacitor, and AR(T/B) is the area ratio of top
antenna versus bottom antenna of the floating MIM capacitor.
( ) capacitorMIMfloatingtheofdielectricofarea
AntennaTopofareaAR DT =/ (7.1)
Chapter 7
100
( ) AntennaBottomofarea
AntennaTopofareaAR BT =/ (7.2)
AR(T/D) is commonly used in studying plasma charging damage in the gate oxide
of MOS transistors, and the plasma charging damage increases with AR(T/D)
[Wan01]. The results presented in Figure 7.3 however show that AR(T/B) is a more
critical parameter rather than AR(T/D) for floating MIM capacitor. In Figure 7.3, the
failure fraction of different capacitors with the same top antenna is compared. The
capacitor is different in size: one has an area of 5 × 5 µm2, the other has an area of
20 × 20 µm2. A top antenna area of 10720, 12400 or 17200 µm2 is used. The
bottom plate of all these floating MIM capacitors is connected to a 10000 µm2
plate. For the small capacitor, the value of AR(T/D) is 16 × higher compared to that
of the big capacitor. However, the failure fraction presented in Figure 7.3 indicates
that, the small capacitor with 16 times higher AR(T/D) fails even less than the big
capacitor. The two capacitors with the same AR(T/B) do not have the same failure
fraction. We believe that this can be explained with the role of the capacitor area
in the oxide breakdown mechanism. It is well known that, under identical stress
conditions, larger area capacitors fail more (or earlier) than small area capacitors
[Deg98]. In section 7.4, we present a damage model based on AR(T/B) rather than
AR(T/D), which confirms the important role of AR(T/B) in the study of plasma
charging damage of floating MIM capacitor.
0
2
4
6
10720 12400 17200
Top antenna area (µm2)
% fa
ilure
frac
tion
5x5micr.capacitor
20x20micr.capacitor
Figure 7.3: Failure fraction as a function of the top antenna area for two capacitor sizes. The bottom antenna is 10000 µm2 in all cases.
Plasma charging damage of floating Metal-Insulator-Metal capacitors
101
7.3.2 Impact of the antenna area
The dependence of AR(T/B) on the failure fraction of floating MIM capacitors is
shown in Figure 7.4. Both top antenna and bottom antenna are on the same metal
level and the capacitor is isolated from the substrate. When the top antenna and
bottom plate have the same size, the failure fraction falls back to almost zero. The
failure fraction increases with an increasing of AR(T/B). A potential difference
across the insulator between the two plates is generated proportional to the
difference in the size of the antennas. When AR(T/B) = 1 (top antenna and bottom
plate have the same size), there is no voltage potential difference and as a
consequence, there is no plasma charging damage. When AR(T/B) is large (top
antenna is much bigger than bottom antenna), a large voltage potential difference
is generated, which causes a high failure fraction.
The bottom plate of some test structures is not connected to an antenna but to
an extremely small pad, which is used for connecting to the up level. The effects of
this very small bottom antenna (1.36 µm2) versus a large bottom antenna (10000
µm2) for a range of top antenna sizes are compared in Figure 7.5. For the
extremely small bottom antenna, the failure fraction remains low and is
independent of the top antenna sizes.
0
5
10
15
20
25
0 5 10 15Ratio of top antenna vs. bottom antenna
(AR(T/B))
% f
ailu
re f
ract
ion Finger
antenna
Plateantenna
Figure 7.4: AR dependence on failure fraction for finger and plate antennas.
7.3.3 Impact of the antenna perimeter
As shown in Figure 7.5, the finger antenna structures failed more than plate
antenna structures. Plasma charging damage is more severe with a finger shaped
Chapter 7
102
antenna structures compared to a plate shaped antenna structures with the same
antenna area. This must be due to the electron shading (ES) effect [Has94].
Typically, electron shading is very severe during metal etching by plasma tools
[Ack00]. The electron shading effect during plasma deposition is also reported in
[Car00, Gab00].
0
2
4
6
8
10
12
14
1040 1400 2200 5000Top antenna area (µm2)
% fa
ilure
frac
tion
1.7x0.8 µm2 bottom antenna
100x100 µm2 bottom antenna
Figure 7.5: Effect on plasma charging damage of a very small antenna connected to one plate of the floating capacitor.
7.3.4 Source of the damage
As shown in Figure 7.6, more than 40 V are required to breakdown a 60 nm
thick dielectric of MIM capacitor. With a PDM tool, it was discovered that the
plasma power ramp down (PPRD) step in the end of the PECVD process for IMD
deposition generated well over 60 V lateral potential difference on the surface of
the oxide layer between the centre and the edge of the wafer, as observed in Figure
7.7. A reduced plasma power helps the reduction of particles. However, it is no
longer capable to support a plasma over the full wafer surface: only in the centre of
the wafer there is a small region of plasma remaining. This region is charged
highly negative as confirmed by the PDM measurement. A voltage of –56 V is
generated in the centre of the wafer. For the floating MIM capacitors in this highly
charged region, the large area ratio between top antenna and bottom antenna
causes a large potential difference across the capacitor dielectric, which causes
dielectric breakdown.
The yield mapping result agrees with the PDM result. Figure 7.8 illustrates
typical mapping of the dysfunctional dices, which fail because of high leakage
current. This failure mechanism is strongly related to the leaky MIM capacitors.
Plasma charging damage of floating Metal-Insulator-Metal capacitors
103
The dysfunctional dies are mainly located in the region of the centre of the wafer,
which coincides with the highly charged region detected by PDM tool. The yield
mapping confirms the relation between the charges caused by PPRD step and the
failing of MIM capacitors.
V bd (V)
Capacitor:
200*200um 2
50 60
Cum
ulat
ive
prob
abili
ty
0.01
0.05 0.10
0.20 0.30 0.40 0.50 0.60 0.70 0.80
0.90 0.95
0.99
32 30 34 36 38 40 42 44 46 48 50 52 54 56 58 60
Vbd (V)
Figure 7.6: Breakdown voltage of the dielectric MIM capacitor.
-56 V
Figure 7.7: PDM mapping of a 1000 nm oxide layer followed by the plasma power ramp down step.
Chapter 7
104
Figure 7.8: Typical yield mapping of a wafer processed with the high spin speed rinse process.
7.3.5 Effect of diode protection
-5
0
5
10
15
10400 14000 22000 50000
Top antenna area ( m2)
% fa
ilure
frac
tion
without diode protection
with diode protection
(µm2)
Figure 7.9: Effect on plasma charging damage of diodes connected to both plates of the floating MIM capacitor.
In Figure 7.9, the damage to diode protected and unprotected floating MIM
capacitors has been compared as a function of the top antenna area. For these test
structures, both capacitor plates are connected to n+/p diode by the same metal
level. None of the capacitors protected by diodes fail due to plasma charging
damage, no matter how large the antennas are. So by using protection diodes, the
charges collected on both plates can be discharged efficiently to the substrate
Plasma charging damage of floating Metal-Insulator-Metal capacitors
105
through the diodes, limiting potential build-up and preventing plasma charging
damage to the dielectric. Note that the diodes should be used carefully in order to
prevent impact on parasitic capacitance, voltage dependence and quality factors of
the MIM capacitors.
7.4 Damage model
In this section, the model of plasma charging damage of floating MIM capacitor
is built up. This model agrees with the measurement data of the structures with
normal size bottom antenna very well. However, the structure with extremely
small bottom antenna is exceptional to this model.
To build up the model to express the relation between the failure fraction of
MIM capacitor and AR(T/B), well-established dielectric breakdown statistics is used
[Deg98]. Through Equation (7.3), the yield loss (failure fraction) F is linked with
the charge (Q) through the oxide [Deg98].
=%63
exp1Q
QF (7.3)
where is the shape parameter or Weibull slope of the distribution and is a known
function of the oxide thickness tox, and Q63% is the charge flown through the oxide
inducing failure in 1–e–1 63% of the devices. The dependence of current (I) on
Q63% can be described by
10%63
KIKQ = (7.4)
where the parameters 0K and 1K depend on tox and can be defined from a
separate experiment.
The charge Q is
tIQ *= (7.5)
where t is the processing time. By substituting Equations (7.4) and (7.5) into
Equation (7.3), the following equation can be obtained
( )= +1
0
1exp1 KIK
tF . (7.6)
Chapter 7
106
It was reported before that the damage to MIM capacitor has a logarithmic
relation with the AR [Ack01a, Ack01b]. The driving force of the damage
mechanism is voltage. So now the antenna area dependence of the voltage can be
introduced
)ln(* )/( BTARCV = . (7.7)
In the low voltage region, nitride dielectric shows an Ohmic conduction mode
[Sca98]. Therefore the current through the floating MIM capacitor can be defined
as
R
ARC
R
VI BT )ln(
* )/(== . (7.8)
where AR(T/B) is the area ratio between the top antenna and bottom antenna of the
floating MIM capacitor, R is the resistance of the dielectric, and C is a constant.
By substituting Equation (7.8) to Equation (7.6), the relation between the failure
fraction F and (AR(T/B)) can be obtained
)]ln[ln(*)1()/ln()/ln()]1ln(ln[ )/(10 BTARKRCKtF +++= . (7.9)
Defining
)/ln()/ln( 0 RCKtD += (7.10)
and
)1( 1 += Kn . (7.11)
Equation (7.9) can be rewritten as
DARnF BT += )]ln[ln(*)]1ln(ln[ )/( . (7.12)
The measured failure fraction that has been presented in Figure 7.4 previously
is presented again in Figure 7.10 together with the simulated failure fraction
calculated from Equation (7.12). ln[-ln(1-F)] is selected as the vertical axis in
order to present the straight-line dependence of ln[ln(AR(T/B))]. Note that Figure
7.10 is not a Weibull plot. Figure 7.10 shows that this function fits the measured
data very well, with n equals to 1.03 for finger antennas and 1.04 for plate
antennas, and with D equals to 2.48 for finger antennas and 2.83 for plate
antennas. We expect that the constants n and D are defined by the antenna shape,
the quality of the dielectric, the area of the floating MIM capacitor and the
processing itself. Equation (7.12) allows anticipating the plasma charging damage
in the floating MIM capacitors connected to long interconnects, and can be used to
define design rules.
Plasma charging damage of floating Metal-Insulator-Metal capacitors
107
Note that in Chapter 4 we discussed the relation between failure fraction and
the AR of the MOSFET and derived Equation (4.22) by using the same oxide
breakdown statistic. Here, Equation (7.12) is quite similar to the Equation (4.22).
However, please note that the definition of AR(T/B) here is different. (AR(T/B)) is
defined as the area ratio between top antenna and bottom antenna of the floating
MIM capacitor, and the AR in Chapter 4 is the area ratio between antenna and the
gate oxide of the MOSFET. Furthermore, the substrate of MOSFET is silicon and
charging current through the gate oxide is FN tunnelling current. The current
dependence of the voltage is given by Equation [Sno67, Len68]
)*
exp()(** 2
g
ox
ox
gox V
tB
t
VAAI = (7.13)
*2
3
16 m
mqA
bh=
hq
mB b
3
24 2
3*
= (7.14)
where, Aox is the gate oxide area, q is the electron charge, h is the reduced
Planck constant, m is the electron rest mass, *m is the electron effective mass in
SiO2 ( mm *34.0* = ) and b is the energy barrier height at the Si/SiO2 interface
( b =3.1eV). Apparently, the current dependence of voltage is different from
Equation (7.8), which is used in the floating MIM capacitor case.
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
0.1 1 10 100
ln(AR(T /B))
ln[-
ln(1
-F)]
Finger antenna
Plate antennay=1.03ln[ln(AR(T /B))]-2.48
y=1.04ln[ln(AR(T /B))]-2.83
extremely small bottom antenna
normal size bottom antenna
Figure 7.10: Measured failure fraction as a function of the antenna area ratio and simulated failure fraction for normal size bottom antenna structures.
Chapter 7
108
There is an exception for the above model, when the bottom antenna is
extremely small. As shown in Figure 7.10, Equation (7.9) does not predict the
failure fraction which the bottom antenna is limited to a very small area (1.7 × 0.8
µm2) which is required to make the connection to a higher metal level. The failure
fraction of this extremely small bottom antenna is found to be almost zero even
when the other antenna is very large, indicating a different failure mechanism.
The possible explanation could be that, with a small antenna, only little charge
can be exchanged with the environment. As long as the leakage of the floating
MIM capacitor dielectric can support this charge transfer, the capacitor will not be
damaged. We have only results from devices with an extremely small bottom
antenna but we believe this extremely small antenna mechanism is also suitable for
a small top antenna. This would imply that when the top antenna is very small, we
expect that the floating MIM capacitors will not be damaged no matter how big the
bottom antenna is.
7.5 Layout solutions
In this section, several layout approaches will be discussed that lead to low
plasma damage in line with the model presented above.
7.5.1 Using metal bridges to limit interconnection line connected to one of the two plates of the floating MIM capacitor
Figure 7.5 shows that, for the small bottom antenna, the failure fraction remains
low and is independent of the top antenna size on the other plate. This
phenomenon is especially interesting because it opens the possibility for the
introduction of metal bridges as a way of protecting the floating MIM capacitor.
When the ratio of the two conductors connected to the plates of the floating MIM
capacitor becomes too large, one of the antennas can be disconnected from the
capacitor at the level of the antenna and reconnected again at a higher metal level
by means of very small metal area. As such most plasma charging damage during
the processing is avoided. Figure 7.11 shows a possible layout for the protection of
the floating MIM capacitors by the use of a metal bridge.
7.5.2 Using protection diodes to drain the charging from the dielectric of the floating MIM capacitor
Figure 7.12 shows a possible layout for the protection of the floating MIM
capacitors by the use of n+/p diodes. Both capacitor plates are connected to the
Plasma charging damage of floating Metal-Insulator-Metal capacitors
109
diodes by the same metal level. In this way, negative charges collected on both
plates can be discharged to the substrate. As such, plasma charging damage on the
floating MIM capacitor is reduced. The efficacy of the protection diodes has been
proven by the experimental results presented in Figure 7.9. Special care must be
taken that both capacitor plates are connected to the double-sided diodes by the
same metal level. In the case that only one plate is connected to the substrate by a
diode and the other plate is left floating, then all conductors connected to the
substrate can act as an antenna of the connected plate. In this case, the ratio
between the antenna areas on both plates can be very large. As such a high a
potential difference can be built up across the capacitor, leading to discharge
through the capacitor and possibly breakdown.
Metal 2
Metal 1
Metal 3 bridge
Metal 1.5MIM capacitor
Via 2
Via 1
Figure 7.11: Possible layout for the protection of the floating MIM capacitors by using metal bridges to limit the connect pad or lines of the bottom plate.
Metal 2
Metal 1
Diode Diode
Figure 7.12: Possible layout for the protection of the floating MIM capacitors by the use of diodes.
Chapter 7
110
7.5.3 Using first order self-balancing interconnect layout design
In principle, the first order self-balancing interconnect layout design addressed
in Chapter 6 is also suitable for the floating MIM capacitors. Since there is very
little electron shading (ES) effect observed in this study (Figure 7.4), the extent of
the benefit of this method will be low. The details about this method can be found
in Chapter 6.
7.6 Design rules
The results of the experiments can be summarized in the following simple
design rules.
• Keep the ratio between the areas of the antennas connected to both
plates of the floating MIM capacitor for each individual metal level
close to unity except for the case that the area of one of the antennas is
below a certain threshold value.
• Contacting only one of the floating MIM capacitor plates to the
substrate by a contact, a diode or even by a MOS gate has to be
avoided.
• The use of metal bridges or protective diodes as proposed in Figure
7.11 and Figure 7.12 can repair violations of these rules.
7.7 Conclusions
In this chapter, results from plasma damage experiments on MIM capacitors are
presented. The antenna effect is studied and modelled, and design solutions to
minimize plasma damage are proposed.
Plasma charging damage to floating MIM capacitors is related to the size and
shape of the antennas connected to both capacitor plates. The large area ratio of
the interconnects that are connected to the two plates of the capacitor, leads to a
potential difference across the insulator between the two plates. This unexpected
potential difference stresses the dielectric of the floating MIM capacitor and
causes the degradation of the device. Large capacitors are more vulnerable than
small capacitors for the same antenna area. Two damage mechanisms describe
very well the relation between the failure fraction and the area ratio of antennas
connected to the two plates of the floating MIM capacitor. For normal size
antennas, the failure fraction is increasing with an increasing difference in top
antenna and bottom antenna and falls to almost zero when the top antenna and
Plasma charging damage of floating Metal-Insulator-Metal capacitors
111
bottom antenna are identical. For a very small antenna on one plate, the failure
fraction remains low and is independent of the antenna size on the other plate.
Antenna design rules should be applied during the IC layout phase to prevent
the potential plasma charging damage during IC manufacturing. By using small
metal bridges and protective diodes, the plasma charging damage of the floating
MIM capacitors can be reduced. The ratio between the areas of the interconnects
connected to both plates of the floating MIM capacitor for each individual metal
level should be close to unity except for the case that the area of one of the
antennas is only a few square micrometers. Furthermore, it has to be avoided to
contact only one of the floating MIM capacitor plates at a given metal level to the
substrate by a contact, a diode or even by a MOS gate.
7.8 References
[Ack00] J. Ackaert, “Antenna test structures matrix description, application for optimization HDP oxide deposition, metal etch, Ar preclean and passivation processing in sub-half micron CMOS processing”, Proc. of 5th P2ID, p. 77, 2000.
[Ack01a] J. Ackaert, Z. Wang, E. Backer and P. Coppens, “Charging damage in floating metal-insulator-metal capacitors”, Proc. of 6th P2ID, p. 120, 2001.
[Ack01b] J. Ackaert, Z. Wang, E. Backer and P. Coppens, “Plasma damage in floating metal-insulator-metal capacitors”, Proc. of 8th Intern. Symp. on the Physical & Failure Analysis of Integrated Circuits (IPFA), p. 224, 2001.
[Ack01c] J. Ackaert, Z. Wang, E. Backer, P. Colson and P. Coppens, “Non contact surface potential measurements for charging reduction during manufacturing of metal-insulator-metal capacitors”, Microelectronics Reliability, vol. 41, p.1403, 2001.
[Car00] J. P. Carrère, J. C. Oberlin, and M. Haond, “Topographical dependence of charging and new phenomenon during inductively coupled plasma (ICP) CVD process”, Proc. of 5thP2ID, p. 164, 2000.
[Dec00] S. Decoutere, F. Vleugels, R. Kuhn, R. Loo, M. Caymax, S. Jenei, J. Croon, S. Van Huylenbroeck, M. Da Rold, E. Rosseel, P. Chevalier and P. Coppens, “ A 0.35µm SiGe BiCMOS process featuring a 80 GHz Fmax HBT and integrated High-Q RF passive components”, Proc. of BCTM, p. 106, 2000.
[Deg98] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E. Maes, “New insights in the relation between electron trap generation and the statistical properties of oxide breakdown”, IEEE Trans. Electron Dev.,vol.45, no.4, p. 904. 1998
[Fan94] S. Fang and J. P. McVittie, “Oxide damage from charging: breakdown mechanism and oxide quality”, IEEE Trans. Electron Dev. Vol. 41, no. 6, p. 1034, 1994.
[Gab00] C. T. Gabriel and R. Y. Kim, “Transient fuse structures: the role of metal Etching versus dielectric deposition”, Proc. of 5th P2ID, p. 168, 2000.
Chapter 7
112
[Har98] E. B. Harris, “Charging damage in Metal-Oxide-Metal capacitors”, Proc. of 3rd P2ID, p. 15, 1998.
[Has94] K. Hashimoto, “Charge damage caused by electron shading effect”, Jpn. J. Appl. Phys., vol 33, p. 6013, 1994.
[Kay88] C. Kaya, H. Tigelaar, J. Paterson, M. de Wit, J. Fattaruso, S. Kiriakai, K. S. Tan and F. Tsay, "Polycide /metal capacitors for high precision A/D converters," Int. Electron Device Meeting (IEDM) Technical Digest, p. 782, 1988.
[Len68] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2”, J. Appl. Phys., vol. 40, p. 278, 1968.
[Mcc81] J. L. McCreary, "Matching properties and voltage and temperature dependence of MOS capacitors", IEEE Journal of Solid-State Circuits, vol. sc-16, p. 608, December 1981.
[MSa00] H. M’Saad, S. Desai, D. Witty, C. Hamon, S. Cho and F. Moghadam, “Plasma-induced defect generation on silicon surfaces in HDP-CVD processing”, Proc. of 5th P2ID, p.42, 2000.
[Sca98] J. Scarpulla, E. D. Ahlers, D. C. Eng, D. L. Leung, S. R. Olson and C.S. Wu. “Dielectric breakdown, defects and reliability in SiN MIMCAPs”, Proc. of GaAs Reliability Workshop, p. 92, 1998.
[Sno67] E. H. Snow, “Fowler-Nordheim tunneling in SiO2 films”, Solid State Comm., vol. 5, p. 813, 1967.
[Ste97] K. Stem, J. Koeis, G. Hueekel, E. Eld, T. Bartush, R. Groves, N. Greco, D. Harame and T. Tewksbury, “High reliability metal insulator metal capacitors for silicon germanium analog applications," Proc. of BCTM, p.191, 1997.
[Tay92] S. P. Tay and J. P. Ellui, "Thin gate and analog capacitor dielectrics for submicron device fabrication," J. Electronic Materials, vol. 21, no. 1, p.45, 1992.
[Wan01] Z. Wang, A. Scarpa, C. Salm and F. G. Kuper, “Relation between plasma-process induced oxide failure fraction and antenna ratio”, Proc. of 6th P2ID, pp. 16, 2001.
[Yin98] A. Yin, J. White, A. Karroy and C. Hu, "Integration of polycide/metal capacitors in advanced device fabrication," Proc. of 5th ICSICT, pp. 131, 1998.
Chapter 8 Concluding Remarks
An overview of the content of this thesis is given in this chapter. The suggestions and recommendations on detection of and protection against plasma charging damage are particularly summarized, since they are the ultimate objective of this work. Finally, the original contributions of this thesis are addressed.
Chapter 8 114
8.1 Concluding remarks
In this thesis, the ways to detect and reduce plasma charging damage in the
context of back-end-of-line (BEOL) processes have been studied. First a general
introduction of the inevitable role of plasma processes as well as the
characterization of plasma charging damage in the semiconductor industry is
given. The mechanisms of plasma charging damage are briefly explained. The
commonly used test structures and experimental techniques for plasma charging
damage evaluation are described. Subsequently, the effect of antenna ratio (AR) on
plasma charging damage is studied. A semi-empirical and physical model has been
developed, which describes the quantitative relation between plasma process-
induced oxide failure fraction and AR. The effects of plasma processing on the loss
of MOS reliability are demonstrated. Finally the strategies to cope with plasma
charging damage are given, for MOS transistor and floating MIM capacitors as
well.
The suggestions and recommendations on detection of and protection against
plasma charging damage are particularly summarized in the following sections,
since they are the ultimate objectives of this work.
8.1.1 Detection of plasma charging damage
In the most studies of plasma charging damage by so far, the general test
structures are based on elementary devices like MOSFETs, capacitors or memory
cells. Normally, a series of test structures with different antenna size, different
inter-finger space, and different level are designed in order to get a full picture of
the plasma damage during all the plasma processes. It proves the plasma charging
as the root cause of damage if the device degrades as the increase of antenna size.
The plate antenna structure and finger antenna structure help to define the
mechanism of the plasma damage, either plasma non-uniformity or electron
shading effect. The antenna structures with T-fuse (Figure 3.3) are used to
distinguish the damage from different plasma etching phases (main etching phase
versus over-etching phase). The antenna structures with different diodes (p+/n
diode, n+/p diode) help to detect the charging polarity. For all the antenna
structures, the connections to the bond-pads should be bridged. This means that the
connections to the bond-pad should be made via the last metal level, as shown in
Figure 3.2. Without bridging, the charging effect of the bond-pad could affect the
test structure and overwhelm the antenna effect.
Concluding remarks
115
After processing, the antenna structures are measured. Gate leakage (Ig,leak)
measurement is the most commonly used technique, because it is fast, simple and
useful. Sometimes a short and high stress could be used to reveal the latent
damage. An antenna test structure can be considered to fail when the Ig,leak
measured through its gate oxide exceeds a certain value. This value (normally
between 0.1 nA to 1 nA) is selected based on the fact that the devices with Ig,leak
above this value, diverge from the intrinsic slope of the leakage current
distribution, indicating extrinsic damage induced by plasma charging.
A plasma system can be diagnosed by a Langmuir probe. It is commercially
available and is widely used by plasma processing equipment vendors as well as
process-development engineers. The Langmuir probe can in principle measure the
electron temperature (Te), electron density (ne), positive ion density (ni), plasma
potential (Vp) as well as the floating potential (Vf). It can measure all of these
quantities as a function of position and therefore map the distribution directly.
Another commercial available tool is plasma damage monitor (PDM, by
Semiconductor Diagnostics Inc.). It is a contactless and damage-free measurement
to determine the amount of charge built up in an oxide layer by plasma. 100 nm
thermal oxide layer is grown on blank test Si wafers. Before and after the
treatment of the test process step, the potential over the oxide layer can be
measured by PDM. The potential difference ( Vpdm) reflects the charging
contribution of this test process step. This PDM tool has been used to detect the
process step that causes the charging problem in Chapter 7.
8.1.2 Protection against plasma charging damage
8.1.2.1 Fixing the damaging process
When the plasma process is suspected to be the source of yield loss or
reliability reduction, the first and the most difficult step is to identify which
specific plasma process step causes the problem. In state of the art silicon IC
manufacturing process, plasma is used in more than 20 different critical steps. By
using the matrix of antenna structures and by running different splits, one could
identify a certain plasma process step as the main source of charging damage
though it is not easy.
The method of fixing a damaging plasma process is highly process specific and
cannot be generalized. For example, pressure has a dramatic effect on the level of
charging damage during plasma enhanced dielectric deposition [Cot95]. The
Chapter 8 116
solution for the charging damage in a TCP metal etcher was to use a larger
discharge coil and a bigger gap between the top electrode and the wafer. The fix
for the charging damage in an ashing chamber was to introduce a trace amount of
moisture. Tricks like these come from trial and error types of trouble-shooting.
There is no systematic way of fixing plasma charging damage because most
plasma systems have their own specific properties. Common practice is to modify
the processing parameters within the constrains of the equipment and the process
requirements.
8.1.2.2 Use of design rules
The antenna design rule is commonly used for sub-micron IC technology in
semiconductor industry. It limits the maximum allowed antenna ratio in the IC
design and therefore limits the impact of plasma charging damage on the yield and
reliability of products. Luchies et. al. showed that smaller and fewer antennas can
improve the yield in the presence of charging damage [Luc98]. The design rules
used in the industry depends on the company and technology. It ranges from zero
to infinity. Zero means that every floating node in the circuit is tied down by
protection diodes. Infinity means that no rule is established. In practice, the most
common design rules fall between 100:1 to 1000:1.
8.1.2.3 Diode protection
Currently, computer-aided-design (CAD) tools cannot automatically layout the
circuit with the antenna rule as one of the constraints. Antenna rule violation
checking is done as a separate step after the layout is completed. When an antenna
rule violation is found, the common method of handling the problem is to insert a
minimum size diode if space is available.
The best diode protection scheme depends on the specific charging polarity and
temperature. For plasma deposition charging at high temperature, the double-sided
diode proposed in our study is recommended. Though the photo-induced leakage
current of the protection diode is reduced because of continuously increased
integration density and use of tiling metal lines in nowadays VLSI technology, the
leakage current of the diode is still sufficient to shunt the charging current from
plasma due to the high environment temperature during the plasma process. During
the plasma etching the wafers can be heated to about 70 °C and during the plasma
depositions processes, the ambient temperate is even 400 °C. Considering the fact
that plasma deposition is gaining importance, the use of double-sided diode is
considered to be the best choice in most cases.
Concluding remarks
117
However, diodes do represent additional circuit elements that need to be
included in the circuit model. The additional load may degrade the circuit
performance. The best strategy to identify and eliminate or at least minimize
plasma charging damage is to fix process tools or parameters first. And then use
design rules to limit the impact of the residual charging damage. When no other
solutions are appropriate, then the use of protection diodes is recommended.
8.1.2.4 Novel first order self-balancing interconnect layout design
In our study, a novel first order self-balancing interconnect layout design is
proposed. If the layout of the interconnect lines is such that the spacing between
the interconnect lines is alternately wide and narrow, both negative and positive
charges are collected. Because these charges balance each other, the plasma
charging damage is reduced. This trick might be difficult to apply to global IC
circuits, but it is quite useful for specific transistors that are attached to very long
interconnect lines. Simply, dummy lines could be added to the layout around the
interconnect lines to form this self-balancing layout. Unlike the protection diode,
the adding of these dummy lines will not influence the performance of the circuit.
8.2 Original contributions of this thesis
The following original contributions have been proposed in this thesis:
• It is demonstrated in this thesis that the value of the gate leakage
current is not only a failure indicator in the region about 1 nA but also a
good indicator of the reliability of the devices in the region between 1
pA and 1 nA.
• Oxide breakdown measurement with a stepped voltage stress is proved
to be a better test technique to reveal latent as well as actual plasma
damage, for a wide range of gate oxide quality in a very fast way,
compared to constant voltage stress method.
• A semi-empirical and physical model has been developed, which
describes the quantitative relation between plasma process-induced
oxide failure fraction and AR. This model enables us to extrapolate the
yield loss data obtained on large AR test structures to the charging
currents and yield loss of smaller AR structures which occur more often
in real circuits. With this model, a designer is able to predict the plasma
charging induced yield loss of the circuit, if the AR distribution of the
Chapter 8 118
circuit is available. Therefore, AR design rules can be set more
accurately to a specific layout of the circuit based on this model.
• It is reported in this thesis that the enhancement of the efficacy of
diodes in protecting very thin gate oxides is primarily due to the high
ambient temperature during the plasma processes. A double-sided
diode with floating nwell is proposed. The strategic diode protection
scheme for plasma charging damage is proposed. The best protection
scheme depends on the specific charging polarity and temperature. For
plasma deposition charging at high temperature, the double-sided diode
is recommended. Considering the fact that plasma deposition is gaining
importance, double-sided diodes are considered to be the best choice in
most cases.
• A novel first order self-balancing interconnect layout design is
proposed. If the layout of the interconnect lines is such that the spacing
between the interconnect lines is alternately wide and narrow, both
negative and positive charges are collected. Because these charges
balance each other, the plasma charging damage is reduced.
• Design rules are given to protect floating MIM capacitors from plasma
charging damage. It is suggested in this thesis that the ratio between the
areas of the antennas connected to both plates of the floating MIM
capacitor for each individual metal level should be kept close to unity
except for the case that the area of one of the antennas is below a
certain threshold value. Contacting only one of the floating MIM
capacitor plates to the substrate by a contact, a diode or even by a MOS
gate has to be avoided. If there are still violations of these rules, metal
bridges or protective diodes are proposed to reduce the plasma charging
damage.
8.3 References
[Cot95] D. R. Cote, S. V. Nguyen, W. J. Cote, S. L. Pennington, A. K. Stamper, and D. V. Podlesnik., “Low temperature chemical vapor deposition processes and dielectrics for microelectronic circuit manufacturing at IBM”, IBM J. Res. Develop., 39 (4), p. 437, 1995.
[Luc98] J. M. Luchies, P. Simon, F. Kuper, and W. Maly, “Relation between product yield and plasma process induced damage”, Proc. of 3rd P2ID, p. 7, 1998.
Summary Plasmas are key for enabling technologies in modern ultra-large scale
integrated (ULSI) circuit manufacturing. Since the modern ULSI circuit consists of
107-108 transistors, the back-end-of-line (BEOL) metallization process with a
multi-level interconnection of these transistors is a major technological challenge.
These advanced multi-level interconnections can only be made by using high-
density plasma-enhanced deposition and etching techniques. However, a plasma is
also a very harsh environment to integrated circuit (IC) products. A plasma could
generate an unintended high electrical field which stresses and degrades the
underlying thin gate oxide layer of the metal-oxide-silicon (MOS) transistors and
non-volatile memories (NVM) as well as the insulator of MIM capacitors. MOS,
NVM and MIM capacitors are major elements which form IC’s. Therefore the
yield and reliability of these IC products are degraded by plasma charging damage.
How to detect, control and reduce plasma charging damage becomes a formidable
challenge in modern IC technology.
In this thesis, the ways to detect and reduce plasma charging damage in the
context of back-end-of-line (BEOL) processes have been studied. First a general
introduction of the inevitable role of plasma processes as well as the
characterization of plasma charging damage in the semiconductor industry is given
in Chapter 1. Two main mechanisms of plasma charging damage, plasma non-
uniformity and electron shading effect are briefly explained in Chapter 2.
In Chapter 3, different test structures and experimental techniques for plasma
charging damage evaluation are described. Besides the existing and traditional
measurement techniques, it is demonstrated in this thesis that the value of the gate
leakage current is not only a failure indicator in the region around 1 nA but also a
good indicator of the reliability of the devices in the region between 1 pA and 1
nA. Additionally, it is realized that the oxide breakdown measurement with a
stepped voltage stress is a better test technique to reveal latent as well as actual
plasma damage, for a wide range of gate oxide quality in a very fast way,
compared to constant voltage stress method.
Subsequently, the effect of the antenna ratio (AR) on plasma charging damage
is studied in Chapter 4. A semi-empirical and physical model has been developed,
which describes the quantitative relation between plasma process-induced oxide
failure fraction and the AR. This model enables us to extrapolate the yield loss data
obtained on large AR test structures to the charging currents and yield loss of
Summary 120
smaller AR structures which occur more often in real circuits. Therefore, the
plasma charging induced yield loss of the circuit is able to be predicted if the AR
distribution of the circuit is available. Our investigation is very helpful to set AR
design rule more accurately to a specific layout of the circuit.
In Chapter 5, the effect of plasma process-induced latent damage on the
reliability of the IC has been directly demonstrated by using both single-layer (SL)
and multi-layer (ML) or stacked antenna structure, without any impact of
additional defects generated by normal constant current stress (CCS) revealing
technique. Secondly, the reliability tests of hot carrier (HC) stress and oxide
breakdown demonstrate the relation of reliability of MOS transistors and the
antenna ratios.
The strategies to cope with plasma charging damage in design and layout phase
are discussed in Chapter 6. It is reported that the enhancement of the efficacy of
diodes in protecting very thin gate oxides is primarily due to the high ambient
temperature during the plasma processes. A double-sided diode with floating nwell
is proposed. Considering the fact that plasma deposition is gaining importance,
double-sided diodes are considered to be the best choice in most cases. Moreover,
a novel first order self-balancing interconnect layout design is proposed. If the
layout of the interconnect lines is such that the spacing between the interconnect
lines is alternately wide and narrow, both negative and positive charges are
collected. Because these charges balance each other, the plasma charging damage
is reduced.
In Chapter 7, the mechanism of plasma charging damage of metal-insulator-
metal (MIM) capacitors as well as possible protection schemes are discussed. It is
suggested that the ratio between the areas of the antennas connected to both plates
of the floating MIM capacitor for each individual metal level should be kept close
to unity except for the case that the area of one of the antennas is below a certain
threshold value. Contacting only one of the floating MIM capacitor plates to the
substrate by a contact, a diode or even by a MOS gate has to be avoided. If there
are still violations of these rules, metal bridges or protective diodes are proposed to
reduce the plasma charging damage.
Finally, the suggestions and recommendations on detection of and protection
against plasma charging damage are summarized in Chapter 8.
Samenvatting Plasma’s zijn essentieel voor het fabriceren van moderne geïntegreerde
schakelingen (IC). Omdat moderne circuits zeer grote hoeveelheden (107-108)
transistoren bevatten is het aan elkaar verbinden met metaalbanen, het zogenaamde
“back-end-of-line (BEOL) proces” met meerdere metaal niveaus een grote
uitdaging. Deze geavanceerde meerlaags metaalverbindingen kunnen alleen
gemaakt worden met behulp van plasmadeposities en plasma-etsstappen, waarbij
de plasma’s een hoge dichtheid hebben. Een plasma is echter ook een op zijn minst
onvriendelijke, zoniet vijandige omgeving voor geïntegreerde schakelingen. Door
het ontstaan van grote elektrische velden wordt de gate-isolator in de transistoren
(MOS) en de isolerende laag in niet-vluchtige geheugens (NVG) of metaal-
isolator-metaal (MIM) capaciteiten belast en kan deze degraderen of zelfs kapot
gaan. MOS, NVG and MIM capaciteiten zijn belangrijke bouwelementen van IC’s.
Zowel de procesopbrengst als de betrouwbaarheid van IC’s wordt aangetast door
plasmaschade. De mogelijkheden om plasmaschade te detecteren, te beheersen en
te verminderen zijn grote uitdagingen in moderne IC-fabricageprocessen.
In dit proefschrift worden manieren bestudeerd om plasma schade te meten en
te verminderen tijdens BEOL processen. In hoofdstuk 1 wordt een algemene
inleiding gegeven over de rol van plasmaprocessen en de manieren waarop
plasma’s worden gekarakteriseerd in een industriële omgeving. De twee
belangrijkste schademechanismes, te weten niet uniforme plasma’s en
schaduwwerking, worden kort uitgelegd in hoofdstuk 2.
Hoofdstuk 3 beschrijft experimentele technieken om plasmaschade te
evalueren. Naast de bekende veel gebruikte meetmethodes zal in dit hoofdstuk
worden aangetoond dat de waarde van de lekstroom door het gate-diëlektricum
niet alleen een goed criterium is rond de tot nu toe veelgebruikte waarde van 1nA,
maar ook toegepast kan worden in het gebied tussen 1pA en 1nA. Daarnaast wordt
aangetoond dat het gebruik van een getrapte-spanningstest een beter en sneller
resultaat geeft dan de veelgebuikte constante-spanningstests om zowel latente
schade als daadwerkelijke fouten aan te tonen.
Vervolgens word het effect van de antenneratio (AR) op plasmaschade
bestudeerd in hoofdstuk 4. Een semi-empirisch en fysisch model is ontwikkeld dat
de relatie tussen hoeveelheid falende gate-diëlektrica en de antenneratio beschrijft.
Dit model stelt ons in staat om het opbrengstverlies gemeten aan teststructuren met
grote AR’s te vertalen naar een voorspelling voor echte circuits, waarin een
Samenvatting 122
kleinere AR toegepast wordt. Een chipontwerper is met deze gegevens in staat om
het verlies in opbrengst van een circuit te voorspellen als de verdeling van AR’s
bekend is. Met behulp van deze kennis kunnen de ontwerpregels voor AR’s
nauwkeurig per circuitontwerp worden vastgesteld.
In hoofdstuk 5 wordt de latente schade door plasmaprocessen aangetoond door
het vergelijken van schade aan eenlaags en meerlaags teststructuren. Voorts wordt
door middel van hete-ladingsdrager testen en gate-oxide doorslag de relatie tussen
de betrouwbaarheid van MOS transistoren en de antenneratio aangetoond.
De mogelijke strategieën om plasma schade te reduceren tot een acceptabel
niveau, in de ontwerpfase van de chip, worden besproken in hoofdstuk 6. De
hogere efficiëntie van de protectiediodes bij hogere temperaturen, zoals tijdens de
meeste plasmaprocessen, wordt besproken. Een “dubbele diode” met een
zwevende nwell wordt voorgesteld als beste protectiemethode omdat
plasmaschade door de depositiestappen een steeds grotere rol gaat spelen.
Daarnaast wordt een nieuw bedradingsontwerp geïntroduceerd waarmee de diverse
schade mechanismen elkaar (deels) opheffen. Indien het ontwerp van de
metaalverbindingen afwisselend grote en kleien afstanden tussen de
metaalspoortjes bevat word zowel positieve als negatieve lading ingevangen.
In hoofdstuk 7 worden de plasmaschademechanismen die optreden in metaal-
isolator-metaal (MIM) capaciteiten besproken alsmede de mogelijke manieren om
het device te beschermen. De gesuggereerde oplossing is het kiezen van elk van de
AR’s zo klein mogelijk, tenzij een van beide AR’s onder een bepaalde
grenswaarde ligt. Het moet worden voorkomen dat slechts een van de platen van
de zwevende MIM capaciteit verbonden wordt met het substraat, zelfs niet via een
diode of de gate van een MOS transistor. Ook kunnen metaalbruggen of
beschermingsdiodes gebruikt worden om de plasmaschade te minimaliseren.
Tenslotte worden in hoofdstuk 8 de suggesties om plasmaschade te detecteren en
de beschermingmethoden tegen plasmaschade samengevat.
Abbreviations and Acronyms AR antenna ratio BEOL back-end-of-line CAD computer aided design CCS constant current stress CMOS complementary-metal-oxide-semiconductor CV capacitance-voltage CVD chemical vapor deposition EEPROM electrically-erasable-and-programmable-read-only-
memory EES extended electron shading ES electron shading HC hot carrier HDP high density plasma HFCV high frequency capacitance-voltage IC integrated circuit ICP inductive coupled plasma IMD inter-metal dielectric IV current-voltage ML multi-layer MIM metal-insulator-metal MOS metal-oxide-semiconductor MOSFET MOS field effect transistor NVM non-volatile memory PDM plasma damage monitor PECVD plasma-enhanced chemical vapour deposition PRPD plasma power ramp down QSCV quasi-static capacitance-voltage SEM scanning electron microscope SILC stress-induced leakage current SL single-layer STP slow trap profiles ULSI ultra-large scale integrated VLSI very large scale integrated
Abbreviations and acronyms 124
List of Publications Journal Papers
• Z. Wang, J. Ackaert, C. Salm, F. G. Kuper, M. Tack, E. Backer, P. Coppens, L. Deschepper, and B. Vlachakis, “Plasma Charging Damage of Floating Metal-Insulator-Metal (MIM) Capacitors”, IEEE transaction on electron devices (TED), vol. 51, No. 6, pp. 1017-1024, 2004.
• Z. Wang, J. Ackaert, C. Salm, F. G. Kuper, and E. Backer, “A Novel Interconnect Layout Design for Reducing Plasma-Process Induced Charging Damage in Modern CMOS Processes”, submitted to Solid- State Electronics, 2004.
• Z. Wang, J. Ackaert, C. Salm, F. G. Kuper, and E. Backer, “Plasma Charging Damage Reduction in IC Processing by A Self-balancing Interconnect Layout” Microelctronics Reliability, 2004.
• J. Ackaert, Z. Wang, E. De Backer, P. Colson, and P. Coppens “Non Contact Surface Potential Measurements for Charging Reduction During Manufacturing of Metal-Insulator-Metal Capacitor”, Microelctronics Reliability, vol. 41, pp.1403-1407, 2001.
Conference Papers • Z. Wang, J. Ackaert, C. Salm, F. G. Kuper, and E. Backer, “Plasma Charging
Damage Reduction in IC Processing by A Self-balancing Interconnect Layout”, 15th Europ. Symp. on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), 2004.
• Z. Wang, J. Ackaert, C. Salm, F. G. Kuper, K. Bessemans, and E. Backer, “Plasma Charging Damage Induced by a Power Ramp Down Step in the end of Plasma Enhanced Chemical Vapour Deposition (PECVD) Process”, Proc. of Semiconductor Advances for Future Electronics (SAFE), 2003.
• Z. Wang, J. Ackaert, C. Salm, E. Backer, G. van den Bosch, and W. Zawalsky, “Correlation between Gate Leakage Current Measurement and Reliability Measurement in Monitoring Plasma Process-Induced Damage on Gate Oxide”, proceeding of Inte.l Symp. on Physics and Failure Analysis (IPFA), p. 242, 2002.
• Z. Wang, A. Scarpa, S. Smits, C. Salm, and F. G. Kuper, “Temperature Effect on Antenna Protection Strategy for Plasma-Process Induced Charging Damage”, Proc. of Inter. Symp. on Plasma Process-Induced Damage (PPID), p. 134, 2002.
• J. Ackaert, Z. Wang, E. Backer and C. Salm, “Correlation between Hot Carrier Stress, Oxide Breakdown and Gate Leakage Current for Monitoring Plasma Processing Induced Damage on Gate Oxide”, Proc. of Inter. Symp. on Plasma Process-Induced Damage (PPID), p. 45. 2002.
• Z. Wang, A. Scarpa, S. Smits, C. Salm, and F. G. Kuper, “Temperature Effect on Protection Diode for Plasma-Process Induced Charging Damage”, Proc. Of Semiconductor Advances for Future Electronics (SAFE), p.127. 2002.
List of publications 126
• Z. Wang, A. Scarpa, C. Salm, and F. G. Kuper “Relation between Plasma Process-Induced Oxide Failure Fraction and Antenna Ratio”, Proc. of 6th Inter. Symp. on Plasma Process-Induced Damage (P2ID), pp. 16-19, 2001.
• J. Ackaert, Z. Wang, E. Backer and P. Coppens, “Charging Damage in Floating Metal-Insulator-Metal Capacitors”, Proc. of 6th Inter. Symp. on Plasma Process-Induced Damage (P2ID), pp. 120-123, 2001.
• J. Ackaert, Z. Wang, E. Backer and P. Coppens, “Plasma Damage in floating Metal-Insulator-Metal Capacitors”, 8th Inter. Symp. on the Physical & Failure Analysis of Integrated Circuits (IPFA), pp. 224-227, 2001.
• Z. Wang, J. Ackaert, C. Salm, and F. G. Kuper, “Plasma Process-Induced Latent Damage on Gate Oxide ---- Demonstrated by Single-layer and Multi-layer Antenna Structure”, 8th Inter. Symp. on the Physical & Failure Analysis of Integrated Circuits (IPFA), pp. 220-223, 2001.
• J. Ackaert, Z. Wang, E. De Backer, P. Colson, and P. Coppens, “Non Contact Surface Potential Measurements for Charging Reduction During Manufacturing of Metal-Insulator-Metal Capacitor”, 12th Europ. Symp. on Reliability of Electron Devices, Failure Physics and Analysis. (ESREF), pp. 1403, 2001.
• Z. Wang, J. Ackaert, C. Salm, and F. G. Kuper, “Charging Induced Damage on Complex-antenna Test Structures”, Proc. Of Semiconductor Advances for Future Electronics (SAFE), pp. 220-223, 2001.
• Z. Wang, C. Salm, F. G. Kuper and A. Scarpa, “Antenna Ratio Power Law Dependence of Plasma Process-Induced Oxide Failure Fraction”, Proc. Of Semiconductor Advances for Future Electronics (SAFE), p. 3. 2000.
• Z. Wang, P. G. Tanner, C. Salm, A. J. Mouthaan, F. G. Kuper, M. Andriesse, and E. van der Drift, “Plasma-Induced Charging Damage of Gate Oxides”, Proc. Of Semiconductor Advances for Future Electronics (SAFE), pp. 593-600, 1999.
Awards
• The Best Poster Award for the poster entitled “Temperature Effect on Protection Diode for Plasma-Process Induced Charging Damage”, Semiconductor Advances for Future Electronics (SAFE) conference, 2002.
• The Poster Award for the poster entitled “Oxides: why don't they isolate?”, MESA+ yearly workshop, 2001.
Awards 128
Acknowledgements Five and half years ago I flew alone a long way with my luggage from
Singapore to Holland, a country I never thought I would come to live in before. I
remember that it was a sunny day, but soon I realized it was in fact not typical
Dutch weather that day. I was quite curious and kept looking out of the window
when I took the train to Enschede. I saw ‘Enschede’ on the board at almost all the
train stations we passed by. I wondered whether I should get out and change trains
and therefore asked a boy who sat next to me. Luckily, he was a student of
University of Twente, the university I came to pursue my Ph. D degree. The boy
was friendly and hospital as most of Dutch people I met later. With his help, I
found my flat in University of Twente that Marie-Christine booked for me
successfully. I started to live here with a perfect day! I met a lot of nice people
during last years. Without their encouragement, assistance, support, and
understanding, this thesis would not have been possible. I would like to take this
opportunity to express my sincere acknowledgements.
First, I would like to thank my promoter Fred Kuper for supervising my work
and for guiding me in my research. Your constant encouragements helped me to
overcome a lot of difficulties. With your help, I had the opportunity to do my
internship in Philips in the beginning of my project. It helped me a lot to select the
direction of my research. I appreciate very much the freedom that you gave to me
in research.
I am deeply grateful to my daily supervisor Cora Salm for the fruitful
discussion, continues support and considerate concern. Thanks for your early
feedback and detailed corrections in reviewing my papers and the manuscript of
this thesis. I feel so lucky to be one of your students. You helped me in any way
that you could.
I am grateful to all members and ex-members of the SC group during my stay in
the group. I would like to thank Jurriaan Schmitz for your great knowledge of
science. With your suggestions, the typography of symbols, equations and numbers
in this thesis is improved. I would like to thank Ton Mouthaan, who first contacted
me and offer me the opportunity to pursue my Ph.D. in Holland. I also would like
to thank Hans Wallinga and his wife for their kindness and concern, and Pierre
Woerlee for your kindness. My special gratitude goes to my office mates and also
my ‘paranimfen’, Jay and André. Thanks for creating a most wonderful working
environment with me and sharing a lot of information with me. I enjoyed a lot of
Acknowledgements 130
interesting discussions we have made including IC technology, culture difference,
cars, child-care, computers, food, politics, etc. Cor, Egbert and Frederik, thanks for
your high quality maintenance of the PC network and HP network. Henk and
Marcel, thanks for your assistance in testing room. Ton, Tom, and Arthur, thanks
for making the samples for me in our clean room. I would like to also thank
Annemiek Janssen, Miranda van Wijk, Marie-Christine Prédéry, Margie Rhemrev,
and the financial administrators Sophie Kreulen and Joke Vollenbroek for their
excellent administrative assistants. Nataša, Svetlana, Hieu, Gratiela, Sheela, and
Andreea, thanks for your friendship. Thanks, Alexey, Radko and Phuong, for good
collaboration in RIM course. Thanks, Jisk, for discussing with me the diode
current. Sander, thank you for your input on the simulation of the diode current.
Thanks, Guido and Eric, for sharing the fun with me during the group ‘uitje”.
I would like to thank Philip Tanner from Griffith University, Australia. Thanks
for helping me a lot with the STP software and measurements. Also I would like to
thank Misha Andriesse and Emile van der Drift for doing several plasma exposures
measurements for us.
This Ph.D. work was co-operated with AMI Semiconductors. I owe my
appreciation to Marnix Tack, Eddy De Backer, Peter Coppens, Luc Deschepper
and Basil Vlachakis. Specially, I am greatly indebted to Jan Ackaert for his
tremendous contribution to this thesis, for his support and encouragement, and for
his friendship.
This Ph.D. work was also co-operated with Philips Semiconductors. I owe
many thanks to the process reliability group in MOS34. My special gratitude goes
to Andrea Scarpa for his enormous support and fruitful discussion. I would like to
thank my many other colleagues in BL LPG, MOS2, and QAS in Philips
Semiconductors Nijmegen, who give me support and encourage me to finish the
thesis.
I owe my great appreciation to my Chinese friends in the Netherlands. I
treasure very much our friendship and a lot of nice moments you shared with me.
Thank you all for having made my life in Holland much easier and more
enjoyable.
I am indefinitely indebted to my husband, Liquan Fang. Thanks for your love,
care, and understanding in all the years. You encouraged and supported me in
every possible way to accomplish this Ph.D. thesis. Dear, thank you very much for
all the things you have done for me. I am greatly indebted to my lovely son and
daughter, Daniel and Michelle. You bring me so many joys and happiness, which
made me continue writing this thesis in a good mood.
Acknowledgements
131
I could not list the names of all the people who have directly or indirectly
helped me to complete this thesis, but they are always in my heart. Thank you all!
Zhichun Wang