Designing with programmable logic

Designing with programmable logicM.J.P. Bolton. B.Sc.(Eng.), A.C.G.I.. D.Phil., Mem.I.E.E.E.

Indexing terms: Computer aided design, Integrated circuits

Abstract: The structure of programmable logic devices of the PLA type is described and the various devicearchitectures currently available are reviewed. Following a discussion of their evolution, the design techniquesnecessary for their effective application are presented. Recent developments in computer-aided design anddevice testing specifically for programmable logic are surveyed. Finally, some comparisons are made with otherforms of semicustom circuit.

1 Introduction

Probably the most widely used type of semicustom com-ponent is programmable logic. Although these componentshave been available for a long time, recent developments indevice architecture and computer-aided design (CAD) haveincreased their attractiveness to digital designers.

Programmable logic devices (PLDs) are standard com-ponents whose ultimate function is determined by thedigital designer; they leave the manufacturer in anunprogrammed state. Programming is performed either byloading internal storage registers, or by inducing per-manent or reversible physical changes in selected parts ofthe circuit. In the former case, the device's program can bemodified dynamically, whereas in the latter, this is not gen-erally possible.

A wide spectrum of digital logic elements could becalled 'programmable' according to the above definition.However, the class of devices to be considered here is amore restricted one. A more specific term would be 'arraylogic', one which has been widely used, but is now unfor-tunately confused with terms such as 'logic array', a differ-ent type of component. The justification for the use in thisreview of the term 'programmable logic' is current indus-trial usage.

The programmable logic circuits to be discussed are allspecialisations of the bussed cellular array. Examples ofcomponents based on this pattern are the diode matrix,read-only and read/write memory (ROM and RAM),content-addressable memory, and the programmable logicarray (PLA) together with its derivatives. Circuits of thistype are, of course, used as components of larger inte-grated circuits; here the concern is only with entire inte-grated circuits based on this structure.

The aims of this review are, first, to provide an overviewof the programmable logic family and the areas of use, andsecondly to discuss design techniques for its efficient appli-cation. Only currently or soon to be available componentsare mentioned. Finally, some comparisons are made withother semicustom technologies and some developmenttrends are identified.

2 Circuit structures and evolution

2.1 Bussed cellular arraysThe bussed cellular array is introduced as a unifying struc-ture for the PLDs discussed in later Sections. Most of thedevices were probably not conceived in this way, butnevertheless they can all be shown to be special cases ofthis general form. The model is due to Heutink [1], but isgeneralised here to include wired-OR buses.

Paper 371OE (C2), first received 1st October and in revised form 14th December1984

Dr. Bolton is with the Department of Electrical and Electronic Engineering, Uni-versity of Bristol, Queen's Buildings, University Walk, Bristol BS8 1TR, England

The structure of a bussed cellular array is shown inFig. 1A. A bussed cellular array is a cellular array in which

i i i

Fig. 1A Bused cellular array

all cells in a row or column are connected in parallel to thesame conductor. Signals can thus be transmitted the entirelength or breadth of the array. An advantage of this con-figuration over a cellular array, in which a cell can onlycommunicate with its neighbours, is a potentially lowerpropagation delay through the array when it is used forrealising combinational logic functions.

To determine the usefulness of such an array, thechoices for cell functions must be examined. In the mostgeneral case, each cell can use the two buses to which it isconnected as inputs or outputs. In the latter case, if othercells also drive the same bus, the wired-OR or wired-ANDfunction is performed by the bus, which one resultsdepends on the logical polarity chosen and the cell outputcircuits.

The cell functions are easily enumerated for the twocases of wired-OR and wired-AND outputs. These are pre-sented in Table 1. A cell, C, is shown in Fig. IB with itsbus connections. The signals appearing on the horizontaland vertical buses are x and y, respectively. The signalswhich would appear on the buses without the contribu-tions of cell C, i.e. if cell C were disconnected, would be xand y.

In a single array, both wired-OR and wired-AND busescan exist. Cells of type 1 and 10 can be ignored, as theyhave no effect on the buses to which they are connected.Certain combinations of cells placed in rows or columnscan perform useful elementary operations. For example, acolumn of cells of type 2 and 3 can perform the AND ofselected signals and their complements appearing on sel-ected horizontal buses. An example of this is shown inFig. 2A. Similarly, cells of types 11 and 12 can performvertical ORs. Horizontal versions of these operations can

IEE PROCEEDINGS, Vol. 132, Pts. E and I, No. 2, MARCH/APRIL 1985 73

Table 1: Possible cell functions

Cell type Signal on x bus Signal on y bus

Outputs wire ANDed

1 x=x y=y2 x = x y = yx3 x=x y=yx4 x = x • y y = y5 x=x•y y=y•x6 x=x•y y=y•x1 x =x•y y = y8 x =x•y y = yx9 x=x•y y=yx

Outputs wire ORed

101112131415161718

x = xX =X

X = Xx = x + yx = x + yx = x + yx = x + yx = x + yx = x + y

y = yy = y + xy = y + xy = y

y = yy = yy = y + x

x bus

y bus

F i g . 1 B A cell, C

2 —

3 —

u

<

I3

T2

T3

> 2

Fig. 2 A Forming the AND of signals on horizontal buses

The cell types mentioned so far may be easily realised,each with a single diode or transistor. Fig. 3A introduces

y

(

x2 ^

I

J

I

I

1

y

1>— 2

1— 3

T1

13 <

1

2 y

Ti <

> 2

— I —> 3

13

<

i

13

T3

—t3

2

T "i— 1

T13

product buses

y2 y3

JAND-OR form

X2

12

16

12

16

16

12

— fi

— u

16

Jproduct buses

Fig. 2B Two equivalent sum-of-products arrays

NAND - NAND form

be performed by cells of types 4 and 7, and 13 and 16,respectively.

Using these functions, an array can now be designed toperform a set of Boolean functions in sum-of-products orproduct-of-sums form. A simple example is given inFig. 2B, where the AND-OR and NAND-NAND formsare illustrated. All of the other six forms (AND-NOR,NAND-AND, OR-NAND, OR-AND, NOR-OR, NOR-NOR) are possible, with inputs entering either horizontallyor vertically. The number of cell types required can bereduced if inputs can be made available in complementedform.

the commonly used shorthand notation [5] for depictingrows or columns of identical cell types, and Fig. 3B givesexamples of distributed gate circuits which could realisesome of these functions. (An X on an input line denotes agate input and thus the presence of a diode or transistor.)Arrays can be drawn in the shorthand notation where anyrequired complementation is performed outside the array.Where this is the case, a complete sum-of-products arraymay be constructed from only one kind of cell.

The other cell types have internal feedback; only two ofthese are useful, however. Cell types 6, 8, 15 and 17 are

74 IEE PROCEEDINGS, Vol. 132, Pts. E and I, No. 2, MARCH/APRIL 1985

unstable, cell type 5 is an unsettable flip-flop and cell type14 is an unresettable flip-flop. The two useful types are 9

a—it

O- =

ii-

0000Fig. 3A Shorthand notation for distributed gates

a row of type 4 cellsb row of type 16 cellsc row of type 13 cells

d row of type 7 cellse columns of cells of types 2, 12, It and 3

AND

p— NOR4- -VW-

Fig. 3B Some examples for distributed gates in different technologies

and 18, which are set/reset flip-flops. Rows and columns oftype 9 or 18 cells can be constructed to provide combinedlogic and storage.

From the ten useful cell types, any digital system can beconstructed utilising any number of levels of logic. Heutink[1] suggested a design for a programmable cellular arrayusing a subset of the useful cell types. Functions can beimplemented in a smaller area if segmentation into sub-arrays is permitted. An array of this type, which permits anumber of sum-of-products arrays to be combined, hasbeen described by Greer [2]. Patil and Welch [3] designeda segmented array with embedded flip-flops, furtherincreasing the range of digital systems suitable for realis-ation in array form. Recently, a bussed array with segmen-tation and peripheral flip-flops, has been described [4].Arrays of this type are not currently commercially avail-able as standard parts however, and are therefore not con-sidered further.

2.2 Evolution of programmable logicEven though most of the currently available PLDs havebeen introduced only in the last five years, the ideas onwhich they are based belong to the origins of digital tech-nology. In this Section the evolution of the devices them-selves and of their application will be briefly presented.

Some reasons will also be suggested for their initial slowacceptance by designers, and their recent growth in popu-larity.

The earliest programmable arrays used in computerswere diode matrices constructed with discrete components.A matrix connected in the manner of Fig. 4 is capable of

inputs(with -complements)

"ANDmatrix

ORmatrix

Fig. 4 Sum-of-products with a diode matrix

realising any set of sum-of-products expressions; it can beseen that the diode AND and OR gates of Fig. 3B can beproduced in the same matrix by connection of selectedbuses to a high or low voltage, respectively. Multiple levelAND-OR functions can also be realised by defining sub-arrays. Diode matrices were originally used for decoding[6] and for implementing general Boolean functions [7].Thin film, and later integrated circuit, diode matrices weredeveloped for similar applications. At this time were alsodeveloped the first user-programmable arrays, in whichdiodes could be removed electrically [8]. Diode matriceshave limited application due to the small array sizes pos-sible when packaged independently and their effect on thenoise immunity of low voltage logic.

A parallel development, which has dominated prog-rammable logic applications, was the read-only memory.Conceptually, this is a sum-of-products matrix with anAND array which decodes all input combinations (Fig. 5).The OR array produces a programmable set of outputsindependently definable for each minterm, and is thus ana-logous to a storage array. Wilkes [9] proposed the use ofsuch a matrix for the more orderly construction of a com-puter control unit, microprogramming. (Micro-programming is the most highly developed and widelyused application of programmable logic in the form ofROMs, but its treatment is beyond the scope of thisreview.) Constructing a diode matrix with a fully decodingAND array is not, in general, an efficient way of imple-menting Boolean functions due to the redundant, repeatedlines necessary in the OR array pattern. However, with thedevelopment of integrated circuit ROMs, this inefficiencybecame less important, the primary consideration when

rJ •nputs < i

1 '

AND

(fixed)

OR

(programmable)

' y 2 minterms

' L m, /*" outputs

Fig. 5 Read-only memory (conceptual)


designing with integrated circuits being to reduce thenumber of packages. The introduction of the programm-able ROM (PROM) gave a boost to the application ofmemories as replacements for gate logic. Apart frommicroprogramming, memories have been used for codeconversion, character generation, look-up tables, sequen-tial function generators and controllers, arithmetic oper-ators and as a general purpose replacement for gates inBoolean functions [10]. The key to successful use of mem-ories for these tasks is problem partitioning, the number ofbits required in a memory being an exponential function ofthe number of inputs.

As LSI developed, a widening gap opened up betweenthe integration densities possible with memory on the onehand and unstructured (or 'random') logic on the other. Anobvious response to this was: 'Why can't logic be built likememory, in regular arrays?' ROM was one approach, butone which had limitations because of the usually unavoid-able redundancy. An array approach which did not sufferthis disadvantage was the content-addressable memory.The structure of such a memory is shown in Fig. 6. The

word n-1word n -2

i

associativearray

.!—tinput

/— • -—~-

m

.match lines

storagearray

i

outputbit lines

Fig. 6 Content-addressable memory

first array, the 'associative' or 'search' array, stores nwords, each bit of which can assume a '1 ' , '0' or 'don't care'state. Each input line passes through the same bit positionin every word of the associative array. Each word in thisarray can be thought of as the specification of the inputpattern which is required to address the correspondingword in the storage or 'read' array. Because 'don't care'can be stored in the associative array, the possibility existsfor more than one word to be read from the storage array.If, in this case, the output is defined to be the OR of allwords accessed, the content-addressable memory is func-tionally identical to the sum-of-products matrix of Fig. 4;each 'match' line is a product term. IBM [11] investigatedthe use of such arrays as a general purpose LSI tech-nology; one circuit type could potentially implement all ofthe logic of a computer. They designed a content-addressable module, to which they gave the name Func-tional Memory, with combined associative and storagearrays having additional control logic for sequencing thesearch, read and write operations. The conclusion of thiswork was that the technology gave too much freedom,similar aims could be achieved with the simpler read-onlyequivalent, the programmable logic array (PLA).

The PLA (also termed the read-only associativememory, ROAM [12], or AROM [13]) was seen in theearly days of LSI as a useful method of reducing the designtime of control logic in processor integrated circuits [14].It is a technique which is now widely used. Applicationswere also seen for discrete PLA circuits, as a more efficientreplacement for gates than ROMs [12]. In 1970, TexasInstruments introduced a pair of mask-programmable

MOS PLAs with built-in state registers, circuits whichwere universal sequential machines of the Mealy type [15](Fig. 7). These circuits were slow (200 kHz clock frequency)

input<

state register(clocked)

output

Fig. 7 PLA universal synchronous sequential machine

and were not suitable for gate replacement, but for taskssuch as industrial machine control. In 1973 National Semi-conductor announced another mask-programmable device,a 14 input, 8 output, 96 product term PLA withoutstorage, having a propagation delay of 150 ns [16]. Againuses of this device were predicted in slow sequential con-trollers, but also as a package-saving ROM replacement.The most successful applications were those in which thedesign was conceived in terms of PLAs. For example, thecontrol store of a small computer can be advantageouslyreplaced with a PLA [17], or a complete digital systemwith distributed data processing sections and controllerscan be built from PLAs [18].

Despite the wide potential field of application, PLAsdid not achieve the hoped for success outside the computermanufacturers. Reasons for this were suggested to be [19]:the dedicated controller market was dominated by themicroprocessor, a component which could be programmedby people from a software background; PLAs were tooslow for many tasks; prototyping designs was costly; thegenerally available computer-aided design tools, essentialfor other than simple designs, were inadequate. The pro-totyping problem was solved by the introduction of thefield-programmable logic array (FPLA), which broughtPROM technology to the PLA [20, 21]. However, tomake a significant impact, the PLA would have to be in aform which was more widely applicable in general digitaldesign. This was achieved with the invention of the PAL[5] (which stands for Programmable Array Logic, a termwhich serves as a trademark rather than a description).The PAL is an FPLA with a fixed OR structure, similar tothat described in Reference 12; sets of product term linesare permanently connected to an OR gate (Fig. 8). Productterms thus cannot be shared among outputs. The PAL wasan answer to some of the criticisms of the PLA/FPLA; thechip was smaller because only a single array was nownecessary, and for the same reason it was faster and easierto manufacture. A number of versions were introducedwith different input, output and OR gate arrangements toincrease the number of application possibilities.

PAL applications are predominantly in the data pathsof digital systems, or for self contained functions such asdecoders and counters. For these tasks, the fixed OR arrayis usually not a disadvantage, as product term sharing isseldom possible. PALs are often seen as simply more flex-ible versions of standard parts, for example if a register isrequired with an additional mode, it may be more eco-nomical to create one with a PAL than adapt a standardpart by adding extra peripheral gates. FPLAs, on the otherhand, are often the most suitable devices for implementing


controllers, especially in the form of the field-programmable logic sequencer (FPLS), introduced at

input

outputFig. 8 PAL structure

about the same time as the PAL, a device which has aninbuilt state register.

Since the rejuvenation of the programmable logicmarket by the acceptance of the PAL, a number of manu-facturers have entered with further variations. This hasresulted in a wide choice of components; there is now aspectrum of both device architectures and array sizes.However, there is still user education to be carried out, asthe recent increase in popularity of programmable logichas bypassed many of the system design issues raised tenyears ago when the potential of PLAs was extensivelystudied, especially by IBM. These will have to be raisedagain if programmable logic is to become more than a'random logic' replacement in conventionally designedsystems.

2.3 General modelSince there are now about 70 programmable logic deviceseither in production or announced, there is a need for auniform method of device description. A method is pre-sented here, based on the general structure shown inFig. 9.

In the most general device, each input passes throughan input cell, which may contain storage, and is fed intothe input decoder. In the majority of FPLAs and PALs,this is a one-bit decoder, i.e. each bit is individually

decodersoutputcells

outputs(inputs)

trclock(s) .external controls

Fig. 9 General structure for programmable logic devices

IEE PROCEEDINGS, Vol. 132, Pts. E and I, No. 2, MARCH/APRIL 1985

decoded into two signals, one true and one complement.(In a memory, this would be an n-bit decoder if there weren inputs.) PLAs have been built with other than one-bitdecoders [18], which have certain advantages, but none ofthis type is available commercially. The logic array may bea full AND-OR array (PLA), an array with no OR (field-programmable gate array, FPGA), or an array with a fixedor only partially programmable OR (PAL). In parallelwith the logic array and operating on the same inputs isthe control array. The function of this array is to select themode of multimode output cells. A great variety of outputcell types are used, both with and without storage. Someare defined to have fuse-programmable modes so that, forexample, storage cells can be permanently bypassed.Finally, some of the outputs can be fed back into the logicand control arrays to allow either synchronous or asyn-chronous sequential machines to be produced.

Synchronous circuits will have one or more clockinputs. The control inputs can have functions such aspreset, clear or load registers, or enable the outputs.

Fig. 10 presents a set of output cells sufficient todescribe the current family of components, whose architec-tures are summarised in tabular form in Table 2. Otherswill have to be added as new designs emerge. These celltypes are either permanently defined, or selected by controlarray outputs or by blowing fuses. (This explains the pre-sence of the 'output' cell type 9, which is in fact an input.)

3 How can programmable logic be used?

The ways in which programmable logic can be used relateto the level in the design hierarchy at which its use is con-sidered. Fig. 11 shows four levels of the digital design hier-archy chosen to support the present argument. At level 1the specification of the system's function exists; this ideallycontains no details of the implementation. Level 2 is thesystem architecture; this is a description of the major func-tional blocks of the system and their interconnection.Control and data processing will be separated where thiscan be done conveniently. The architecture may be con-strained by certain major components, such as micro-processors, on which it is based. At level 3, all of thecomponents have been selected and the first iteration of adetailed design exists. Finally, at level 4 the design hasreceived its final stage of optimisation. The optimisationcriteria will, of course, depend on the intended use of thecompleted system.

It is possible to construct an entire digital system inprogrammable logic, apart from memory and purely elec-trical functions, such as buffers and level translators [18].This would seldom be a sensible course of action though,as many standard parts are likely to be directly usable.(Also, no PLAs of the size used by Logue et al. [18],capable of containing a number of subsystems, are avail-able, making such an approach less likely to be eco-nomical.) The exception is the case of very small systemswhich perform mainly a control function; an FPLS may beall that is required.

Perhaps the most appropriate level at which to considerprogrammable logic is after the definition of the systemarchitecture. Here the system is divided first into sectionswhich can readily be allocated to component types, such asmemory, standard arithmetic circuits, bus data interfacecircuits or microcomputer components and, secondly, intosections where the choice is not obvious. Examples of thelatter are blocks labelled 'controller', non-standard arith-metic or data processing functions, and logical 'glue'required to format signals entering and leaving complex

77

s

pA

Q

clock

/

D Q

C EN

/• ^

D Q

A°clock

S 0

RA

clock

D Q

AI

clock

D Q

_ clock

K RA

3

Fig. 10 Output cellsC denotes control array output— $ — denotes a fuse

• — denotes an external input• denotes a connection to other output cells

a directb direct with enablec complementaryd direct with programmable polaritye direct with programmable polarity and enable/ S-R flip-flopg D latchh input/outputi direct feedbackj input/output with programmable polarityk input/output with programmable polarity and dual internal/external enable/ inputm D flip-flop with feedbackn S-R flip-flop with feedbacko D flip-flop with programmable polarity and feedbackp D flip-flop with feedback, input/output and programmable polarityq D/S-R flip-flop with programmable polarity, input/output and dual enable, inter-nal clockr J-K/D flip-flop with feedback and load ( © = 3-state connection)s J-K. with feedback, internal clock and reset


standard components. Whether it is indeed an advantageto use programmable logic will depend on cost, com-

level1 system function

specification

^consider programmable logic

systemarchitecture


componentsselected


optimiseddesign

Fig. 11 Programmable logic in the design hierarchy

ponent count, power consumption as compared to otheralternatives, and acceptability of the parts in the applica-tion. In addition, design techniques for the use of the com-ponents must be familiar to the designer; these requiresome knowledge of 'classical' switching theory.

At the lowest level, a design utilising only standardparts is to be optimised by the possible replacement of sec-tions by programmable logic. This was the 'first gener-ation' approach to design with PALs [22].

The evolving use of programmable logic since then canbe traced by studying References 23-28. Section 7 willdiscuss some of the factors to be considered when decidingwhether programmable logic should be used in a design.

4 Design techniques4.1 Standard part replacemen tThis is the least challenging, but perhaps most widely useddesign technique. In its simplest form it entails drawinglines around sections of a logic circuit diagram potentiallyreplacable by a PLD. Replacement is possible if thenumber of inputs and outputs do not exceed the device'scapacity, the number of product terms required is smallenough, and timing requirements can be met.

A similar technique is the realisation in a PLD of partswhich are only slightly different to standard ones, butwhich saves the gates which would be required to adaptthe function of the standard part. Examples are specialisedcounters, or multifunction registers.

4.2 ControllersGiven that the PLA is a natural component for realising aset of Boolean functions, it is only a small step to therealisation of sequential machines. As a controller is asequential machine with, in general, very little regularity inits defining Boolean equations, the PLA would thusappear to be a suitable component to use (see Fig. 7).However, when using programmable logic, the designer isconstrained to use certain predefined array architectures.The controller may have to be partitioned to fit into theavailable components, or a microprogrammed solutionusing ROMs may be preferable. Fig. 12 summarises thecontroller design process.

All of the PLDs may be used in controllers, but someare more suited to this task than others. The FPLS deviceswere designed to be efficient controllers, whereas the PALdevices (perhaps with the exception of the most recenttypes), with their fixed OR structure and, in most cases,fixed output polarity, are more difficult to use for otherthan simple controllers.

One of the major difficulties of controller design is thelack of a standardised method of specifying function. The

specification ofcontroller (e.g. A.S.M)

choose PL divice (s)(optimise)

designcomplete

YES

Fig. 12 Stages in controller design

variety of methods presented by the different manufac-turers in their application notes and articles has obscuredthe essential simplicity of the design procedure. One sys-tematic method for controller design is ASM [29](algorithmic state machine). Fig. 13 shows a system clock

Fig. 13 Clock controller ASM chart

controller described in ASM as an example of a small con-troller. (For simplicity, full details of the design are notpresented.)

ASM describes synchronous sequential machines byadapting flowchart notation to describe state transitions.States are represented by boxes and binary decisions bydiamonds. Outputs asserted unconditionally for the dura-tion of a state ('CLOCK 1', 'CLOCK2', 'ENSW') arenamed in the state boxes; outputs asserted only on giveninput conditions are named in rounded boxes placedbetween states. Having drawn an ASM chart and made astate assignment, a state table can be produced (Fig. 14) bytracing all 'link paths' between states. Each link pathdefines a line of the state table. A link path can be identi-fied with a product term in a PLA if D-flip-flops are usedin the state register; the 'present state' and 'inputs' columnsthus define the AND array, and the 'next state' and'outputs' the OR array. If a PLA is able to accommodatelinkpath

123

Fig. 14 State table format

presentstate inputs next

state outputs


the table directly, no optimisation would be required.Fitting this table into a PAL is more difficult, as only inrare cases would there be a single T o n each line of the'next state' and 'output' columns, as would have to be thecase with a fixed OR array. Lines would either have to beduplicated to separate these T s or some minimisationwould have to be performed.

Minimisation for PL As is a multiple function problem;numerous algorithms exist e.g. Reference 51. Minimisationfor PALs is a single output problem due to the indepen-dent OR gates. A convenient manual procedure for mini-misation with PALs or for reduction with PLAs when usedin state machines is the method of 'map-entered' or infre-quently used' variables [30], which overcomes the problemof constructing Karnaugh maps of large dimension. Anautomated method which provides near-optimal PLAimplementations, together with a state assignment, isdescribed in Reference 31.

Certain of the FPLS devices allow a degree of opti-misation with very little expenditure of effort by thedesigner; they increase the likelihood of being able toproceed directly from ASM chart to device program. Forthose parts which use R-S or J-K flip-flops, 'hold tran-sitions' (Fig. 15) may be coded with no product term; nostate variable changes, therefore all state flip-flop inputswill be '0'. Some contain a 'complement array', as shown in

Fig. 15 'Hold'transition

Fig. 16A Complement array

Fig. 16A. This is an additional OR line which is invertedand fed back into the AND array. The use of this facility isillustrated with reference to the ASM fragment of Fig. 16B.There are five link paths from the state box, but three ofthese end in state A. The link paths to states B and C eachrequire a product term, but if the link paths to state A arethought of as the paths which 'do not lead to state B orstate C this condition can be detected by appropriatecoding of the lower (NOR) line of the complement array.This can now be used to define just one product term forall three link paths to state A. The complement array canbe used in every state of the machine, but for only one'bundle' of link paths per state in general. The exception iswhere the inputs can be partitioned to enable more thanone complement term to be defined.

The ASM method, while easy to use and systematic, haslimitations; some of these will be addressed and extensionsproposed in a future publication.

4.3 Data path elementsData path elements can also be viewed as sequentialmachines after the model of Fig. 7. Instead of the registerholding an explicitly specified machine state, it contains adata word. The combinational logic of the machine definesthe processing to be performed on this word and on anexternally input data word. Parallel data path elements aremade up of strings of (usually) identical one-bit processingelements, with perhaps signals (e.g. carries) passingbetween them. This structure naturally fits the PAL family,and in fact data path elements are very easy to specify forPAL implementation. PALs containing registers makesuitable elements for pipelined data processors [28].

Arithmetic function realisation does present interestingproblems, though. A PLA version of a four-bit fully paral-lel adder would need 105 product terms, while an eight-bitadder would need 2009 [32]. It is clearly impractical to usea standard PLA for this task. Modifications to the PLAarchitecture have been proposed to reduce the array sizerequired by study of the nature of arithmetic computa-tions. One such is shown in Fig. 17; the OR array is split

input

destinationstate A B A C

Fig. 16B Link paths with common destination states

Destination state

output

Fig. 17 PLA with exclusive-ORed outputs

into two arrays, P and Q, whose outputs are exclusive-ORed [33]. The addition (or subtraction) operation can beexpressed as A © B © C, where A and B are the operandsand C is the carry from the previous bit position. Thisrequires four product terms. A © B can be evaluated as asum of products in the P array, requiring two products,and the carries can be evaluated in the Q array. The finalstage of the addition takes place in the exclusive-OR stage.The technique can be applied to the PAL structure, whichnow has multiple partitioned OR arrays. PALs of this typeare useful for the economical construction of counters, forexample. More complex arithmetic operators can addi-tionally benefit from two-input decoders at the inputs [33].Weinberger demonstrates how large adders can be simpli-fied with this feature [34]. One of the PAL devices has

80 1EE PROCEEDINGS, Vol. 132, Pts. E and I, No. 2, MARCH/APRIL 1985

both output exclusive-OR gates and two-bit decoding,making it particularly suitable for arithmetic functions.There would have to be strong reasons, of course, for usingsuch a device in preference to a standard, optimised, arith-metic part.

4.4 Combined functionsAs larger PLDs become available, it is often no longer effi-cient to dedicate an entire part to a purely controlling ordata processing role. If a subsystem is realised with a singledevice, it is very likely to contain both types of function.This type of design was adopted by IBM [18], but has stillto be used in everyday programmable logic design. Themain reason for this is the limited array sizes and numberof registers available in PLDs. The FPLS devices, the mostflexible components, usually do not have enough flip-flopsto allow complex controllers and parallel data processingto be performed together, while PALs, when used for dataprocessing, do not leave much room for more than simplecontrollers. However, PALs with 16 and 32 flip-flops andflexible allocation of product terms to pairs of OR gatespossible, are becoming available. These parts will enablemixed functions, but because of their less flexible PALstructure, design will be more difficult than with PLAshaving the same number of inputs and outputs, in whichany product term can contribute to every output.

4.5 Asynchronous systemsAlthough asynchronous sequential circuits are generallyavoided in digital systems design due to difficulties in reli-able design and testability, they cannot be completelyavoided. Where synchronous systems with different clockshave to communicate, or where a very rapid response isrequired, asynchronous circuits have to be used.

The classical techniques of asynchronous design can beapplied directly to PALs and PLAs. These designs mustgenerally be confined to small machines, owing to the diffi-culties of applying these methods to machines with manystates. Ditzinger and Lipp [35] have developed a modelapplicable to any array logic device (ROM, RAM, PLA orPAL) which can be used to assess its suitability in asyn-chronous machines. The parameters of this model have tobe measured for each device type. If the device chosen hassuitable parameters, then it can be used to construct a reli-able asynchronous machine with an arbitrary state assign-ment. Hayes [36] describes another method of designinglarger asynchronous machines with PLDs by adapting asynchronous machine to be self clocking.

A recently introduced PAL device, the 20RA10 (seeAppendix 10), has output cells with flip-flops which can beused asynchronously, or clocked individually (see No. 17of Fig. 10). This configuration allows more possibilities fordesign of the 'standard logic replacement' type and alsogives opportunities for the construction of asynchronoussequential machines by using the flip-flops in set/resetmode.

5 CAD for programmable logic

The key to effective use of programmable logic is anappropriate set of computer-aided design tools. These donot have to be very complex, but the design process wouldsoon become unmanageable without them. Good CADalso encourages a high-level design approach appropriateto programmable logic; gates should be considered only asan implementation option, not as a design primitive.

The simplest type of design aid uses the PLA 'person-ality' table as the primary input. With a little practice, thisnotation is easy to understand and it has the advantagethat pretested macros can be inserted [33]. It is also veryeasy to convert ASM designs directly into this format, pro-vided no optimisation is required. The low level designsoftware for FPLA/FPLS devices accepts this type ofdescription.

The most widely used method of specification isBoolean equations. Here the sum-of-products expressionsare.entered into a source file which is assembled into adevice program file. Although others have been written[36], the assembler written to support the first PALs,PALASM [22], has virtually become a standard.PALASM has been adopted by a number of PLD andprogramming equipment manufacturers. It cannot carryout any optimisation, but for most PAL applications thisis not a disadvantage. Boolean equation specification is anatural one for relatively simple data path elements, butfor more complex data processing operations and control-lers, it is an inadequate form of documentation. The func-tion, especially for a controller, is not visible from aPALASM specification. For example, the specificationbelow describes an implementation of the controller of Fig.13, the function is impossible to discern. Lines 5 and 6 listthe allocation of signals to pins. The Boolean equationsstart on line 8. '/' denotes negation and '*' denotes AND.(The output 'XOR' and the inputs 'XT and 'X2' belong toan exclusive-OR gate using some of the unwanted logic ofthe PAL.)

PAL16R4 PAL DESIGN SPECIFICATIONCK M.J.P. BOLTON 11/83CLOCK CONTROLLER FOR ALU EXPERIMENTE & EE, UNIVERSITY OF BRISTOLCLK LOAD STEP RUN /RESET NC NC XI X2 GND/EN XOR /ENSW /SO /EN2716 CK2 CK1 NC NC VCC

/CK1 == RESET + /CK1*/CK2*EN2716*/SO*/RUN*/STEP*/RESET+ CK1*CK2*EN2716*/SO*/RESET+ /CK1*/CK2*EN2716*SO*/RUN*/RESET+ CK1*CK2*EN2716*SO*/STEP*/RESET+ CK1*/CK2*/EN2716*/SO*/LOAD*/RESET

/CK2 := RESET + /CK1*/CK2*EN2716*/SO*/RUN*/STEP*/RESET+ CK1*CK2*EN2716*/SO*/RESET+ /CK1*/CK2*EN2716*SO*/RUN*/RESET+ CK1*CK2*EN2716*SO*/STEP*/RESET+ /CK2*/EN2716*/SO*/RESET


EN2716== RESET + /CK1*/CK2*EN2716*/SO*/RUN*/STEP*/LOAD*/RESET+ /CK1 */CK2*EN2716*/SO*RUN */RESET+ /CK1*/CK2*EN2716*/SO*/RUN*STEP7RESET+ CK1*CK2*EN2716*/SO*/RESET+ /CK1*/CK2*EN2716*SO*/RESET+ CK1*CK2*EN2716*SO*/RESET+ CKl*/CK2*/EN2716*/SO*/LOAD*/RESET

SO == /CK1*/CK2*EN2716*/SO*/RUN*STEP*/RESET+ CK1*CK2*EN2716*/SO*/RESET+ CK1*CK2*EN2716*SO*STEP*/RESET

/X1*/X2 + X1*X2/XOR =

Recently, universal assemblers have been introduced forPLDs. The two currently available are Cupl [37] and Abel[38]. These programs do what PALASM does, but fordevices from every manufacturer, including ROMs, andoffer further features to simplify specification. Theseinclude the ability to operate on fields of bits, especiallyuseful for data and decoding operations, arithmetic oper-ators, and nested forms of algebraic specification. A formof state machine description is provided, making controllerdescription more direct and readable. The availability ofthese programs is sure to add to the popularity of prog-rammable logic, removing as they do some of the diffi-culties of specification. Both also offer minimisation.Another assembler, also able to accept a database of manydevice types, is PLPL [39]. PLPL has, or is planned tohave, the facilities mentioned above in addition to a blockstructure allowing a succinct description of arrays of pro-cessing cells. A compiler which accepts ASM input directlyhas also been developed, but this is only available on aparticular CAD system [40]. This compiler includes auto-matic state assignment and minimisation.

Whereas it is very desirable to have these CAD tools,each new one brings with it a new hardware descriptiondialect. Standardisation is obviously needed, but in arapidly growing market with a number of different manu-facturers competing, this could be a slow process.

6 Testing aspects of programmable logic

Since the last stage of manufacture of a PLD is performedby the user, and each design produced is unique, testing isof importance even for prototyping work. Before insertingthe programmed device into the system, the user must besure that it functions correctly. The techniques used formemory functional testing are not adequate for nonmem-ory PLDs. For a PROM, verification of the programmedfuse array using normal inputs and outputs is a sufficientfunctional test. For the other devices, a verified fuse arraydoes not imply a correctly functioning device since logicexists which has not been tested. Some manufacturers dotest this by means of circuitry added to the chip, others donot.

Two types of testing are therefore required: array verifi-cation and logic verification. The first of these is straight-forward and can be done by the programming equipment;it is simply a test to verify that the required fuses havebeen blown correctly. The second is a test of the functionof the complete device and may take one of the followingforms:

(a) exhaustive testing(b) tests designed to test postulated faults(<•) tests generated from a knowledge of function(d) pseudo-random testing with output compression.

For type c and d testing, some measurement of test cover-age with respect to postulated faults is required. Deviceswith registers are much harder to test because the problem

exists of setting the register to a known state. However, themore recent sequential PLDs have loadable registers, thusreducing the effort required to generate tests.

Exhaustive testing entails the measurement of theresponse of the device to every possible combination ofinputs. The responses are compared to those calculatedfrom the specification. The problems with this method oftesting are the time required to present the large number ofvectors to the device and the time required to calculate theexpected response from the specification. For thesereasons, this method of test is not widely used.

Testing of type b depends on the availability of algo-rithms to generate the test vectors. A number of these havebeen described specifically for PLA test pattern generation[41-47]. The incorporation of such automatic test vectorgeneration into the CAD programs available will be animportant addition.

Type c testing relies on the designer generating testvectors manually based on a knowledge of the intendedfunction of the device. These vectors are also a usefulmeans of verifying the correctness of the specification,especially where a Boolean equation description has beenused. The assembler programs have simulators whichenable this correlation to be done. Also available fromthese programs is a measure of the coverage of the testvectors with respect to certain faults. If some faults arefound not to be testable, further vectors can be created.

The final form of testing, pseudo-random testing, whichis offered by some manufacturers of PLD programmingequipment, relies on a correctly functioning device forcomparison. In an application of signature analysis [48],the device under test is excited with a fixed number ofpseudo-random inputs from a linear feedback shift registerwhich accumulates a signature for the test. This signatureis then compared to that obtained from a verified device. Ifthey are the same then the tested device is very likely to becorrect, provided the test sequence is long enough [49].This type of testing works less well for sequential devicesand should be used in conjunction with predefined testvectors.

As with any logic design, it is possible to designuntestable programmable logic, both at the device andsystem levels. Untestable designs can be detected by mea-suring fault coverage at an early stage. At system level,methods such as scan path design can be used to ensuretestability. Future PLDs will have this form of testingfacility included.

7 Comparison with other semi-customtechnologies

The principal justification for the use of programmablelogic is the potential for reduction of parts count andcircuit board area, and thus system cost since many of thecomponents of the final manufactured cost of a digitalsystem are proportional to the number of integrated cir-


cuits used. It is impossible to state, in general, how manyfewer parts would be required if programmable logic wereemployed in place of standard circuits; the ratio of stan-dard parts required to a programmable logic replacementdepends on the architecture of the system, how effectivelythe programmable logic is used, and the complexity of theprogrammable logic part. For example, some functionswhich programmable logic can perform very economically,such as controllers, are very expensive when performedwith a limited number of gate types. A ratio of 4:1 for partreplacement is typical for the smaller PLDs [27], whileratios of over 10:1 are possible for the more complexPLDs.

The main rival to programmable logic is the gate array.Gate array chip complexity is often stated in number ofsimple gates and/or flip-flops. A similar measure for prog-rammable logic is not meaningful. For example, functionscan be programmed for the 10H8 PAL which are equiva-lent to between 8 to over 100 two-input gates. Some of therecent larger PLDs are suitable alternatives to the smallergate arrays [50] with figures of 500 to 1000 equivalentgates being given. Comparisons of this kind can only betaken seriously in the context of a particular application.The small number of flip-flops in PLDs (the larger deviceshave 10, 16 or 32) is perhaps a greater constraint than thesingle array; this is effectively partitioned in most largerapplications. A difficulty with programmable logic designhas been the inflexibility of the clocking scheme provided,all registers being connected to the same clock signal.Many gate arrays allow more flexible clocking arrange-ments, making this design medium more suitable for lowlevel design techniques. Some recent PLDs, however, alloweach register to be clocked independently. It could beargued, though, that a higher level of design encouraged bya strictly synchronous regime is desirable.

The great advantages of programmable logic are therapid turnaround of prototypes possible and its adapt-ability. The devices are adaptable as the function per-formed by a component or even its pinout can be easilychanged. This, together with the rapid programmingprocess, make it an ideal prototyping medium. One strat-egy for digital system development which combines thelower unit cost of gate arrays and the flexibility of prog-rammable logic is to implement those parts of the systemwhich are unlikely to change, such as the data paths, ingate arrays, and those which could be subject to laterevision, such as controllers, in programmable logic [28].Some PLDs are available in mask programmable form atlower cost due to the lack of programming circuitry. Herethe comparison with gate arrays becomes more difficult,since both alternatives are committed by the manufacturer.

Factors which count against programmable logic arecomponent cost, power consumption and reservationsabout the reliability of fuse programmed devices. The pro-duction economics of some digital systems are such thatthe higher component cost of programmable logic couldnot be tolerated; in some cases the use of a greater numberof standard parts may be preferable. Power consumptionand reliability will be mentioned in the next section.

In summary, programmable logic will always save com-ponents when used in place of low integration level stan-dard parts, parts which need to be used even in VLSIsystems. Some of the larger PLDs may be able to performthe same function as a small gate array. PLD personalitiesmay be developed very rapidly and can be altered even ata late stage in a design. The use of programmable logic aspart of a top-down design strategy allows rapidly pro-duced and reliable designs.

8 Concluding remarks: current developments

Programmable logic is developing in two ways; improve-ments in device technology and in architectures.

In high speed systems, programmable logic has alwaysbeen difficult to apply because of the limited speed of thearrays in comparison with gates. There has been a steadyprogress in PAL speed, with 15 ns maximum propagationdelay devices now in production. Even faster devicesintended for ECL systems are planned. Another drawbackof programmable logic has been the high power consump-tion of the static arrays used. The bipolar devices havebeen produced in slower but lower power versions, andnow CMOS PLDs are available. A principal application ofthe CMOS devices is seen in the support of CMOS micro-processors.

Erasable PLDs are now available. These componentswill obviously ease prototyping, but there is less need gen-erally for erasable PLDs than for erasable memories.However, these devices, with their charge storage cellsrather than fuses, can occupy a smaller silicon area [52],and can be fully tested by the manufacturer, so it is likelythat their use will become very widespread.

The larger arrays now being manufactured are becom-ing more flexible. Some of the features of PLAs, forexample, programmable output polarity and a largernumber of product terms available per output, are beingadded to PALs. At the same time the newer versions of theFPLA/FPLS are becoming more uniform with simpleroutput cells. Perhaps, with even larger arrays, the con-vergence will be complete and the PLA/PAL distinctionwill no longer exist. These newer components are alsomore easily tested by the user and more comprehensivelytested by the manufacturer than previously. For other thanvery small logic replacement tasks, a single device such asthe 22V10 [50] will fulfill most requirements.

The use of the large PLDs demands a good CADpackage. Developments in CAD are likely to continuebeyond the packages currently available in the areas ofhigh level specification languages, automated logic gener-ation and optimisation, and automatic test vector gener-ation. In addition, this CAD will have to be integrated intothe framework of a comprehensive digital design automa-tion environment, where programmable logic is only oneimplementation option.

9 References

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12 HENLE, R.A., HO, IT., MALEY, G.A., and WAXMAN, R.: 'Struc-tured logic'. AFIPS Conference Proceedings, 1969, 35, (AFIPS Press,1969) pp. 61-67

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18 LOGUE, J.C., BRICKMAN, N.F., HOWLEY, F , JONES, J.W., andWU, W.W.: 'Hardware implementation of a small system in prog-rammable logic arrays', IBM J. Res. & Dev., 1975, 19, (2), pp. 110-119

19 VODOVOZ, E.: 'Programmable logic arrays: A dormant giant awak-ening', EDN, 1975, 20, (5), pp. 29-35

20 CAVLAN, N., and CLINE, R.: 'Field-PLAs simplify logic designs',Electron. Des., 1975, 23, (18), pp. 84-90

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27 CARLSON, D.A., and MORIN, R.P.: 'Care in packaging off-the-shelfLSI keeps 32-bit minicomputer compact', ibid., 1982, 55, (20), pp.115-119

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33 JONES, J.W.: 'Array logic macros', ibid., 1975, 19, (2), pp. 120-12634 WEINBERGER, A.: 'High-speed programmable logic array adders',

ibid., 1979, 23,(2), pp. 163-17835 DITZINGER, A., and LIPP, H.M.: 'Use of memories and prog-

rammable logic arrays for asynchronous sequential circuits', IEE J.Comput. & Digital Tech., 1979, 2, (5), pp. 213-220

36 SHERWOOD, W.: 'PLATO—PLA translator/optimizer', Proc. ofthe symposium on design automation and microprocessors, (IEEE,New York, 1977), pp. 28-35

37 'CUPL 1.0 user's manual' (Assisted Technology Inc., Oct. 12th, 1983,Revision B)

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39 KITSON, B, and OW-WING, K.: 'Logic-programming languageenriches design processes', Electron. Des., 1984, 32, (6), pp. 183-192

40 'Daisy Hardware Compiler', Preliminary specification, Daisy SystemsCorp., June 1983

41 MUEHLDORF, E.I., and WILLIAMS, T.W.: 'Optimized stuck faulttest pattern generator for PLA macros', 1977 Semiconductor testsymposium, (IEEE, New York, 1977), pp. 89-102

42 CHA, C.W.: 'A testing strategy for PLAs', Proc. of the 15th annualdesign automation conference, (IEEE, New York, 1978), pp. 326-334

43 OSTAPKO, D.L., and HONG, S.J.: 'Fault analysis and test gener-ation for programmable logic arrays (PLAs)', FTCS-8. The 8th inter-national symposium on fault-tolerant computing, Digest of Papers,(IEEE, New York, 1978), pp. 83-89

44 SMITH, J.E.: 'Detection of faults in programmable logic arrays',IEEE Trans., 1979, C-28, (11), pp. 845-853

45 EICHELBERGER, E.B, and LINDBLOOM, E.: 'A heuristic test-pattern generator for programmable logic arrays', IBM J. Res. &Dev., 1980, 24,(1), pp. 15-22

46 AGARWAL, V.K.: 'Multiple fault detection in programmable logicarrays', IEEE Trans., 1980, C-29, (6), pp. 518-522

47 SOMENZI, F , GAI, S., MEZZALAMA, M., and PRINETTO, P.:'PART: Programmable array testing based on a partitioning algo-rithm', ibid., 1984, CAD-3, (2), pp. 142-149

48 FROHWERK, R.A.: 'Signature analysis: A new digital field testingservice method', Hewlett-Packard J., 1977, 28, (9), pp. 2-8

49 DEPINA, R.M., and BELMONDO, V.E.: 'Functional testing of logicarrays', 11th semi-annual ATE seminar/exhibit proceedings (Morgan-Grampian Publishing, 1982) pp. VI/32-49

50 KITSON, B., LAWS, D., and MILLER, W.: 'Programmable logicchip rivals gate arrays in flexibility', Electron. Des., 1983, 31, (25), pp.95-98, 100, 102

51 BRAYTON, R.K., HACHTEL, G.D., McMULLEN, C.T., andSANGIOVANNI-VINCENTELLI, A.: 'Espresso-II: a new logicminimiser for programmable logic arrays', Proceedings of the 1984custom integrated circuits conference, (IEEE, New York, 1984), pp.370-376

52 RAPPAPORT, A.: 'First CMOS reprogrammable logic array specslow power and UV erasability', EDN, 1984, 29, (9), pp. 93-96

(Notes to Table 2 continued)

NotesThe OR array is shown as (products) * (outputs), or as a collection ofgates.Partitioning is shown with brackets for multiple sections and commasfor separation.Control terms are single additional product terms. Control outputswhich come from the OR array are not included in the control termcount.The number of inputs to gate is added as an argument, e.g. AND(3).

1 feedback variables from the registers and 4 of the inputs are pair-wise decoded

2 XOR(2) inputs come from pairs of OR gates. Some product termsare predefined

3 type m outputs are externally enabled4 type o outputs are externally enabled5 XOR(2) inputs come from pairs of OR gates6 eleven inputs optionally pass through separately clocked flip-flops7 eleven inputs optionally pass through separately enabled latches8 one input is common with the clock9 registers have asynchronous preset and clear

10 output register partitioned into two separately clocked and exter-nally enabled banks11 asynchronous output register preload is provided12 all cells in a bank must be of the same type13 four output register presets14 output register partitioned into four separately clocked and exter-nally enabled banks15 outputs externally enabled16 programmable external preset or enable17 complement array provided18 outputs controlled in groups of four19 outputs enabled in two groups programmably from one pin20 outputs of type r in groups of two21 outputs of type r in groups 9, 2 and 4. First group P and R fromcontrol array22 outputs of type r in two groups of four P's and R's from controlarray23 type s output cells have a common clock and reset24 registers reset on power up


10 Appendix

Table 2: Programmable logic device architectures

Partnumber

10H810L810P812H612L612L1012P1014H414L414L816A4

16C116H216H816HD816L216L616L816LD816P816R416R616R816RP416RP616RP816X418L4R19L8R19R4R19R6R19R8T19L8T19R4T19R6T19R820C120L220L820L1020P820R420R620R820RA1020RS4

20RS820RS1020S1020X420X820X1022V10/22RP10

32R1664R3282S100/182S102/382S104/582S150/182S152/382S154/582S156/782S158/982S16182S16774333/574839/40

Numberofinputs

101010121212121414148

161610101616101010888888818131111111311111120201412141212121010

10101210101012

16321616166844412141214

Numberoffeedbackvariables

—————————8

——66——6668888888—68886888——6868881010

1010810101010

1632——61210121212—84—

ANDarray

20x8(2)20x8(2)20x8(2)24x4(2),2(4)24x4(2),2(4)24x10(2)24 x 10(2)28 x 4(4)28x4(4)28x6(2),2(4)32x4(7),(4,5),(4,6),(4,7),(4,8)32x1632x2(8)32x8(7)32 x 8(8)32 x 2(8)32x4(4),2(2)32x8(7)32x8(8)32x8(7)32x4(7),4(8)32x2(7),6(8)32x8(8)32x4(7),4(8)32x2(7),6(8)32x8(8)32x4(7),4(4,4)36x2(6),2(4)38x8(7)38x4(7),4(8)38x2(7),6(8)38x8(8)38x8(7)38x4(7),4(8)38*2(7),6(8)38x8(8)40x1640 x 2(8)40 x 8(7)40x10(3)40x8(7)40x4(7),4(8)40x2(7),6(8)40 x 8(8)40x10(4)40x2(7),2(14),2(16)40x2(7),4(16)40x2(8),4(16)40x2(7),4(14)40 x 6(3),4(2,2)40 x 2(3),8(2,2)40x10(2,2)44x2(8),2(10),2(12),2(14),2(16)64x8(16)128x16(16)32x4832x944x4836x1236x3232x3232x3232x3224x4844 x4832x3228x32

ORarray

8OR(2)8NOR(2)8OR(2)4OR(2),2OR(4)4N0R(2),2N0R(4)10 N0R(2)10 0R(2)40R(4)4NOR(4)6NOR(2),2NOR(4)4NOR(7),4XOR(2)

OR(16)2OR(8)8OR(7)8OR(8)2NOR(8)4NOR(4),2NOR(2)8NOR(7)8NOR(8)8OR(7)4NOR(7),4NOR(8)2NOR(7),6NOR(8)8NOR(8)4OR(7),4OR(8)2OR(7),6OR(8)8OR(8)4NOR(7),4XOR(2)2NOR(6),2NOR(4)8NOR(7)4NOR(7),4NOR(8)2NOR(7),6NOR(8)8NOR(8)8NOR(7)4NOR(7),4NOR(8)2NOR(7),6NOR(8)8NOR(8)OR(16)2NOR(8)8NOR(7)10 NOR(3)8OR(7)4NOR(7),4NOR(8)2NOR(7),6NOR(8)8NOR(8)10 0R(4)2OR(7),2[OR(n),OR(14-n)],2[(OR(n),OR(16-n)]2OR(7),4[OR(n),OR(16-n)]2OR(8),4[OR(n),OR(16-n)]2OR(7),4[OR(n),OR(14-n)]6NOR(3),4XOR(2)2NOR(3),8XOR(2)10XOR(2)2OR(8),2OR(10),2OR(12),2OR(14),2OR(16)8[OR(n),OR(16-n)]16[OR(n),OR(16-n)]48x8—48x14(2)—32x1032 x 8,2(2,2,2)32x6,2(2),[2,4(2)]32 x 4,8(2)48 x 848x12(2)32 x [2,4(2)],632x6

Numberoftermsterms

——————————4

——8———8—842—42—4—842—842———810842—406

6—1062—10

—————310111111————

Outputcells

8 type a8 type a8 type d6 type a6 type a10 type a10 type d4 type a4 type a8 type a4 type h, 4 type m

type c2 type a2 type b, 6 type h2 type a, 6 type /2 type a6 type a2 type b, 6 type h2 type a, 6 type /2 type e, 6 type j4 type h, 4 type m2 type h, 6 type m8 type m4 type j, 4 type o2 type j, 6 type o8 type o4 type h, 4 type m4 type a2 type b, 6 type h4 type h, 4 type m2 type h, 6 type m8 type m2 type b, 6 type h4 type h, 4 type m2 type h, 6 type m8 type mtype c2 type a2 type b, 6 type h2 type b, 8 type h2 type e. 6 type j4 type h, 4 type m2 type h, 6 type m8 type m10 type k/q6 type j, 4 type o

2 type j, 8 type o10 type o2 type e, 8 type j6 type h, 4 type m2 type h, 8 type m10 type m10 type j/p

2(8 type d/o)4(8 type d/o)8 type d9 type d8 type f, 6 type n12 type j10 type j8 type /, 4 type r6 type y, 6 type r4 type j, 8 type r8 type d6 type f. 6 type n6 type g. 4 type s6 type d

Notes

1,2,3

3334,244,244,241,3,5

63,63,63,673,73,73,7

333

4,11,24

4,11,244,11,24

3,53,53,58,9

10,11,1211,12,13,14151516,1718

17,19,2017,19,2117,19,221516,172315

Notes (continued on facing page.)The part numbers shown are the ones most commonly used.The general model and output cell types are given in Figs. 9 and 10.The AND array is described as (inputs + feedback) x (products).


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Designing with programmable logic