Design of Sequential Adder Design by Using Multiflipflop

8/18/2019 Design of Sequential Adder Design by Using Multiflipflop

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Design of Sequential adder by using

multi bit flip-flop for Power Reduction

Technique


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Abstract

• The consumption of power has become an important issue in modern VLSI

design power consumption can be reduced by replacing some flip-flops

with fewer multi-bit flip-flops

• !ulti-bit flip-flop is one of the methods for cloc" power consumption

reduction This pro#ect focuses on reduction of power using multi-bit

flipflops by cloc" synchroni$ation

•

!erging single bit flip-flops into one multi-bit flip-flop a%oids duplicatein%erters& lowers the total cloc" power consumption and reduces the total

area


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Abstract

• ' combination table which can store the flip-flops that can be merged to

obtain a multi-bit flip-flop

• Ripple carry adder is used as an application for multibit flip-flop (ighest

)*+ bit finding algorithm is used to find the highest * bit from the output of

Ripple carry adder This algorithm chec"s the output of ripple carry adder

in each cycle.

• This proposed algorithm is designed and reali$ed using ,ilin Spartan ./

0P1' and ,ilin IS/ software for hardware implementation and analysis

the cloc" power consumption of single&two&four and eight bit flipflop

indi%idually


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234/5TIV/S

• To implement the sequential 6 bit ripple carry adder by using multi bit flip-

flop based highest *+s bit algorithm and to reduced the 0lip-flop cloc"

power& delay and area


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LITERATURE SURVEY TITL/ 72R8 D29/ DIS'DV'9T'1/

:*;

In-Placement 5loc"-Tree'ware !ulti-3it 0lip-0lop1eneration for Power2ptimi$ation

This paper introduces a no%el placement flow with cloc"-treeaware flip-flop merging and!300 generation& and proposes the correspondingalgorithms to simultaneouslyminimi$e flip-flop power andcloc" latency when applying!300s during placement

This paper minimi$e the 0lip-0lop power and 5loc"latency when applying!ulti-0lip-0lop only during placement

:


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TITL/ 72R8 D29/ DIS'DV'9T'1/

:.;

' 9oble Research on toReduce 5loc" Power by =sing

!ulti 3it 0lip 0lops

The multi bit flip-flop techniqueis one of the techniques used to

reduce the cloc" power The power reduction isachie%ed through the merging offlip-flops based on certain timingconstraints

This paper designed the single bit flip-flop to multi bit flip-

flop transformation but theyare not implemented anyLogic circuits for analysis performance

:>; ' Reduced 5loc"-Swing0lip-0lop ?R5S00@ for A.BPower Reduction

This paper introduces anR5S00 can reduce the cloc"

system power of a VLSI downto one-third compared to thecon%entional flip-flop and it canreduced area& delay and power

This paper reduce cloc" power&area and delay based on R5S003ut further more reduced thecloc" power& area and delay byusing multi bit flip-flopbut theyare not used multi bit flip-flop


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TITL/ 72R8 D29/ DIS'DV'9T'1/

:C; (alf VDD 5loc"-Swing0lip-0lop with Reduced5ontention for up to AB PowerSa%ing in 5loc" Distribution

This paper introduces a newlow cloc" swing flip-flop ?0E0@is proposed to reducedarea&cloc" &power and delay

This paper reduce the area&cloc" power and delay 3ut theyare also only used single bitflipflop 3ut they are notused the multi bit flipflop 3ut if it is used means futherreduced the area&power anddelay


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/,ISIT91 SFST/!

• In eisting system& they are only designed the !ultibit 0lipflop to reduced

the duplicate in%erter compared from single bit flip-flop

• To 'nalysis and compared the single bit and multi bit flip-flop power

consumption


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Disad%antage of /isting system

• In eisting system& only designed the transformation of single bit andmulti bit flip-flop design and combination table and not implemented any

digital logic circuits

• This multi bit flipflop is not implemented / tested in 0P1'


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Proposed System• In the proposed wor" used D-00 this ma"es low power when compared to other 00

and the output will be easy to processed 'fter finding that number the particular

bits of 00 storage is getting enabled and remaining will be in sleep mode It reduces

the power consumption and wire length for the !300

• Depends upon the 00 storage enabled The combination table is selected for 00

selection :below Fig shows the single bit flipflop to multi bit flipflop

transformation;

• To analysis the clock power and area consumption of single& two& four and eight

bit flipflop based adder design


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3loc" Diagram


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'ddition 7a%eform


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Power consumption in Singlebit 0lip-

0lop


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Power consumption in Twobit 0lip-

0lop


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Power consumption in 0our bit 0lip-

0lop


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Power consumption in /ight bit 0lip-

0lop


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Switch Interface with FPGA


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• The abo%e diagram shows interfacing switch with 0P1' board

• (ere one end of the switch is connected with supply and

another end connected with ground as well as 0P1' board

• If we push the switch to high )*+ will be display on the L5D

module and if we push switch to low means )+ will be display

• This eight switches are used to gi%e the input for the addition


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LED Interface with FPGA


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• The abo%e figure shows the 0P1' interfacing with L/Ds and these L/Ds

are used to find the added output

• 2ne end of the L/D connected with 0P1' and another end connected with

resistor

•

If the high %alue ?)*+@ comes to L/D means light will glow otherwise ?)+@it will not glow


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LCD Interface with FPGA


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• The abo%e diagram shows the interfacing L5D module with 0P1' board

• Typically L5D module has three control terminal and eight data terminal

• The three control terminals are /9&RE7 and RS and these are used to

control the L5D module

• This L5D module used to shows the added %alue as well as find the

selection of flip flop


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Working of hardware

• In the hardware section we ha%e two eight bit switches& these switches are

used to gi%e the input to the adder

• The addition process ta"es place in 0P1' board

• Then the added output shows in L5D module and L/Ds

• The L5D module shows the output according to the highest )*+ bit

algorithm


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Working of proposed systemin hardware

• Step * G 1i%e 6 bit input through the 6 switch connected with 0P1' board

• Step < G 1i%e another 6 bit input through the 6 switch connected with

0P1' board

• Step . G The addition operation is done by 0P1' c.s*e

• Step > G The result can %iew in L5D module and also onboard L/D light


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Working of proposed systemin hardware !"

• Step C G If the !S3 of output is binary )*+ means the !S3 will be stored

in single bit 00 and other 6 bit result will be stored in 6 bit 00

• Step A G If the fourth bit of the output is )*+ and before the fourth bit all )+

means > bit %alue only stored in > bit 00

• Strep H G Similarly for all case


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'd%antage of proposed system

• In proposed system& The multibit flipflop is implemented with adder logic

circuit with the concept of highest *+s bit algorithm and combination table

function

• The adder logic circuit is implemented in ,ilin 0P1' and analysis the

cloc" power and area consumption of the logic circuit


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Conclusion

In this paper& we ha%e introduced a new placement flow with cloc"-tree aware flip-

flop merging and !300 generation 7e ha%e also proposed the corresponding

algorithms to simultaneously minimi$e power and cloc" latency when applying

!300s during placement and we also designed multiple bit 0lip-0lop up to eight

bit and we are used that 0lip-0lop for storing the output of eight bit adder 7e ha%e

showed the power comparison for single bit& two bit& four bit and eight bit 0lip-0lop

with eight bit adder using ,ilin *i software 0inally we ha%e implemented this

adder in Spartan - ./ 0P1' board


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Reference

• =sing multi-bit flip-flop for cloc" power sa%ing by Design 5ompiler

• 'utomatic register ban"ing for low power cloc" trees

• ' reduced cloc"-swing flip-flop

• /ffecti%e and /fficient 'pproach for Power Reduction by =sing !ulti-3it

0lip-0lops

• Power-dri%en flip-flop merging and relocation

• =sing multibit register inference to sa%e area and power


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Than" Fou

Documents

Design of Sequential Adder Design by Using Multiflipflop