Laboratory of Integrated Systems Design

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Laboratory of Integrated Systems Design

Department of Electronics

AGH University of Science and Technology in Cracow

Task 1

Design of NAND or NOR gate optimisation of voltage transfer characteristics

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1. Purpose

Familiarizing students with the work of basic CMOS gates. Understanding the influence of the

way of transistors switching and theirs dimensions on voltage-transfer characteristics (VTC) of the

gate. Acquiring the ability to perform parametric simulations. Semi-automatic generation of a

layout.

2. Task

Draw a schematic diagram of a two-input NAND or NOR gate. Perform a simulation

confirming the correct work of the gate (e.g. transient analysis).

Perform a simulation to plot voltage-transfer characteristics of the gate. Using the

parametric analysis, choose the size of the transistors (width) to obtain the largest possible

gate noise margins

Draw a layout using the semi-automatic method. Keep the smallest dimensions of the layers

and the space between them (possibly expand those layers that you need but do not increase

the dimensions of the whole gate, e.g. power lines).

Extract the netlist from the layout with parasitic parameters: R and C. Perform post-layout

simulations to determine voltage-transfer characteristics and time parameters (propagation

time, rise and fall time of the output signal) and average power consumption when loading

the gate with a capacitance of 10 fF.

3. Result

Present the final layout to check by the teacher.

Write a short report containing: aim of the project and the results of pre-layout and post-

layout simulations, i.e. obtained gate parameters: the gate switching threshold, noise

margins, delay and edges times, average power consumption, dimensions and area. Please

remember to give the conditions the gate simulations (load capacitance, signal frequency,

etc.). It is not advisable to place the topography in the report, but it is necessary to specify

the path and name of the library where the final version of the project exist in your account.

The report can be sent by e-mail, entering the subject of the letter:

ICS_task1_name_surname.

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4. Realization of the task – useful information

4.1. Initial settings and the gate schematic diagram

You can create a new directory for the first task or, if you want, you can work in the existing

design directory. But necessarily create a new library when you use later case. Of course, in the new

directory you need to prepare the environment – umc_180_setup. Do not use this commend if you

work in the old directory. In the Library Manager, you must create a library, cell and view of

schematic, in the same way as in the case of the inverter. Now, we proceed to draw the schematic of

the selected gate. Transistors taken from the library can have the minimum dimensions for this

technology. Next, a simulation should be performed that confirms the correctness of the schematic

and proper work of the gate (e.g. transient analysis). This can be done similarly to the inverter.

4.2. Schematic diagrams for voltage-transfer characteristics simulations

The second stage is to prepare a schematic for simulation of gate voltage-transfer characteristics,

i.e. DC analysis (.dc). The parameters, which can be determined from these characteristics, are the

gate threshold voltage (switching) and the noise margins. Since the voltage transfer curve has no

"vertical" slope, the switching voltage can be defined as the input voltage for which the output

voltage takes the value of half of the supply voltage. Additionally, you can designate a maximum

value of input voltage for "0" (VIL) and minimum value for "1" (VIH). Based on them, a noise

margins can be calculated.

Noise margins definition says, that:

low noise margin: OLILL VVM

high noise margin: IHOHH VVM

Values of voltages are defined below in Fig. 1. Points A and B are determined when slope of the

curve is –1 (in other words: dVout /dVin = – 1).

Fig.1. Voltage-transfer characteristic for an inverter – the method of noise margins determining

In contrast to the inverter for multi-input gates, it is necessary to examine all possible ways of

gate control, i.e. for example for a two-input NOR gate with AB inputs, we will have cases:

(1) A = 0, B = , (2) A = , B = 0, (3) A = , B = (the arrows denote a change of a signal – edge).

In consequence we obtain three curves. Since the characteristics for different ways of gate control

do not cover between each other, hence extreme cases should be selected to determine the VIL and

VIH voltages, which are needed to calculate the noise margins. However, you need to modify the

schematic three times to get all the curves.

Another way to obtain all curves on one chart is to draw three measurement schematic diagrams

on one sheet for all ways of switching the gate. It is enough to use one input source, which should

be properly connected to all gates ensuring three driving ways. Choosing the output signals we will

get three voltage transfer curves on one graph. From the extreme curves we will calculate the noise

margins.

A

B

Vout

Vin

VOH

VOL

VIH VIL

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4.3. Parametric simulations and transistors width selection

The main purpose of this task is such selection of transistors width in order to put voltage-

transfer characteristics as close as possible to a half of supply voltage – in the middle of the graph.

The job can be simplified to search for the width of PMOS transistors (assuming NMOS minimal)

so that the average threshold switching voltages for extreme characteristic cases is equal to half the

supply voltage (Fig. 2).

Fig.2. Voltage-transfer characteristics for different driving ways of a gate shifted into the middle of the graph

In the case of NAND gates with a larger number of inputs, it may happen that the NMOS

transistors will have to be widening due to their serial connection, but PMOSs remain minimal.

In order to search for the optimal dimensions of transistors, it is possible to perform parametric,

sweep DC analysis instead of repeated simulations followed by transistors width changes. Below is

a description of example settings that allow simulating voltage-transfer characteristics of NAND

gate:

Parametric Analysis in ADE L:

Instead of the value of a specific parameter, which we want to change in subsequent

analyzes, enter the name of the parameter (e.g. szer):

Vout

Vin

Vdd

½ Vdd

Vdd½ Vdd

½

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Next from menu Launch choose command ADE L, which starts the window controlling

simulations.

Click the button Choose Analyses and choose dc analysis, select Component

Parameter and click Select Component:

On the schematic diagram choose an element, which parameter you want to select to

control the simulation (e.g. input voltage source), and in the window Select Component

Parameter select dc and confirm (OK):

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After returning to the previous window, set the range and step of changes of the selected

parameter. Below is a window with all parameters set:

Next in the ADE window, after pushing of the button Setup Outputs you can

choose voltages to display.

You must also select variables. Push button Edit Variables . And the window

Edit Design Variables opens, in which click Copy From. It will copy the variables

from the simulation schematic (there in transistors parameters our parameter "szer" was

put). In the field Value write down default value of the parameter (e.g. min. width of

transistors– 240 nm) and click button Change. Final result should be as below.

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In the ADE window all needed parameters will be completed:

It is also necessary to select the parameter, which should change during the analysis. In

our case we have one our parameter ("szer") and of course another, default – the

temperature. From ADE window choose Tools → Parametric Analysis …

In window Parametric Analysis from pull-down menu choose our variable ("szer") and

in proper fields write down start, end values and number of steps.

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Now, only remains to run of the simulations:

Observation and analysis of simulations results

Results of parametric analysis will be a set of voltage-transfer characteristics of the gate:

For voltages values determination you can use marker, which is invoked by the button

Create Marker . A window for its parameters editing will opened. In the window

requested values for X and Y axis can be set. In our case a half of voltage supply should

be written for Y axis.

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On the graph a marker appears in selected place. After hovering over the dotted marker

line, there will be shown balloons with voltage values for each intersection of the

characteristics with the marker.

Another usable function in Virtuoso Visualization is possibility to hide curves on the

graph. Just press the "eye" in the left panel with the description of the waveforms.

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4.4. Semi-automatic layout generation

In the Cadence IC Design program it is possible to generate a layout components based on the

schematic diagram. Layouts of library elements used in the schematic will be used.

Open previously drawn schematic or draw a new using Schematics XL. In the Library

Manager, press the right mouse button on the selected scheme and select Open With.

After that a window will open allowing you to select the application to open the file.

The window with the schematic will now look a bit different than previously:

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From menu Lunch choose Layout GXL. The window with options selection appears:

Next window is for a new layout creation:

After set appropriate values in the window, next for layout drawing will open. And a

desk will be organized as follows:

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Now we can start to generate layout based on the schematic. From the Virtuoso Layout

GXL menu choose: Connectivity → Generate → All From Source.

The window opens, which will allow to setting parameters of the generated layout:

In the window above, we define the type of layers for pins and labels properties. In the

field Pin Label push Options, an following window will appear:

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After setting proper values and approval of previous windows, generated layout will

appear. It is not complete layout but only layouts of used cells, which must be properly

placed and connected.

The layout editor has some facilities. For instance, choosing from menu Connectivity →

Incomplete Nets → Show/Hide Selected we can turn on showing of interconnection,

which have to be done.

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However, in order to make visible the lines showing the points to be connected (nets),

they must be turned on in Display Options.

Results will be similar to shown below:

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When drawing a layout, contacts and vias often have to be made. In the Virtuoso Layout

editor, it is possible to automatically generate these structures. For this purpose choose

Create → Via (shortcut o).

A window opens, which allow defining type of contact/via (Via Definition), theirs

number (Rows, Columns), and mode: Single, Stack Auto and other parameters.