Design of LNA at 2.4 GHz Using 0.25 m TechnologyMarco DonadioMSICT RF Communication SoC

PaperDesign of LNA at 2.4 GHz Using 0.25 m Technology:

by Xiaomin Yang, Thomas Wu and John McMackenUniversity of Central Florida, School of E.E.

implementation of 2.4 GHz CMOS low noise amplifier in a 0.25 m technology single ended configuration fully integrated circuit, without off-chip components trade-off Power-supply vs figure of merit

IntroductionWhat is an LNA?A circuit used to provide gain where preserving the signal-to-noise ratio is important

Where can I find one?In wireless/wireline receivers and sensor interfaces

Why ultra-low-power?Want a long battery life for portable/remote applications and implants

PAPERS IMPLEMENTATION Inductive degeneration topology is used to get better noise performance for the narrow band applications. The amplifier has the commonly used cascode architecture wich provide a good isolation between the input and output stages. Ls and Lg are used to make impedence matching at the input, while the output impedence matching can be obtained by tuning the third inductor LD and the capacitor Cout.

Design MethodologyCommon-SourceProblems with common-source- Low device output resistance low gain- Poor input/output isolation InstabilityCascodeCascode Design: Lg, Ls, Ld, Cm, Ctune, VB, VGS1, W1/L1, W2/L2

Lg

RFin

Ls

VDD

Ld

RFout

M1

Cm

Ctune

VDD

Lg

RFin

RFout

Ld

Ls

VB

M1

M2

Cm

Ctune

Papers Implementation

0.25 m technology 3.3 V supply gain about 15 dB noise figure of 2.2 dB power dissipation of 7.2 mWLNA specification

S11 = -17 dB S12 = -24 dB S21 = 15 dB S22 = -23 dB IIP3 = 1.3 dBm

PAPERS IMPLEMENTATIONDESIGN OF THE LNABoth the input and the output impedence are required to be 50 .The first step is to determine the MOS transistor size in the input stage; the optimum device width for the authors is 200 m to minimize noise figure.INPUT MATCHInput impedence is calculated as:

where R1 is the series resistance of the gate of inductor and Rg is the gate resistance of the NMOS transistor M1.

where R is the sheet resistance of the poly silicon, W is the total width of the device, L is the gate length and n is the number of gate fingers used to lay out the deviceLs is determined

PAPERS IMPLEMENTATIONDESIGN OF THE LNAAt the central frequency 2.4 GHz, the imaginary term of Zin will be zero, wich gives:From this equation, Lg is solved

MY IMPLEMENTATIONStep1: MOS transistor technology featuresCTH technology (0.25 m)

MY IMPLEMENTATIONStep2: Impedence matching (design Lg, Ls value to create a 50 input impedence)Choose a small value of Ls (1.4nH) because it can be realized as a integrated inductor.Find the unity gain frequency gm/Cgs = T = 3.57e10 sec^-1 from the condition :Small-signal model

+

-

Ls

Cgs1

Lg

Rs

RF

gmVgs

Vgs

Zin

Cm

VDD

Lg

RFin

RFout

Ld

Ls

VB

M1

M2

Cm

Ctune

MY IMPLEMENTATIONStep3: Optimal transistor size 3. Knowing transistor paramiters alpha, delta and gamma I found the parameter p = 2.253 and the optimal value of QL = 1.2 from:

4. Using the value of operating frequency 0 I computed = 1.6nH

5. Finally I found the optimal value for the device width

where = 1.467e-12 F

MY IMPLEMENTATIONConsiderations about optimal W W = 840 mbig transistor size, that means high power consumptionIn the papers implementation W = 200 m

Transistor Sizing for NoiseNF of LNA improves with larger WHowever, power proportional to W Noise-power tradeoff

W [m]NFLNA [dB]CascodeCommon-Source

MY IMPLEMENTATIONFinal Design of LNA

Simulations and resultsS12 S21 ParametersGain at 2.4 GHz is 21.5 dBReverse isolation gain is - 42.5 dB

Simulations and resultsInput Matching S11 ParameterInput matching at 2.4 GHz is -12 dBThe initial value for S11 was about 7 dB, playing with Lg value I provided 12 dB (optimizer tool).

Simulations and resultsOutput Matching S22 ParameterThis value of S22 is obtained adding buffer stage at to output; without this stage output matching value was too bad, about -3 dB. Output matching at 2.4 GHz is

Simulations and resultsNoise Figure ParameterNoise Figure is very good (1 dB)This is intuitive because high power consumption (big W value)!!!!!!!

Simulations and resultsIntermodulation Distortion IIP3Distortion is measured by applying two pure sinusoids with frequencies well within the bandwidth of the circuit (f1 and f2). The harmonics of these two frequencies would be outside the bandwidth of the circuit, however there are distortion products that fall at the frequencies 2f1 f2, 2f2 f1, 3f1 2f2, 3f2 2f1, etc.

Simulations and results1dB Compression Point1 dB compression point is the point at which the actual gain is 1 dB below the ideal linear gain

Simulations and resultsPower Consumption23 mW

ConclusionsComparison between paper and our implementation:Input matchingmy S11= -15 dB vs papers S11 = -17 dB acceptable Output matchingmy S22= -14.7 dB vs papers S11 = -23 dB Bad Gain and revers isolationmy S21= -21.5 dB vs papers S21 = -15 dB GOOD my S12 = -42.5 dB vs papers S12 = -24 dB acceptable Noise figuremy NF = 1 dB vs papers NF = 2.2 dB GOOD Power Consumptionmy PC = 23 mW vs papers PC = 7.2 mW TOO BAD !!!

Future ImprovementsOutput Matching:- Implement a new output matching network in order to achieve the S22 required.

Power Consumption:Implement a new LNA with a 1.8 power supply.Use of capacitors in parallel to cascode stage to minimize width of transistors.