Design of Handshake Mode With 8255 Using 8086

7/23/2019 Design of Handshake Mode With 8255 Using 8086

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Homework Title: Design of handshake mode with 8255 using 8086 Course Code: ECE 212

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Handshaking refers to the process of

communicating back and forth between two

Intelligent devices

8255 handles handshaking signals (a

powerful built in features of the 8255)

Printers are good example for a device

with handshaking capabilities

PRINTER HANDSHAKING SIGNALS

1. A byte of data is presented to the data bus

of the printer.

2. The printer is informed of the presence of

a byte of data to be printed by activating its

STROBE input signal.

3. Whenever the printer receives the data it

informs the sender by activating an outputsignal called ACK(acknowledge).

4. The ACKsignal initiates the process of

providing another byte of data to the printer.

Example printer interface

From the data segment:

MYDATA DB Ceva", CR, LF, "$"

PA EQU 300H ;port APB EQU 301H ;port B

PC EQU 302H ;port C

CWP EQU 303H ;control word

LF EQU OAH ;line feed

CR EQU ODH ;carriage return

From the code segment:

;control word PA=out mode 1

MOV AL, 10100000B

MOV DX, CWP

;issue control word

OUT DX, AL

;PC6= 1 for INTEa

MOV AL, 00001101 B

; using BSR mode

MOV DX, PC

OUT DX, AL

;SI = data address

MOV SI, OFFSET MYDATA

Print the string using Polling

AGAIN:

MOV AH,[SI] ;get a character

CMP AH,'$' ;is it the end?

JZ OVER ;if yes, exit

MOV DX,PC ;DX=302 port C address

BACK:

IN AL,DX ;get status byte from port C

AND AL,08 ;is INTRa high?


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JZ BACK ;if no, keep checking

MOV DX,PA ; if yes, make DX=300 data

port

MOV AL,AH ;addressand

OUT DX,AL ;send char to printer

INC SI ;increment the data pointer

JMP AGAIN ;keep doing it

OVER: ... ;go back to DOS

8255 mode :

The 8255A is a widely used, programmable,

parallel I/O device.It can be

programmed to transfer data under various

conditions, from simple I/O to interrupt I/O.

It reduces the external logic normally

needed to interface peripheral devices. The

8255A/82C55A replaces a significant

percentage of the logic required to support a

variety of byte oriented input/output

interfaces.

it has 2 versions :

INTEL8255

INTEL 8255A-5

There are some differences in their electrical

characteristics.its main function are to

interface peripheral devices to the

microcomputer.it has three 8 bit ports

namely

Port a

Port b

Port c

o Port c upper

o Port c lower

operating modes of 8255A PPI :

Two 8-bit ports (A and B)

Two 4-bit ports (Cu and CL0

Data bus buffer

Control logic

The intel 8255 has the following 3 modes of

operations which are selected by software :

Mode 0-simply i/o

Mode1- strobed i/o

Mode2 bidirectional

The 8255 has two 8 bit ports and two 4 bit

ports. The RD#, WR#, A0 and A1 (Port

Select 0 and Port Select 1) signals are input

into the device. The Read/Write Control

Logic issues control words to the device

Group A and Group B Controls. The Group

A and Group B Controls, in turn, issue

commands to the associated ports. The

Control Groups are defined as:


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Control Group A: Port A and Port C upper

(C7-C4).

Control Group B: Port B and Port C lower

(C3-C0).

The specifications for the peripheral device

are examined to determine the control and

data signals which must be supported by the

8255A/82C55A. The 8255A/82C55A is then

programmed to provide the correct I/O and

data paths.

input/output feature in Mode 0 for the8255A PPI :

_ Outputs are latched

_ Inputs are not latched

_ Ports do not have handshake or interrupt

capability

output control signals used in 8255A PPI

OBF _output Buffer Full

ACK _Acknowledge

INTR _Interrupt request

INTE _Interrupt Enable

MODE1: INPUT PROTS WITH

HANDSHAKING SIGNALS

The 8255 can be programmed to receive

data through ports A and B using

handshaking signals through port C

MODE 1

Simple I/O with handshaking capabilities

Ports A and B can be used as input or

output ports with handshaking capabilities Handshaking signals are provided by the

bits of port C (the device provides the

handshaking

Signals)

MODE 2

Bidirectional port A with handshaking

capabilities

Port A can be used as a bidirectional I/O

port with handshaking capabilities whose

signals are

Provided by port C. (the device provides the

handshaking signals)


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A - mode 2 and B - mode 1 input

Mode 2 timing diagram

BSR (BIT SET/RESET) MODE

A unique feature of port C is that the bits

can be controlled individually. BSR mode

allows one to set too high or low any of PC0

to PC7 as shown in Figure below.

EXAMPLE:

Program PC4 of the 8255 in the following

Figure to generate a pulse of 50 ms with

50% duty cycle.


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SOLUTION:

To program the 8255 in BSR mode,

bit D7 of the control word must be low.

For PC4 to be high, we need a control

word of 0xxx1001".

Likewise, for low we would need

0xxx1000" as the control word.

The x's are for "don't care" and generally

are set to zero.

MVI A,09H ; load the control byte (PC4=1)

OUT 93H ;set PC4 to high, sent to control

reg

CALL DELAY ;time for the high part of

pulse

MVI A,08H ;load the control byte (PC4=0)

OUT 93H ;set PC4 to low, sent to control

reg

CALL DELAY ;time for the low part of

pulse

The signals are as follows:

From the figure:

A and B are configured as input

ports

PORT A uses upper three signals

PC3, PC4 and PC5.

PORT B uses lower three signals

PC0, PC1 and PC2.

STB STORBE

Active-low input signal.


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When an external peripheral device

provides a byte of the data to an input port

(A or B), it informs the 8255 through the

STB pin that PERIPHERAL HAS

TRANSMITTED and it can load (latch in)

the data into its internal register

This signal goes low (active), stays low for

a time, and goes back high. The amount of

time it stays low depends on the device.

The 8255 in response to strobe generates

IBF and INTR

IBF (INPUT BUFFER FULL)

Active-high output signal.

In response to STB, the 8255 latches into

its internal register the data present at PA0-

PA7 or PB0-PB7, and through IBF indicate

that it has latched the data, but it has not

been read by the CPU yet

To get the attention of the CPU to read the

data, IBF activates INTR (sets it high).

INTR (INTRUPT REQUEST)

Active-high output signal to interrupt the

CPU.

If INTE =1 , STB=1, IBF=1

When IBF goes active, INTRis activated

(set to high) to inform the CPU that there is

a byte

Of data in the 8255.

Either an interrupt orpolling the status

word can be used to read the data from port

A or B.

It is only when the CPU reads the data by

activating the RD (going low) signal of the

8255 that INTR becomes inactive (the

falling edge of RD makes INTR go low) The

RD signal from the CPU is of limited

duration and when it goes high, the 8255 in

turn makes IBF inactive by setting it low.

IBF informs the peripheral device that the

byte of data was latched by the 8255 and

transferred to the CPU as well.

By receiving IBF, the external device

knows it can send another byte to the 8255's

port

A or port B.

Then it sets low STB, and the process is

repeated.

Notice that INTR is set to one when all

three signals STB, IBF, and INTE are high.


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OFBA (OUTPUT BUFFER FULL FOR

PORT A)

Active-low signal going out of PC7

Indicate that the CPU has written a byte of

data into port A, so the receiving peripheral

device can read it

OBFa must be connected to STROBE of

the receiving equipment (such as a printer)

ACKA (ACKNOWLEDGE PORT A)

Active-low signal (Has limited duration)

Received at PC6 of the 8255

Indicates that the data at port A has been

picked up by the receiving device

The 8255 in turn makes OBFa high, to

indicate that the data at the port is old data

OBFa will not go low until the CPU writes

a new byte of data to port A.

INTEA (INTRUPT ENABLE FOR

PORT A)

8255 can disable INTRa to prevent it from

interrupting the CPU

INTEa is an internal flip-flop designed to

mask (disable) INTRa

INTEa can be set or reset through port C in

BSR mode since the INTEa flip-flop is

controlled through PC6

INTEb is controlled by PC2 in BSR mode

STATUS WORD

8255 enables monitoring the status of

signals INTR, OBF, and INTE for both ports

A and B

This is done by reading port C into the

accumulator and testing the bits

This feature allows the implementation of

polling

INTRUPTS Vs POLLLING

The CPU services various devices. There are

two ways for the CPU to provide service to

those devices: interrupts and polling.

In the interrupt method, whenever any

device needs its service, the device informs

the CPU by sending it an interrupt signal.

The CPU interrupts whatever it is doing and

serves the request for service.


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In polling, the CPU continuously monitors

a status condition and when the conditions

are met it will perform the service.

The advantage of interrupts is that the CPU

can serve many devices (of course, not all at

the same time). Each device receives service

from the CPU based on the priority assigned

to it. It can also ignore (mask) a device

request for service.

The disadvantage of interrupts is that they

require much more hardware and software.

In contrast, polling is cheap and requires

minimal software, but it ties down the CPU.

To avoid tying down the CPU, interrupts are

the preferred choice

8088 Single Board Microcomputer

System Hardware

The purpose of this document is to brieflydescribe the theory of operation behind the8088 Single Board Microcomputer. Thesystem has been designed to meet thefollowing requirements:

1) A sufficiently large memory (both RAMand ROM)

2) Parallel i/o capabilities

3) Serial i/o capabilities

4) Analog i/o capabilities

5) A maximum mode system

The 8288 is needed to decode the 8088's

status outputs since we are operating the

8088 in maximum mode. In addition to

generating the memory and io-port

read/write signals the 8288 also controls the

bidirectional data bus driver (the 8286) and

the lower address latch chip (the 8282).

Since the upper address lines are not

multiplexed all we need to do is buffer them,

hence the use of the LS244 octal buffer.

Buffering the address and data lines is very

important if future expansion of the system

memory or i/o spaces is desired.

The 8088 CPU runs from an 8284

driven by a 10 MHz crystal.

EPROM: 2764 8K-bytes, E000 to

FFFF

RAM: 6264 8K-bytes, 0000 to 1FFF

PARALLEL I/O: Two 8255's

Analog: port A (00) drives a 1408

DAC

port B (01) reads the 0804 ADC

port C (02) controls the 0804

Control port (03)

Digital port A (20)

port B (21)

port C (22)

Control port (23)

SERIAL I/O: 8251 with 1488/89 line

driver/receivers


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port (40) data

port (41) Control/Status

Since the 8088 will execute its first

instruction starting at address FFFF0

the equivalent address in our system

is FFF0 because we ignore the upper

4 address lines. This address

corresponds to address 1FF0 in the

EPROM and starting at this location

is the following code:

which performs a long jump to the

start of the monitor (EPROM address

100, CS equal to 0E00).

REFERENCES:

1. www.wikipedia.com

2. www.ask.com

3. Book of microprocessor by Gonker

4. Book of microprocessor by B.ram
http://www.wikipedia.com/http://www.ask.com/http://www.wikipedia.com/http://www.ask.com/

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Design of Handshake Mode With 8255 Using 8086