ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 6, Issue 8, August 2017

922

All Rights Reserved © 2017 IJARECE

Abstract— Low-Density Parity-Check codes (LDPC) are

widely using ECC (Error Correcting Codes) for having

eminent capabilities. By using Message Passing Algorithm,

these codes can be decoded. These codes perform better than

Turbo Codes and easily attains Shannon’s limit. For low SNR,

these codes provide low bit error rates. For high SNR, these

codes provide no error floor. These codes are used in various

applications like Wi-Fi, Mobile WiMAX, DVD-S2, and IEEE

802.3 (10 GBASE –T). The main feature of these codes is that

they can provide efficient encoding and decoding. In this

paper, an LDPC encoder and decoder are implemented by

Verilog techniques. For simulation, Xilinx Vivado Design Suite

14.2 and Questasim 10.4c are used. And for synthesis,

Leonardo Spectrum 2014b.4is used. For ASIC Design in

130nm, Mentor Graphics Custom IC Design Tool is used and

also these designs are tested on Nexys 4-DDR

XC7A100TCSG324-2L FPGA.

Index Terms—Low Density Parity Check (LDPC), Hard

Decision, Mentor Graphics Custom IC Design Tool, Leonardo

Spectrum, FPGA.

I. INTRODUCTION

In 1960, Gallager proposed LDPC (Low density parity

check) codes, which are similar to linear block codes. At that

time, these codes are neglected due to its high computational

complexity. In 1981, LDPC codes are generalized into

graphical representation (Bipartite graph or Tanner graph)

by Tanner. In 1990‟s, these codes are again came back by D.

Mackay and R. Neal, who constructed a parity check matrix

with dynamic sparseness. Richardson and Urbanke improved

the parity check matrix to reduce the complexity for faster

encoding and decoding. These code‟s performance is very

close to channel capacity specified by Shannon. In practical

implementation, these codes provides a high degree of

parallelism.

Wireless Communications is one of the prime application for

error correcting codes. Because of the eminent capability,

LDPC codes are being used in various applications like

Wi-Fi, Mobile WiMAX, DVD-S2, and IEEE 802.3 (10

GBASE –T). The standards like DVB-S, 3GPP-LTE uses

Turbo Codes.

Manuscript received Aug, 2017.

Palleti Raju, Dept. of E.C.E, MVGR College of Engineering (A),

Vizianagaram.

Second Author name, Dept. of E.C.E, MVGR College of Engineering (A),

Vizianagaram.

The complexity and throughput of an LDPC decoder depends

on many parameters such as block length, code rate,

processing node complexity, interconnection complexity,

parallelism level and no. of iterations. There is a balance

between the performance of decoder and complexity of

decoding. The parallelism in decoding provide eminent

throughput if properly used.

The flexibility in FPGA is suitable for designing LDPC

decoder rather than in general purpose processor.

II. REPRESENTATION OF LDPC CODES

The representation of LDPC codes can be done either by

using parity-check matrix or by using a Tanner

representation (bipartite graph). In Tanner representation,

there are nodes of two types, Bit node (variable node) is one

and check node is the other. The no. of bit nodes equals to no.

of columns and the no. of check nodes equals to no. of rows in

the matrix H. The connections (edges) between the check

nodes and the bit nodes represents non-zero entities in the

matrix H. A parity check matrix and its graphical

representation is given below.

1) Parity-Check Matrix „H‟

2) Tanner representation of matrix „H‟

Design of an LDPC Decoder using Hard

Decision Algorithm

Palleti Raju, Potnuru Surya Prasad

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 6, Issue 8, August 2017

923

All Rights Reserved © 2017 IJARECE

Fig. 1. The Parity-check matrix „H‟ and its equivalent

graphical representation

In the matrix „H‟, a cycle can be formed by one complete path

through non-zero entries with moves between rows and

columns alternatively. In a tanner graph, a cycle can be

formed by a path starting from a node and ending at the same

node. The number of edges in that path gives the length of the

cycle. The smallest cycle is called as girth. The smallest

possible girth is four. A tanner graph has a minimum cycle of

length four and has even cycle lengths.

III. CLASSIFICATION

LDPC codes are having two classes, Regular LDPC is one

and Irregular LDPC is the other. If the weight of each column

and each row are constant then the codes are called regular

LDPC codes. If the weight of each column and each row are

different then the codes are called irregular LDPC codes.

IV. ENCODING PROCESS

To encode the LDPC codes, first the matrix „H‟ should be

transformed as given below.

The above form of parity check matrix is obtained by

performing Gaussian elimination method [7]. In this

method, only row operations should be used. The addition of

two rows should be modulo-2 addition. This parity check

matrix can also be obtained by performing row swaps and

column swaps on it. Here, „ ‟ represents a parity

matrix and „ ‟ represents an identity matrix.

By using the matrix , Generator matrix „G‟ can be

obtained which is of the form

Now, the encoding of the information bits or message bits is

done by the following form

Here, „C‟ represents the codeword of size N, „u‟ is the

message vector of size K and „G‟ is the generator matrix.

This codeword is the encoded message that is modulated

using BPSK in which {0, 1} {-1, 1} transformation occurs

and transmitted over AWGN channel.

V. DECODING PROCESS

In this paper, Bit Flip algorithm is used to decode LDPC

codes. Bit Flip algorithm is known as Hard decision

algorithm.

The steps involved in the Bit Flip algorithm are as follows

Step 1: Initialization

In this step, the received codeword is assigned to the

corresponding variable nodes. These assigned values are

passed as messages from variable node to check node.

Step2: Check Node Update

In this step, each check node checks the parity check

equation associated with it from the variable node messages.

If the parity check equation is satisfied then its send „0‟ value

otherwise „1‟ value to variable node. If all forms of the

parity-check equations are get satisfied, the termination of

the algorithm will occur.

Step 3: Variable Node Update

In this step, each variable node gets a value from check

nodes. Now each variable node decides that the original

received bit is correct or not by majority voting from check

nodes. If majority of votes are different from the original

received bit then that the bit will be flipped and update its

value.

This updated value will be send as a message to the check

node. After this, step 2 and step 3 are repeated until the

parity-check equations are get satisfied (or) until it reach the

count of iterations specified.

Algorithm Bit-flipping Decoding

1: Procedure decode(r)

2:

3: i = 0 Initialization

4: for i = 1 : n do

5: Mi = ri

6: end for

7:

8: repeat

9: for j = 1 : m do Step 1: Check messages

10: for i = 1 : n do

11:

12: end for

13: end for

14:

15: for i = 1 : n do Step 2: Bit messages

16: if the message disagree with ri then

17: Mi = ( ri + 1 mod 2)

18: end if

19: end for

20:

21: for j = 1 : m do Test: are the parity check

equations are satisfied

22:

23: end for

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 6, Issue 8, August 2017

924

All Rights Reserved © 2017 IJARECE

24: if all Lj = 0 or I = Imax then

25: Finished

26: else

27: I = I + 1

28: end if

29: until Finished

30: end procedure

VI. RESULTS

LDPC encoder and decoder are designed in Verilog HDL

language using Xilinx Vivado Design Suite 14.2 and HDL

Designer 2015.1a. These designs are simulated by using

Xilinx Vivado Design Suite and Questasim. The simulation

results are given below.

Fig. 3. Simulation results of LDPC Encoder

In the above figure, when the reset becomes high, the

encoded output becomes low. When the reset becomes low,

the message 00110111 is encoded as 0011011100110010.

The encoded output will be different for different messages.

Fig. 4. Simulation results of LDPC Decoder

In the above figure, when the reset becomes high, the

decoded output becomes low. When the reset becomes low,

the received codeword 0011011100010010 is decoded as

0011011100110010. In the received codeword, there is an

error at the 11th bit which is decoded by using Bit Flipping

algorithm.

To get ASIC Model of design, the designs should be

synthesized to get the netlist file. In this paper, to synthesize

the designs, Xilinx Vivado Design Suite and Leonardo

Spectrum are used. The netlist obtained by using Xilinx

vivado is dumped into the FPGA to see the performance of

the designs. The netlist obtained by using Leonardo

Spectrum is used to generate ASIC model of the design. RTL

and Synthesized designs of the designs obtained by using

Xilinx Vivado Design Suite are shown in fig 5, 6, 7, 8. RTL

and Gate Level designs of the designs obtained by using

Leonardo Spectrum are shown in fig 9, 10, 11, 12.

Fig. 5. RTL Design of LDPC Encoder in Xilinx

Fig. 6. RTL design of LDPC Decoder in Xilinx

Fig. 7. Synthesized Design of LDPC Encoder in Xilinx

Fig. 8. Synthesized Design of LDPC Decoder in Xilinx

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 6, Issue 8, August 2017

925

All Rights Reserved © 2017 IJARECE

Fig. 9. RTL Design of LDPC Encoder in Leonardo Spectrum

Fig. 10. RTL Design of LDPC Decoder in Leonardo

Spectrum

Fig. 11. Gate Level Design of LDPC Encoder in Leonardo

Spectrum

Fig. 12. Gate Level Design of LDPC Decoder in Leonardo

Spectrum

The synthesized designs using Xilinx vivado are dumped

into Nexys 4DDR FPGA. The utilization reports, when the

designs are tested on Nexys 4DDR XC7A100TCSG324-2L

FPGA are given below

Fig. 13. Utilization report of LDPC Encoder

Fig. 14. Utilization report of LDPC Decoder

For ASIC Design of LDPC Decoder, the netlist generated

using Leonardo Spectrum is used. Design of LDPC Decoder

is obtained from netlist file using Mentor Graphics Custom

IC Design Tool is given below.

Fig. 15. Layout of LDPC Decoder in ASIC Design Flow

VII. CONCLUSION

In this paper, LDPC Decoding is done using Bit Flipping

Algorithm. For a regular parity check matrix of 8x16 whose

row weight is 4 and column weight is 2, and having a code

rate of ½, LDPC Encoder and Decoder are designed by using

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 6, Issue 8, August 2017

926

All Rights Reserved © 2017 IJARECE

Verilog technique in Xilinx Vivado Design Suite 14.2 and

HDL Designer 2015.1a. These designs are simulated Using

Xilinx Vivado Design Suite 14.2 and Questasim 10.4c.

These designs are synthesized using Leonardo Spectrum

2014b.4. For ASIC Design in 130nm, Mentor Graphics

Custom IC Design Tool is used and also these designs are

tested on Nexys 4-DDR XC7A100TCSG324-2L FPGA.

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Palleti Raju was born in INDIA in

1993. He received the B. Tech degree in

Electronics and Communication

Engineering from Avanthi institute of

engineering and technology,

Vizianagaram. Currently, he is

pursuing the M. Tech degree with

specialization in VLSI in Maharaj

Vijayaram Gajapathi Raj College of Engineering

(autonomous), Vizianagaram, Andhra Pradesh, India.

Mr. P. Surya Prasad, received his

M. Tech. (Communication and

Radar Engineering) from IIT,

Delhi and B. Tech (ECE) from

JNTU College of Engineering,

Kakinada, Andhra Pradesh and

pursuing Ph. D from JNTU

Kakinada. He is a life member of

IETE, IEI and IACSIT. He has 15 years of teaching

experience and more than 40 publications in

international/national conferences and journals to his credit.

Presently he is working as Associate Professor in the

department of ECE, M.V.G.R. College of Engineering,

Vizianagaram, Andhra Pradesh, India. His research interests

include signal, image/video processing, pattern recognition

and wireless communications.