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Design of a Design of a RestartableRestartable Clock GeneratorClock Generatorfor Use in GALS for Use in GALS SoCsSoCs
HuHu Wang Wang
August 6, 2008 August 6, 2008
IC Design and Research Laboratory
ECE Department Southern Illinois University of Edwardsville
Masters Thesis Defense
Design Team
Southern Illinois University EdwardsvilleDr. George EngelHu Wang
Blendics Integrated Circuit Systems, LLCPresident. Jerry Cox
ECE Department Southern Illinois University of Edwardsville
Background
Verification occupies 60% to 80% of the engineering hours expended on the design of complex integrated circuits (ICs).
Module reuse along with elimination of the global verification component of chip design has the potential to cut the design time of future ICs.
Develop a novel methodology that blends clockless and clocked systems and eliminates the need for global verification. It is a special case of the Globally Asynchronous, Locally Synchronous (GALS) design approach.
ECE Department Southern Illinois University of Edwardsville
Pair of processing elements communicating using clocklesssequencing network
Blended Design methodology
The clock generator serves as a local clock to the data processing subsystem. A clockless sequencing network between the two subsystems to initiate the operation of the data processing subsystem’s local clock, and to signal an acknowledgment of the completion of that action. Avoids synchronizer failures by stopping the clock and then restarting it when data is valid.
ECE Department Southern Illinois University of Edwardsville
A1i
A2i
A1c
A2cClkA PAAAClk B P B A B
FIFOB < = A
FIFOB = > A
B 1 c B 1 i
B 2 i B 2 c
A1i
A2i
A1c
A2cClkA PAAAClk B P B A B
FIFOB < = A
FIFOB = > A
B 1 c B 1 i
B 2 i B 2 c
Clockless sequencing network
Any size clocked domain
Clock Generator
ECE Department Southern Illinois University of Edwardsville
sin ( ) sin cos cos sint u t u t uω ω ω ω ω− = ⋅ − ⋅The operation of the clock generator is based on the simple trigonometric identity,
Clock generator
Constructed from a pair of fully-differential analog multipliers, a comparator, a quad track-and-hold (T/H) circuit, a pair of SRlatches, and an OR gate.
The restartable clock can be stopped and then restarted at an arbitrary phase of the source.
Can be connected to an external crystal oscillator or a local all-silicon, MEMS-based oscillator as input sources.
ECE Department Southern Illinois University of Edwardsville
Initial Analog Multiplier
ECE Department Southern Illinois University of Edwardsville
First presented by Hsiao and Wu in their paper “A parallel structure for CMOS four-quadrant analog multiplier and its application to a 2-GHz RF down-conversion mixer” in 1998.
Consist of six combiners which has a symmetrical structures because they combine the input signals to form the output.
VB is the DC pedestal on which the input signals rest.
Multiplication of two signals, v1 and v2 is achieved through the use of the quarter-square principle shown below
2 21 [( ) ( ) ]4
x y x y x y⋅ = + − −
ECE Department Southern Illinois University of Edwardsville
Initial Analog Multiplier
Original Combiner Design
ECE Department Southern Illinois University of Edwardsville
21 ( )2DS pn n GS TNi K S v Vn
= ⋅ ⋅ ⋅ −
The Square Law characteristic of a MOS transistor
One of the voltage outputs of the “first stage” combiner
2 21 2( ) ( )
2 2out pn n B TN pn n B TN DDR Rv K S V v V K S V v V Vn n− −
= ⋅ ⋅ + − + ⋅ ⋅ + − +
Original combiner circuit
VDD
VGS1
Vout
M1 M2 VGS2
R
The output currents iop and iom
ECE Department Southern Illinois University of Edwardsville
2 2 2[ 2 ( ) 2 ]2
n pnop a b TN a b TN
S Ki v v V v v V
n⋅
= + − ⋅ + +
2 2 2[ 2 ( ) 2 ]2n pn
om c d TN c d TNS K
i v v V v v Vn⋅
= + − ⋅ + +
The differential output current of the multiplier, iout
1 2out multi K v v= ⋅ ⋅
32 24 ( )n pn
mult B TNS K
where K R V Vn
⎡ ⎤⋅⎛ ⎞⎢ ⎥= ⋅ ⋅ −⎜ ⎟⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦
The Output Current of the Multiplier
Improved Analog MultiplierThe real resistor is replaced by a PFET transistor working in resistive region.
Re-written expression of Kmult
By adjusting the control voltage, Vctrl, the resistance can be altered in order that the DC voltage, VR, across device M3 is tuned to the desired value.
ECE Department Southern Illinois University of Edwardsville
( | |)eqpp p DD ctrl TP
nRK S V V V
=⋅ ⋅ − −
22
( )n pnR
multB TN
S KVK
V V n⋅⎛ ⎞⎡ ⎤
= ⎜ ⎟⎢ ⎥ ⎜ ⎟−⎣ ⎦ ⎝ ⎠
Improved combiner circuit
Automatic gain control circuit for resistive PFET
Voltage divider M20 & M21
Symmetric Miller type – Operational
Transconductance Amplifier (OTA)
Negative feedback loop to generate the
control voltage Vctrl
ECE Department Southern Illinois University of Edwardsville
VB
M20
M21
M19
M17 M18
+VDD
VB
Vctrl
OTA+-IB
I Bia
s
Estimated and simulated results in multipliers
ECE Department Southern Illinois University of Edwardsville
Sensitivity Analysis
2 3 2pnout mult TN TN
out mult pn B TN TN
KI K V VRI K R K V V V
ΔΔ Δ ΔΔ= = ⋅ + ⋅ − ⋅ ⋅
−
2pnout mult TN TN
out mult pn B TN TN
KI K V VI K K V V V
ΔΔ Δ ⋅ Δ= = + ⋅
−
For initial multiplier:
For improved multiplier:
ProcessCorners
Initial analog multiplier Improved analog multiplier
Typical 0 0
Best 54% 26% -6.5% 0.5%
Worst -48% -57% 17.6% -3.1%
_
_
out sim
out sim
IIΔ_
_
out est
out est
IIΔ _
_
out est
out est
IIΔ _
_
out sim
out sim
IIΔ
High-Speed Comparator
Current Mirror
High-Speed NFET latch
Self-biased differential amplifier
Push-pull output drivers
ECE Department Southern Illinois University of Edwardsville
Non Ideal Effects
Channel length modulation
Mismatch and offset analysis
ECE Department Southern Illinois University of Edwardsville
Channel length Modulation
The I-V characteristic of a FET does not fit in the ideal
square law.
Factor (1 + λvDS) should be considered. λ represents the channel
length modulation factor which is inversely proportional to the
length of the device, L.
The multiplier gain
ECE Department Southern Illinois University of Edwardsville
21 ( )2DS pn n GS TNi K S v Vn
= ⋅ ⋅ ⋅ −
22
( )[1 ( )]n pnR
multB TN DD R
S KVK
V V V V nλ⋅⎛ ⎞⎡ ⎤
= ⎜ ⎟⎢ ⎥ ⎜ ⎟− + ⋅ −⎣ ⎦ ⎝ ⎠
Comparison of simulation results
If λ is included, the analytical predictions agree closely (within 5%) with the results obtained from electrical simulations.
ECE Department Southern Illinois University of Edwardsville
Mathcad Electrical SimulationWith λ Without λ
Output of the multiplier’s first-stage combiner
IReq 680 μA 604 μA 706 μA
VBO1 0.5 V 0.5 V 0.49 V
Peak-to-peak output Iout 1.49mA 1.59mA 1.53mA
Note: IReq is DC drain-to-source current of PFET M3 in the multiplier’s first-stage combiners.VBO1 is the DC output voltage for the first-stage combiners.Iout is the peak-to-peak differential current transferred to the NMOS latch in the comparator
Mismatch and offset analysis
Random offsets due to mismatch in transistor parameters will result in the clock’s duty cycle differing from the ideal fifty percent.
In fact, if the offset current becomes larger than the peak differential output current, the clock becomes stuck at one logic level.
The standard deviation of the offset current was computed as 15 µA. The 6σ value, 90µA is well below the upper limit of 190 µA which was needed to ensure a reasonable duty cycle for the output clock.
ECE Department Southern Illinois University of Edwardsville
Variance computed at each stageFor NFET in the “first stage” combiner
ECE Department Southern Illinois University of Edwardsville
1
2 2 22 2 2 2 2 2
2 2 2 2 28 ( ) 8 (15 )pn n n
out TN O
K W LI m V V DS
pn n ng I A
K W L
σ σ σσ σ σ μ
⎛ ⎞⎜ ⎟= ⋅ ⋅ + + ⋅ ⋅ + + =⎜ ⎟⎝ ⎠
1
2 2 22 2 2 2 2
1 1 2 2 2 (2.5 )pn n n
DS TN
K W LI m V DS
pn n ng I A
K W L
σ σ σσ σ μ
⎛ ⎞⎜ ⎟= ⋅ + ⋅ + + =⎜ ⎟⎝ ⎠
2 2 222 2 2
2 2 2 2 (4.3 )pp p pTP
eq
K W LVR
SAT pp p pR
V K W L
σ σ σσσ
⎛ ⎞⎜ ⎟= ⋅ + + + = Ω⎜ ⎟⎝ ⎠
( )1 1
22 2 2 2 212 2 (3.8 )
O DS eqV eq I DS RR I mVσ σ σ= + =
For the output of the “first stage” combiner
For the resistive PFET of the “first stage” combiner
For the differential current output delivered to the NMOS latch
Simulation results
VB = 570mV
Amp = 200mV
Freq = 1GHz
Duty cycle ≈ 50%
ECE Department Southern Illinois University of Edwardsville
Simulation result (cont.)
Delay in restarting clock is less than 1.5 ns.
The peak-to-peak variation in the time required to restart the clock is 120 psec.
ECE Department Southern Illinois University of Edwardsville
SummaryThe restartable clock generator is implemented in 90nm CMOS process.
Completely transistor design without resistors existing in the circuit.
Up to 1GHz, clock frequency can be achieved across different process corners.
Only a single 1V supply is required with 10mW power consumption.
The duty cycle of the clock output is near 50%.
The delay in restarting the clock is small, less than 1.5ns.
ECE Department Southern Illinois University of Edwardsville
ConclusionThe restartable clock can be stopped and then restarted at an arbitrary phase of the source, like a delay based clock.
Completely eliminates metastability hazards.
Can be connected to an external crystal oscillator or a local all-silicon, MEMS-based oscillator as input sources.
ECE Department Southern Illinois University of Edwardsville
Further workA small systematic offset should be added into the comparator to ensure that the clock always restart from low to high.
Monte Carlo simulations to confirm the results presented in thesis predicting the likely offset current will be performed in the future.
Efficiently generate the quadrature input signals from an external crystal oscillator or MEMS-based clock.
ECE Department Southern Illinois University of Edwardsville
Acknowledgement
Dr. George Engel, SIUEPresident. Jerry Cox, Blendics, LLCMr. Sasi K. TallapragadaMr. Dinesh DasariMr. Nagendra S. ValluruNSF-STTR and Blendics, LLC
ECE Department Southern Illinois University of Edwardsville
Thank You !
Hu WangGraduate student
Email: [email protected]
IC Design Research LaboratoryElectrical and Computer Engineering Department
Southern Illinois University Edwardsville