Design of a Micro Power Amplifier for

Neural Signal RecordingGhazi BEN HMIDA, Abdennaceur KACHOURI and Hamadi GHARIANI

Laboratory of Electronics and Technology ofInformation (LETt)National Engineers school ofSfax, Electrical Engineering Department. B.P. W, Sfax, Tunisia 3038

ghazi benhmida@yahoo.fr abennaceur.kachouri@enis.rnu.tn hamadi.ghariani@enis.rnu.tn

Abstract- This paper describes a micro power amplifier forneural signal recording. We describe an amplifier using adifferential pair as input stage. Given that neural amplifiersmust include differential input pair to achieve a high common­mode rejection ratio (CMRR). The amplifier has been designedin the AMS 0.35 "m, 3-metal, 2-poly, n-well standard CMOSprocess. The amplifier current consumption is 4.61 "A at %1Vsupply, which gives a power consumption of 9.22 "W. TheCMRR is 113 dB and the power supply rejection ratio (PSRR> 73dB). The input referred noise is 14.8 "Vrms over 100 - 10KHz. The amplifier gives an input DC offset of 196 "V and anoutput swing of ±O.8 V with minimum distortion.

Key words- Neural signal recording, micro power amplifier,low noise, gain, CMRR, DC offset.

I. INTRODUCTION

The human central and/or peripheral nervous system hasbeen a subject of study and fascination of the neuroscienceand biomedical engineering communities for many decades.

The neural signal recording has been an importantresearch issues and is widely considered as key topics forbetter understanding, controlling and eventually restoringneurological functions using implantable microsystems.These ones require a long term simultaneous recording ofneural activity from many neurons simultaneously. Theideal system for long term recording would be a fullyimplantable device which is capable of amplifying theneural signals and transmitting them to the outside world[1], [2], [3].

Extracellular neural action potentials are one of the mostchallenging ones to record. They contain frequencycomponents from 0.1 - 10 kHz and amplitudes in 50 - 500f.lV range [4]. These signals usually carry DC baselines upto 500 mV due to electrode electrolyte interactions. Thelow-level signal amplitude, wide frequency range, and largeDC baseline are the major challenges one would face whendesigning neural recording amplifiers. In addition,robustness of the amplifier in order to guarantee its properoperation in spite of the process and ambient variations is amajor requirement. Further, it would be useful to have arobust amplifier with tunable bandwidth as well as variablegain that could be used for different types of biopotentialsignals or different components in one type of signal [4].

The most critical block in neural recording system is low­power low-noise neural amplifier which is the first stage inthe neural recording system. There have been considerableresearch efforts in the design of low-power low-noise neuralamplifiers in recent years. Harrison et at. described a low­noise low-power single-ended operational transconductanceamplifier (OTA) with capacitive feedback for neuralrecording applications [5].

Although bioamplifiers that retrieve weak bioelectricalsignals have been developed extensively [5]-[11], very fewreported designs meet the noise, power, and sizerequirements for massive integration in implantablemultichannel recording devices. Furthermore, the integrateddesigns that have been proposed give a high CMRR and alow power dissipation for safe permanent usage with anacceptable input referred noise.

The architecture of the neural recording system isdiscussed in Section II followed by the theoretical study ofthe neural amplifier in Section III. Section IV providessimulation results and Section V is the conclusion.

II. NEURAL RECORDING SYSTEM ARCHITECTURE

The block diagram of the neural recording signal is shownin fig. I. It consists of tow units: an implantable transmitterand an external receiver unit. The implantable transmitteracquires neural signals from microelectrode array, amplifies,process and transmits them to external unit wirelesslythrough a miniature antenna. The receiver picks up theneural signal, digitizes it, and transfers it to the PC forfurther signal processing, recording and visualization. Theimplantable part is supplied by power and data via inductivelink, not included in fig.l [12].

I

, ,f i~ i ······ ····;:·,:;~~;:~;~·~~;~ ..·..······· ······1

: jIII

I L .JIII

Skin

Fig. 1. Block diagram of the neural recording signal system

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III. THEORETICAL STUDY C. Neural amplifier circuit analysis

(a)

B. Setting ofequation

(9)

v -v ~ l+k(~ -V)a b 1- k 2 1 (8)

Referring to fig.3, we can express the output voltage Vout

in terms ofthe differential amplifier input;

Fig.3. Schematic of the neural amplifier circuit used in this design

Fig.2 shows the schematic of the neural recordingamplifier which composed of a differential stage and anoutput gain stage.

If k > 1; the structure given by fig.3 works as a hysteresiscomparator.

If k < 1; therefore, it works as a differential amplifier, andfor maximum voltage gain, k must tend to 1, and gmI mustbe very large compared to gmn.

By operating the transistors Ml and M2 in weakinversion, we can simplify the equation (3) to :

1/gm5 gm2.V2gm6.V

gm7.VblIgm4

gm1.V

(b)Fig.2. (a) Circuit differential input stage

(b) Small-signal equivalent circuit

It notes that gmi is the tranconductance of the transistorMi, with i={I, 2 ...7}.

From the small-signal equivalent circuit (see fig.2.(b)), wecalculate;

,.~,Vss

A.Smansignalanarys~

In the small signal analysis, we focus only on the inputdifferential stage. Fig.2 (a) and fig.2 (b) show respectivelythe transistor differential stage and the simplified equivalentdiagram of the differential stage.

1 1~ =-gm2·~·--- gm6·~·-- (2)

gms gms

We obtain a relation between the differential outputvoltage ( ~ - ~ ) and the differential input voltage ( ~ - ~ )

given by:

and

1 1~ =-gml·~·--- gm7·~·--

gm4 gm4

(1)With Rout is the amplifier output resistance, and gmg, gm9

are the respective transconductance of transistors M8 andM9. Following a small-signal study of the output stage, wecalculate the output resistance as follows:

Rout =(rdssgml7rdsl7 ~ l(rdsI2gmlsrdsIS) (10)

Consider the case where gmg = gm9, and from equations(8) and (9), we obtain an output voltage as:

(3)(11)

With

And

gmI =gml =gm2gmII =gm4 =gms

gmIII =gm6 =gm7

k- gmIII _ gm6 _ gm7---------

gmII gm4 gms

(4)

(5)

(6)

(7)

D. Technological specification

In order to realize a low power and low noise amplifier, toamplify neurological signals which have low amplitude(from 50 to 500J-lV). We must respond to technologicalspecifications and requirements listed in Table I.

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TABLE ISPECIFICATIONS AND REQUIREMENTS

Specifications and re uirementsTechnology AMSO.3SumSupply yoltage ±IVGain at least 40 dBGain bandwidth at least I MHzPhase margin at least 600

Power consumption less than 20uACommon Mode Ratio Reiection CMRR at least 80 dBPower Supply Reiection Ratio PSRR at least 60 dBLoad capacitance upper to 7pF

IV. SIMULATION RESULTS

Referring to fig.3 and respecting the specifications and therequirements shown in table 1, we calculate the size ofdifferent devices. Table.2 presents the parameters values ofthe neural recording amplifier.

TABLE IINEURAL AMPLIFIER PARAMETER VALVES

Deyices ValueMI-M2 W=IOOum L=lumM3, MIO, Mil, M12, MI3,

W=I.S!im L=I!imM18,M14M4,MS,M8,M9,MIS,MI6,

W=6!im L=I!imMI7M6-M7 W=Sum L=lumSupply voltage Vdd=IV Vss=-IVLoad capacitance CL=7pFBias current Ibias -luA

By using Pspice, we process to simulate the circuit givenby fig.3. We determine various characteristics such as gain,phase margin, power, noise, CMRR, PSRR, and offset.

• Frequency analysis

We apply an AC source in the input of amplifier given infig.3. The schema in figA is use to draw Bode diagram andto extract its dynamic characteristics.

Fig.4: AC simulation

Fig.5 shows the Bode diagram that gives a gain=43.95 dB(equivalent to 157.57). The phase margin is equal to 64.6°,hence the stability of the system. The gain-bandwidth isGBW = 1.1294MHz.

~

I"';;: I--.t---. I::::::

0

~-....:::

i:'....'00

'\ i"'-.. .....» "-I.O~< ,~,

1!I a p(V(Mle,dl/VIIC?'9JI 0 • D&IVIMl8,dl/VIJC!'~11

Fig.S Simulated transfer function of amplifierMagnitude (dB) and phase (degree)

• Noise analysisThe input-referred noise voltage of CMOS amplifier is

dominated by flicker (lit) noise at low frequencies andthermal/shot noise at higher frequencies. The frequency atwhich the noise tail intersects the noise floor is called theflicker-noise corner frequency. By representing the noisesources of each transistor by a voltage source at its input,the total input-referred noise contribution can be calculatedby considering the voltage gains from the device to theamplifier output.

In order to examine the noise performance of neuralamplifier was simulated using the Pspice. Fig.6 shows theinput-referred noise voltage versus frequency.

,..

\\

'"...~

'----k,~, ,~,

Fig.6 : Simulated input-referred noise voltage [V/sqrt(Hz)]

The Root Mean Square (RMS) of the input-referred noisevoltage: Vni,nns = 14.8 ~Vrms calculated for a frequencyrange 100Hz - 10KHz. This value is competitive comparedwith other developed recording amplifiers reported in theliterature [10], [13].

• Noise Efficiency FactorWe are interested in minimizing noise within a strict

power budget; we must consider the tradeoff between powerand noise. To compare the power-noise tradeoff amongamplifiers, we adopt the noise efficiency factor (NEF)which is widely used to compare neural amplifier designs.The noise efficiency factor is expressed as:

(12)

Where Vni,nns is the total input-referred noise, ltot is thetotal supply current, and BW is the -3 dB bandwidth of theamplifier. Ur is the thermal voltage, KB is the Boltzmannconstant and T is the temperature.

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[1]

[3]

[4]

[7]

REFERENCES

[5]

[6]

[2]

P. Mohseni, K. Najafi, S. 1. Eliades, and X. Wang, "Wirelessmultichannel biopotential recording using an integrated FMtelemetry circuit," IEEE Trans. Neural. Syst. Rehab. Eng., vol. 13,no. 3, pp. 263-271, September 2005.

Nathan M. Neihart, and Reid R. Harrison, "Micropower Circuits forBidirectional Wireless Telemetry in Neural RecordingApplications" IEEE Trans. Biomed. Eng., vol. 52, no. 11, pp. 1950­1959, Nov 2005.

Ming Yin; Ghovanloo, M., "A Clockless Ultra Low-Noise Low­Power Wireless Implantable Neural Recording System", Circuitsand Systems, 2008. ISCAS 2008. IEEE International Symposiumon. Volume, Issue, 18-21. pp.1756-1759, May 2008.

Ming Yin; Ghovanloo, M., "A Low-Noise Preamplifier withAdjustable Gain and Bandwidth for Biopotential RecordingApplications Circuits and Systems", 2007. ISCAS 2007. IEEEInternational Symposium on. Volume, Issue, 27-30 May 2007Page(s):321 324. Digital Object Identifier10.1109IISCAS.2007.378400

R. R. Harrison and C. Charles, "A low-power low-noise CMOSamplifier for neural recording applications," IEEE 1. Solid-StateCircuits, vol. 38, pp. 958 965, June 2003.

1. Parthasarathy et aI., "An Integrated CMOS Bio-potentialAmplifier with a Feed-Forward DC Cancellation Topology," Froc.28rd Annu. IEEE E? vIBS Conf, pp. 29742977,2006.

P.Mosheni and K.Najafi, "A fully integrated neural recordingamplifier with DC input stabilization," IEEE Trans. Bionied. Eng.,vol. 51, pp. 832837, May 2004.

G. E. Perlin, and K. D. Wise, "Neural recording front-end designsfor fully implantable neuroscience applications and neuralprosthetic Microsystems". Proceedings of the 28th IEEE, EMBSAnnual International Conference, New York City, USA, Aug 30­Sept 3, 2006.

Roy H. Olsson III, and Kensall D. Wise, "A Three-DimensionalNeural Recording Microsystem With Implantable DataCompression Circuitry" IEEE Journal of Solid-State Circuits, vol.40, no. 12, pp. 2796-2804, December 2005.

T. Horiuchi, T. Swindell, D. Sander, and P. Abshire, "A low-powerCMOS neural amplifier with amplitude measurements for spikesorting". Froc. IEEE Int. Symp. Circ. Sys., vol. 4, pp.29-32, May2004.

Reid R. Harrison, Paul T. Watkins, Ryan 1. Kier, Robert O.Lovejoy, Daniel 1. Black, Bradley Greger, and Florian Solzbacher,"A Low-Power Integrated Circuit for a Wireless 100 ElectrodeNeural Recording System", IEEE Journal of Solid-State Circuits,vol. 42, no. 1, pp. 123-133, January 2007.

Ghazi BEN HMIDA, Hamadi GHARIANI and Mounir SAMET:"Design of Wireless Power and Data Transmission Circuits forImplantable Biomicrosystem". Biotechnology 6(2): 153-164, 2007.ISSN 1682-296X © 2007 Asian Network for ScientificInformation.

[13] Roy H. Olsson. III, Derek L. Buhl, Anton M. Sirota, GyorgyBuzsaki, and Kensall D. Wise, "Band-Tunable and MultiplexedIntegrated Circuits for Simultaneous Recording and Stimulationwith Microelectrode Arrays", IEEE Transactions on BiomedicalEngineering, vol. 52, no. 7, pp. 1303-1311, July 2005.

[9]

[8]

[11]

[12]

[10]

Parameters ValueGain GdB = 43.95 dB

Phase margin Mq>=64.6°Gain-BandWidth GBW= 1.1294 MHz

Power Consumption Ptot= 9.22 I..lWTotal Current absorbed Itot=4.617 I..lA

Common Mode Rejection CMRR=113.27dBRatio CMRR> 92dB @ f < 10KHz

Power Supply Rejection PSRRYss=73.11dBRatio PSRRydd=75.29dB

Output-voltage swingCMR+=806mV

CMR-=992mVDC Offset 196uV

Input Referred Noise Vni,rms = 14.8 I..lVrmsNoise Efficiency Factor NEF=13,22

IV. CONCLUSION

This paper presents the design of an integrated micro­power amplifier for neural recording signal. The architectureof the neural recording system was discussed and followedby the theoretical study of the neural amplifier.Furthermore, PSpice simulation which using a real transistormodel was presented. In particular, the transfer function ofamplifier and the noise analysis were presented. A powerdissipation of about 9.22 IlW and an input referred noiseabout 14.8fJ.Vrms were achieved. Future work will focus onthe study of closed-loop amplifier with adjustable gain andlow cut off frequency.

TABLE ill

SIMULATED PERFORMANCE CHARACTERISTICS OF NEURAL AJ\.1PLIFIER

• Summary tableTable III summarizes the simulation results of the neural

recording amplifier.

For UT=25mV, T=27°C=300oK, KB=I.3806.10-23 [J/K],Itot=4.617fJ.A, Vni,nns = 1,4888E-05 Vrms and BW= [100Hz,10KHz].

We obtain NEF=13,22 which is competitive comparedwith [7].

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