Design of a high-frequency series capacitor buck converter

Power Supply Design Seminar

Design of a high-frequency series capacitor buck converter

Reproduced from 2016 Texas Instruments Power Supply Design Seminar SEM2200

TI Literature Number: SLUP337 © 2016, 2017 Texas Instruments Incorporated

Power Seminar topics and online power training modules are available at:ti.com/psds

Texas Instruments – 2016/17 Power Supply Design Seminar

Design of a high-frequency series capacitor buck converter

Pradeep Shenoy


Agenda • High-frequency buck converter limitations• Series capacitor buck converter• Sample experimental results• Design of a high-frequency series cap buck

converter

Series cap buck converter prototype

TPS54A20

Series capacitor Inductors

1-2


Power delivery system

Intermediate bus architecture

Point-of-load Voltage Regulators

1-3


Why increase switching frequency? Inductors usually are the largest component.

1) Smaller size

2) Faster response 3) Lower BOM cost

Converter volume: 1,270 mm3 Converter volume: 157 mm3

Inductor volume: 232 mm3 Inductor volume: 19.2 mm3

1-4


Inductor size reduction: 10-A output

High-frequency operation ! 15 times smaller inductors!

500 kHz

2-5 MHz

1-5


High-frequency (HF) buck converter limitations

• High switching loss

• High-side switch on-time is veryshort at HFo 5 MHz ! 200 ns periodo 10-to-1 voltage ratio ! 20 ns high-

side on-time

Buck converter

Switch timing diagram

HF converters on today’s market have low-conversion ratios (<5-to-1) and low current (<1A)

swloss fP ∝

1-6


Series capacitor buck topology •  Benefits

o  Single conversion stage o  Switching at reduced VDS o  Series cap soft charge/discharge o  Automatic current balancing o  Duty ratio doubled

•  Drawbacks o  50% duty cycle limitation

" Theoretical: VIN,MIN = 4×VOUT " Practical: VIN,MIN = 5×VOUT

o  No phase-shedding Two-phase, series cap buck converter

Series capacitor

P.S. Shenoy, M. Amaro, D. Freeman, and J. Morroni, “Comparison of a 12V, 10A, 3MHz buck converter and a series capacitor buck converter,” in Proc. IEEE Applied Power Electron. Conf., pp. 461-468, Mar. 2015.

1-7


Steady-state operation: Interval 1

1-8



1-9



1-10



1-11


Reduction in inductor current ripple

•  Up to 33% reduction in inductor current ripple o Same L, VIN, VOUT, fSW, etc.

•  Benefit: reduces inductor core loss

•  Alternative: reduction in required inductance o Same ΔiL, VIN, VOUT, fSW, etc.

Current ripple ratio:

20

20 Lswpkswcore ifkBfkP Δ∝≈

)/(1)/(21

,

,

INO

INO

BuckL

SCBuckL

VVVV

ii

−−=

ΔΔ

1-13


TI high-frequency controller • Adaptive constant on-time control

o Fast transient response

o Internal compensation

• Frequency synchronization byadapting on-time

o Fixed-frequency in steady state

o External clock or internal oscillator

1-15


Current density comparison

A 3x to 7x improvement in total solution current density

Series cap buck: 1.2 mm high

Conventional buck: 4.8 mm high

IC Inductors

0 10 20 30 40 50 60 70

0 5 10 15 20

Cur

rent

Den

sity

(A/c

m3)

Rated Output Current (A)

TPS54A20

Research

Industry

TPS54A20

(as of Jan 2016)

1-16


Series capacitor selection • Cap is (dis)charged by the inductors• Select the cap value to keep voltage

ripple <8% at full loado Ex: 10 A load, 2 MHz, 12 VIN, 1.2 VO

• Tradeoff: startup delay to prechargethe series capo 10 mA precharge current into 1 µF cap! 625 µs to precharge to 6 V

( )( ) µF04.1

2V1208.0

2A10

MHz21

V12V2.12

208.0

2=

⎟⎠⎞⎜

⎝⎛ ×

=⎟⎠⎞⎜⎝

⎛

⎟⎠⎞⎜⎝

⎛

=in

out

V

iDTC

Precharge

VO

PGOOD

SCAP

EN

1-21


Feedback network selection

Configuration Crossover Frequency Phase Margin

1 188 kHz 36.9 °

2 196 kHz 48.8 °

# Simple -  No phase boost

#  Phase boost -  Less flexibility

#  Flexible phase boost -  More components

#  Noise immunity -  Most components

Example: VIN = 12 V, VOUT = 1.2 V FSW = 2 MHz, IOUT = 4.8 A COUT = 191 µF, L = 250 nH

1 2 3 4

1-23


HotRod™ package

Bottom-up view of TPS54A20

Pin assignments (top-down view)

• HotRod™ QFN package

• Flip-chip design reducesparasitic elements

• Thermal vias placed inPGND strip for heatremoval

"  PCB ground planes act as a heat sink

"  Aids ground return currents 3.5x4 mm

1-24


Board layout tips • Place input cap and series cap

right next to the IC

• Place gate drive and bootstrapcaps close to the IC

• Insert thermal vias on the PGNDstripeo Connects to internal power

ground planeso Improves thermal dissipationo Provides good ground return

pathExample layout diagram

1-25


Where’s the Heat?

Integrated converter

Series capacitor Inductors

Test condition: 12 VIN, 1.2 VOUT, 10 A, 2 MHz/phase, temp measured in °C

Inductors have relatively low loss and not a thermal bottleneck

1-27


Total solution size

10-A series cap buck prototype 16 x 10 x 1.85 mm = 296 mm3

Inductor on 10-A buck EVM 10.2 x 10.2 x 4.7 mm = 489 mm3

The total solution size is 65% smaller in volume than just the inductor on a competitor’s 10-A evaluation module!

1-28


Summary

• High-frequency (HF) operation of switching convertersenables size reduction and performance improvements

• Buck converters have fundamental limitations that limit HFoperation

• The series capacitor buck converter has uniqueproperties that support HF operation

• Design guidelines for an HF series cap buck converterdemonstrate the ease of implementation

1-29


Reduced switching loss

• Reduced switch voltage/current overlap loss

• Loss due to switch outputcapacitance reduced by67%

• Enables higher frequencyoperation

Energy loss per switching cycle

1-12


Auto current sharing

012345

0 2 4 6 8 10Indu

ctor

Cur

rent

(A)

Output Current (A)

ILa

ILb

ILA (1A/div) ILB (1A/div)

Current Sharing: La ≈ 100 nH, Lb ≈ 200 nH

• Series cap forms averagecurrent feedback mechanismo Inductors charge/discharge capo Charge balance maintained

• Robust to variations in L, DCR

P.S. Shenoy, et al., “Automatic current sharing mechanism in the series capacitor buck converter,” in Proc. IEEE Energy

Conversion Conf. Expo., Sept. 2015.

1-14


Measured efficiency comparison

• Conditions: o 12 VIN, 1.2 VOUT

o Room temp, no air flow

• Higher efficiency over the load range

• Inductors selected for equivalent DCR

Higher peak efficiency at ~4 times the switching frequency

70

75

80

85

90

0 2 4 6 8 10

Effic

ienc

y (%

)

Output Current (A)

2MHz, TPS54A20530kHz, TPS54020

1-17


Transient response

• 12 VIN, 1.0 VOUT; 500 A/µs full-load steps; 2 MHz per phase• Deviation in VOUT <25 mV; recovery time <4 µs; FSW changes during transient• Excellent dynamic current sharing

IOUT (5 A/div)

ILA, ILB (2 A/div)

ILA, ILB (2 A/div)

VOUT (20 mV/div)

Load step-up Load step-down

VOUT (20 mV/div)

IOUT (5 A/div) 2 µs/div

2 µs/div

1-18


60

65

70

75

80

85

90

0 2 4 6 8 10

Effic

ienc

y (%

)

Output Current (A)

2MHz3.5MHz5MHz

Choosing the switching frequency • Increasing frequency can reduce

inductance requirement

o Helps reduce converter size

o K = inductor current ripplepercentage

• Tradeoff: efficiency decreases withincreased switching frequency

SWIN

O

O

OIN

fV

V

IK

VVL

(max)

(max)

2

2

12 VIN, 1.2 VO Efficiency Comparison

1-19


Inductor impact on efficiency • Higher inductance tends to

increase peak efficiency o Lower core loss o Lower RMS currents

• Lower inductance has higher full load efficiency o Lower winding resistance o Assumes same inductor size

• Comparison using 3.2x2.5x1.2 mm inductors, same vendor

65

70

75

80

85

90

0 2 4 6 8 10

Effi

cien

cy (%

) Output Current (A)

12 VIN, 1.2 VO , 2 MHz/phase

250nH330nH470nH

1-20


-40-20

0204060

1 10 100 1,000

Mag

nitu

de (d

B)

Frequency (kHz)

Co=91uFCo=138uF

Input and output capacitor selection • The output caps impact

o Steady-state voltage rippleo Closed-loop bandwidtho Load transient performance

• Ex: ΔIO,MAX = 10A, L = 220 nH,Vo = 1.2 V, ΔVO,MAX = 36 mV

• Input cap selected based on allowedvoltage rippleo Steady-state rippleo Deviation during a load transient

219 kHz 319 kHz

Bode plot: 12 VIN, 1.2 VOUT

μF127)V036.0)(V2.1(4

nH220)A10(4

)( 2

max,

2max,

min,

oo

o

oVV

LIC

0

50

100

150

200

1 10 100 1,000

Phas

e (d

egre

es)

Frequency (kHz)

Co=91uFCo=138uF

1-22


Board layout example • Compact layout

o Lower switching & conduction losso Small switch nodes lower EMI

• Reduces parasitic inductance byminimizing switching loop areao Reduces switching loss and

voltage stresso Power stage and bootstrap caps

• Ensures good ground return patho Ground planes

Switching Loop A

Switching Loop B

Example converter layout

1-26

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Design of a high-frequency series capacitor buck converter