Design of (7, 4) Hamming Encoder and Decoder Using VHDL

www.futminna.edu.ng www.seetconf.futminna.edu.ng

Design of (7, 4) Hamming Encoder and Decoder Using VHDL

Usman Sammani Sani1*, Ibrahim Haruna Shanono2

1,2Department of Electrical Engineering,

Bayero University, Kano, P.M.B. 3011, Nigeria

Corresponding Author’s Email: [email protected], Phone Number: 08025791503

ABSTRACTHamming code is one of the commonest codes used in the protection of information from error. It takes a block of k input

bits and produce n bits of codeword. This work presents a way of designing (7, 4) Hamming encoder and decoder using

Very High Speed Integrated Circuit Hardware Description Language (VHDL). The encoder takes 4 bits input data and

produces a 7 bit codeword. The encoder was designed through the usual generator matrix multiplication while in the

decoder design the computation of the syndrome vector was ignored. Meanwhile, the different states that can represent a

particular input were calculated and the decoder was designed to identify each codeword representing a particular input.

Results have shown that the method is also reliable.

Keywords: Hamming, VHDL, Encoder, Decoder, Syndrome vector.

1. INTRODUCTION

Hamming codes are used in error detection and

correction in digital communication circuitries. Hamming codes belong to the class of block codes

which are codes that work on a block of bits rather

than individual bits of data. A block code

designated by (n, k) means k bits of input data is

used in producing a codeword, C with n bits of data

(Edward and David, 1994), (Richard, 2003). The n

– k bits added are called parity check bits. Thus a

(7, 4) Hamming encoder produces 7 bits from 4

bits and the codeword has 4 parity check bits.

Hamming codes are usually generated by

multiplying the input block, x by a generator matrix, G (John, 2007). Digital communications

involves 0s’ and 1s’. Both the generator matrix and

the input matrix are in form of 0s’ and 1s’. The

addition involved during the multiplication of the

two matrices is modulo – two addition (Edward

and David, 1994). For example a (7, 4) Hamming

code has the generator matrix

(1)For an input x,

C = Gx (2)

Hamming codes are decoded by multiplying the

codeword received, r by a parity check matrix, H to

see whether there is an error or not. The resulting

matrix is called a syndrome vector, Z. If Z is zero,

it means there is no error while if Z is not zero,

then the position of the bit that is in error is

indicated by Z. Hamming codes can only correct a

single bit error (Peter, 2002) and are mostly used in

Random Access Memory for error correction purpose (Mistri et al, 2014).

(3)

For a codeword C,

Z = Hr (4)

In this work, a (7, 4) Hamming encoder and

decoder is designed using Very High Speed

Integrated Circuit Hardware Description Language

(VHDL). VHDL is a programming language that

became popular in the 1990s’. It is similar to other

high level programming languages such as C but in

its own case it doesn’t have a compiler but has a

synthesizer. The synthesizer translates the written

source code into an equivalent hardware described by the source code. The process of this translation

is called synthesis (Enoch, 2006).

2. METHODOLOGY

The G and H matrices above were used in the

process. The encoder and decoder design will be

discussed separately.

2.1 Encoder Design

The encoder has a generator matrix in which it

produces the codewords. The codeword is a vector

with seven bits. Each bit is obtained by multiplying

the input matrix by a column in G as shown below:C(1) = x(1)

C(2) = x(2)

C(3) = x(3)

C(4) = x(4)

C(5) = x(1) XOR x(2) XOR x(4)

!"


C(6) = x(1) XOR x(3) XOR x(4)

C(7) = x(2) XOR x(3) XOR x(4)

C(n) stands for the nth bit in the codeword and x(n)

stands for the nth bit of the input bits. The VHDL code was then developed and synthesized using

XILINX ISE 10.1 software.

2.2 Decoder Design

For restoring the original message, the codewords

corresponding to the 16 possible combinations of

input were calculated using some Matlab codes.

The results of the 16 combinations of 4 bit input

data resulted in the table below:

Table 1. Codewords for 4 input data.

S/N X C

1 0000 0000000

2 0001 0001111

3 0010 0010011

4 0011 0011100

5 0100 0100101

6 0101 0101010

7 0110 0110110

8 0111 0111001

9 1000 1000110

10 1001 1001001

11 1010 1010101

12 1011 1011010

13 1100 1100011

14 1101 1101100

15 1110 1110000

16 1111 1111111

Hamming codes can correct a single error. So in

this work, bits of a codeword representing a

particular input were altered one by one and each

new codeword represents that same input.

Therefore in this case the need of computing the syndrome vector and later on correcting the bit in

error has been abandoned, unlike in (Saleh, 2015),

where the syndrome vector was computed. This

method also differs from that of (Hosamani and

Karne, 2014), in which the parity bits were inserted

directly without the use of a defined generator

matrix at the encoder and then the received parity

bits were also computed at the decoder. Thus in

our own case, each of the 16 input combinations

has 8 different codewords representing it. The

whole seven bits possible combinations of codewords has thus been assigned the correct input

representing it (i.e. 27 = (16 x 8) = 128). The table

below shows the different combinations of

codewords and there corresponding inputs.

Table 2. Codewords extension of 4 bits input.

S/N x C

1. 0000 0000000

1000000

0100000

0010000

0001000

0000100

0000010

0000001

2. 0001 0001111

1001111

0101111

0011111 0000111

0001011

0001101

0001110

3. 0010 0010011

1010011

0110011

0000011

0011011

0010111

0010001

0010010

4. 0011 0011100

1011100

0111100

0001100

0010100

0011000

0011110

0011101

5. 0100 0100101

1100101

0000101

0110101

0101101 0100001

0100111

0100100

6. 0101 0101010

1101010

0001010

0111010

0100010

0101110

0101000

0101011

7. 0110 0110110

1110110

0010110

!#


0100110

0111110

0110010

0110100

0110111

8. 0111 01110011111001

0011001

0101001

0110001

0111101

0111011

0111000

9. 1000 1000110

0000110

1100110

1010110

1001110 1000010

1000100

1000111

10. 1001 1001001

0001001

1101001

1011001

1000001

1001101

1001011

1001000

11. 1010 1010101

0010101

1110101 1000101

1011101

1010001

1010111

1010100

12. 1011 1011010

0011010

1111010

1001010

1010010

1011110

1011000 1011011

13. 1100 1100011

0100011

1000011

1110011

1101011

1100111

1100001

1100010

14. 1101 1101100

0101100

1001100

1111100 1100100

1101000

1101110

1101101

15. 1110 1110000

0110000

1010000

1100000

1111000

1110100

1110010

1110001

16. 1111 1111111

0111111 1011111

1101111

1110111

1111011

1111101

1111110

Codes were also written in VHDL to describe the

decoder.

3. RESULTS

Figure 1. Register transfer level of the encoder.

!$


Figure 2. Component view of the encoder

Figure 3. Register transfer level of the decoder

Figure 4. Component view of the Decoder

5. CONCLUSION

The paper has presented a way of designing (7, 4)

Hamming encoder and decoder using VHDL. The encoder

was designed the normal way while some modifications

were made in the decoder design that avoided the

computation of a syndrome vector. Results have shown

how VHDL simplifies the design of digital hardware and

how the design procedure is effective. The same process

can be used in the design of any Hamming encoder and

decoder. The designed circuits can be used in places they

would be applicable or even be left as trainers for students

to understand the concept of Hamming encoding and decoding. Thus several digital logic circuits meant for

experiment could be designed so that they can be used on a

single target device such as a Field Programmable Gate

Array. This reduces the cost of setting up a laboratory.

REFERENCES

Edward A. L., David G.M., Digital Communication,

Kluwer Academic Publishers, 1994, pp613-617.

Enoch O. H., Digital Logic and Microprocessor Design

with VHDL, La Sierra University, 2006, pp 23-26.

Hosamani R., Karne A.S., design and Implementation of

Hamming Code on FPGA Using Verilog, International

journal of Engineering and Advanced technology, Vol.4,

Issue 2, 2014, pp 181-184.

John P., Masoud S., Digital Communications, McGraw-

Hill, 2007, pp 413-418.

Peter S., Error Control Coding; from theory to practice,

John Wiley and Son’s ltd, 2002, pp 67–69.

Mistri R. K. et al, Reduced Area and Improved Delay

Module Design of 16 bit Hamming Codec Using HSPICE 22nm Technology Based on GDI Technique, international

Journal of Scientific and Research publications, vol. 4,

Issue 7, 2014, pp 1-6.

Richard E. B., Algebraic Codes for Data Transmission,

Cambridge University Press, 2003, pp54.

Saleh A.H., Design of Hamming Encoder and Decoder

Circuits for (64,7) Code and (128,8) Code Using VHDL,

Journal of Scientific and Engineering Research, Vol. 4,

Issue 1, 2015, pp 1-4.

!%

Documents

Design of (7, 4) Hamming Encoder and Decoder Using VHDL