Design-in-reliability: From library modeling and optimization to gate-level verification

Microelectronics Reliability xxx (2014) xxx–xxx

Contents lists available at ScienceDirect

Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

Design-in-reliability: From library modeling and optimizationto gate-level verification

http://dx.doi.org/10.1016/j.microrel.2014.03.0010026-2714/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author. Tel.: +91 80 25048053.E-mail address: [email protected] (P. Jain).

Please cite this article in press as: Jain P et al. Design-in-reliability: From library modeling and optimization to gate-level verification. Microelectron(2014), http://dx.doi.org/10.1016/j.microrel.2014.03.001

Palkesh Jain a,⇑, Bapana Pudi a, Meghna Sreenivasan b

a Embedded Processing Business, Texas Instruments, Bangalore 93, Indiab Indian Institute of Technology Bombay, Mumbai, India

a r t i c l e i n f o a b s t r a c t

Article history:Received 5 September 2013Received in revised form 18 January 2014Accepted 3 March 2014Available online xxxx

Keywords:ReliabilityNBTIEMSignal probability

A novel and comprehensive framework for aging analysis is presented in this work, comprehendingdegradation from BTI, hot-carriers and electro-migration. For the first time, all the primary variablesaffecting the aging of an interconnect and the transistor – namely, the equivalent duty-cycles, slewsand frequencies are incorporated into the calculation. Additionally, from electro-migration stand-point,the framework allows calculation of the exact RMS and ‘recovered’ average current for every metalsegment internal to the circuit, thus making it practically a universal model for aging analysis. Throughdetailed waveform-processor developed for validation, the aging model is ensured to be within 5% ofexact SPICE calculations.

The immediate application of such an extensive and accurate modeling is drawn in terms of influencingchanges to the library design/architecture itself, showcased through circuit and layout optimization fromEM, hot-carriers and NBTI constraints. Finally, we demonstrate the ultimate benefit from such a librarymodel for doing exact gate-level aging analysis, as well as against asymmetric aging. Results from28 nm production library models and complex SoC are shared.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Negative Bias Temperature Instability (NBTI), or gradual degra-dation of pMOS transistor and Channel Hot Carrier (CHC), are dom-inant product aging mechanisms. Their analysis and containment,in forms of manufacturing process correction, test guard-bands,designs margins and techniques has been an integral part of chipmaking, since last decade [1–4]. State-of-the-art STA methodolo-gies for aging, are reasonable in capturing the circuit’s responseto BTI – which is a very strong function of the operating conditions:the input slew, output load. However, the degradation as aphenomenon is strongly dependent on the operating voltage, tem-perature and ON-time of ‘a’ transistor – in turn dependent on theoverall history of the circuit operation, the toggle and slew ratesat the inputs and the loading condition.

Clearly, on a chip having multi-million transistors, the simplis-tic STA methods break, leading to significant inaccuracies in aginganalysis. A simple extension of the problem is highlighted throughFig. 1 in form of clock-network’s asymmetric aging based on theclock input states – analysis of which is not possible through

standard methodologies. Such scenarios only aggravate withaggressive usage of power management techniques [1,15,16].

Needless to say, all of these warrant a tight skew as well aspulse-width control from aging stand-point, including accuratecomprehension of circuit activity to the internal nodes.

Moreover, looking at the phenomenon of NBTI or CHC in a stan-dard 3-input AND circuit of Fig. 2a, for the encircled pMOS transis-tor (Fig. 2b), traditional wisdom holds that pMOS degradationhappens in the logical ‘0’ regime. However, we note that the ‘max-imal’ NBTI degradation really happens in the non-slew regime ofthe waveforms (Fig. 2c). Thus it is needed to incorporate sleweffects into NBTI induced delay degradations. Very naturally, sucha dependence of NBTI effect on the gate-slew also brings in thedependence on the switching frequency through every input ofthe cell. Thus we present a novel methodology of building librariesby means of delay-arc-wise sensitivities for each transistor, as afunction of toggle rates and static probabilities of all inputs.

In real circuits, however, it is not just the transistor which under-goes aging. Electromigration (EM), in wires has only aggravated inpast two decades with exponential shrinkage in wire-sizes andmuch higher increase in the current densities. Much of the EMproblem revolves around containing the average and RMS currentdensities in interconnects – namely signals, power network andcell-internal. While several enhancements happened in EM analysis

Reliab

http://dx.doi.org/10.1016/j.microrel.2014.03.001

mailto:[email protected]


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Clock A

Clock C

Clock B

Fresh Age

Fresh Age

Fresh Age

Fig. 1. Schematics and degradation-maps of (A) free running clock, (B) gated-highclock and (C) a gated-low clock, along with fresh/aged waveforms.

2 P. Jain et al. / Microelectronics Reliability xxx (2014) xxx–xxx

flow in past years – including accurate signal and power networkcurrent estimation, what remained unsolved and inadequately han-dled is the cell-internal EM checking portion at SoC level.

Through this work, we extend our novel methodology to accu-rately incorporate every input’s switching rates, slews and signalprobabilities in deriving the EM safety of cell-internal metalsegments. Additionally, we also consider the impact of EM ‘recov-ery’ on verification, which, to our knowledge, none of the state-of-the-art addresses.

In the next sections, we discuss the thought-process and analy-sis methodology. In particular, Section 2 discusses the prior art,Section 3 discusses the fundamental parameters affecting the reli-ability. The characterization methodologies are discussed in Sec-tions 4 and 5. Section 6 describes the validation of the proposedmodels, while we elaborate the usage of such models in designingrobust libraries in Section 7. Finally, SoC analysis and results areshared in Section 8.

2. Prior art

Aging analysis has garnered significant escalation in researchcommunity in past decade. Indeed, several tools and methods areavailable that analyze the circuit performance degradation causedby aging effects; both at (a) circuit level and (b) gate level. For

Fig. 2. (a) 3 input AND gate and its degradation scenario; (b) A-Y rising arc

Please cite this article in press as: Jain P et al. Design-in-reliability: From library(2014), http://dx.doi.org/10.1016/j.microrel.2014.03.001

instance, Kumar et al. [12] and Stempkovsky et al. [10] discussedthe concept of transistor-level impact on gate-delay. Lu et al. [9]proposed a statistical reliability analysis method; however thetransistor level details remained elusive in that. Cao et al.,proposed critical-node-aware aging analysis, however, the rigoron individual transistor level details was low [7,13]; similarly forTehranipoor et al. [8]. The work done by Lorenz et al. covers thetransistor level stress in detail, however, it still did not considerthe slew and frequency effects on NBTI [11]. In summary, our workadvances the state-of-the-art in multiple vectors: EM verificationas well as accurate aging analysis incorporating all the factors:slew, duty-cycle and frequency. It additionally incorporatesaccurate recovery into EM calculations, which is important fromEM perspective.

3. Key parameters affecting NBTI, CHC and EM

As discussed in previous sections, the key parameters impactingthe aging mechanisms can be noted as:

a. Input slew – at every transistor (s).b. Input toggle rate – at every transistor (R).c. Duty cycle – at every transistor (a).

The important thing here is the extension of above key param-eters from a circuit’s pin to ‘every’ resistor and transistor of the cir-cuit. We note that NBTI predominantly occurs during the standbymode, while the current-driven CHC and EM mechanisms have sig-nificant impact only during the slew periods. EM, additionally, alsohappens during the static period of the circuit operating due to theleakage currents – as summarized in Fig. 2c. Before formulating oursolution, we now study the key parameters in detail:

3.1. Parameters affecting NBTI

We use the classic R–D model for the NBTI degradation:

DVthd ¼n2K2

vaXMCt

f2t2oxð1� aXMÞ

!n

ð1Þ

where the symbols have their usual meaning, [1]. In simple means,Vth shift is proportional to the stress time as follows:

for the circuit, with B/C high (c) switching regimes with degradation.

modeling and optimization to gate-level verification. Microelectron Reliab


P. Jain et al. / Microelectronics Reliability xxx (2014) xxx–xxx 3

DVths ¼ ðK2v tÞn ð2Þ

Note that in the existing practice, the ‘ON-time’ of a pMOS tran-sistor is the primary indicator of the stress time.

However, we observe that even the time, which pMOS transis-tors spend in transitioning from ON to OFF state (or vice versa, alsoreferred to as the slew-period), is crucial in determining the netstress on the transistor (slew period in Fig. 2). Indeed, NBTI doesshow a significant inverse relationship with slew and toggle rate,as supported by data generated through RelXpert based simula-tions on the 3-input AND gate in Fig. 3.

This can be explained by the fact that the NBTI phenomenon isdriven by inversion, or the presence of carriers. During the slewperiod, large switching currents flow through the circuit, causingthese carriers to be swept away, so the NBTI degradation reduces.While calculating NBTI induced delay, our approach takes care ofthe slew effect by subtracting the net time spent in slew fromequivalent duty cycle calculations.

As a natural extension, if the transistor sees a high frequencysignal, the ‘slew regime’ occurs more often – pronouncing theimpact of such a slew on NBTI degradation, making it importantto account for in calculations.

To our knowledge, this work is the first incorporation of such acorrection in the ‘real’ stress-time computation for NBTI. As a nota-tion, we will use the terms ‘logical’ duty cycle for duty cycle whichis derived independent of the slew, and ‘effective’ duty cycle for theone which incorporates slews.

3.2. Parameters affecting CHC

CHC has been traditionally modeled as a degradation in thethreshold voltage, Vth, given by, [5]:

DVth ¼Ids

HWIsub

Ids

� �m

� t� �n

ð3Þ

where symbols have their usual meaning. From a standard circuitoperation standpoint, we note that CHC fundamentally depends on:� Drain voltage (impacts the amount of current.� Slew and load (impacts the duration of current flow.

Further, in case of stack-topology circuits, the CHC effect is inmost cases of the second-order, since the Vds applicable on the de-vices goes down. However, for all other circuits, as we note thatCHC depends on the absolute slew as well as the frequency (ornumber of toggles per second), we introduce a parameter ‘‘percent-age slew’’ – ratio of absolute slew to the time period. This singleparameter captures the impact of both slew as well frequency.

Average NBTI induced delay deg. vs Avg % Slew

0

1

2

3

4

5

6

7

8

0 5 10 15 20 25

% Slew (average)

Ave

rage

del

ay d

egra

datio

n

Fig. 3. NBTI delay degradation decreases with increasing slew.


3.3. Electromigration

The classic Black’s equation relates the mean time to failure(MTF) to the average DC current density (AVG) and the absolutetemperature of the wire [2]:

MTF ¼ Að J�nÞeEa=kT ð4Þ

This is also plotted graphically through Fig. 4. Additionally, thewire temperature has an inherent squared dependence on theroot-mean-square (RMS) current flowing through it, famouslyknown as Joule heating (JH), [3]. Pioneering work by Hunter, [4],combines AVG, RMS currents and temperature to create self-consistent formulations for EM checking, thus making the analysisindependent of peak currents for regular signal interconnects.

However, AC electro-migration brings in a peculiarity of recov-ery of damage. This recovery factor ‘r’, however, is non-unity andthe effective average current, thus, needs to be computed in themanner as authors have described in [6]. Such an incorporationin library models for EM is a fundamental contribution of thiswork. From the foregoing discussion, the key parameters whichdetermine the NBTI, CHC and EM can be summarized as in Table 1.

3.3.1. Importance of accurate temperature estimationAs noted in previous sections, the two important effects against

which, interconnects needs to be safeguarded are, Electromigration(EM) and Joule Heating (JH).

While EM is a indeed a long term problem aggravated with tem-perature rise due to JH, Joule heating in itself is an instantaneousproblem. Thus, for example, while a design with only 2 yearlifetime requirement might have very relaxed EM rules, the con-straints on RMS currents for the design will not be very differentfrom a design with either 2 months lifetime or even 10 years. Addi-tionally, while the fundamental EM limits can also be influenced bya design’s choice of junction (or ambient) temperature and systemcomplexity [6], no such knob exists for RMS currents.

Fig. 4. Representative acceleration of EM failures with temperature.

Table 1Enlisting various parameters of interest for reliability analysis.

Phenomenon NBTI CHC EM

Transistor/resistor dimensions Weak Strong StrongCkt topology (stacked, Vds) Weak Strong WeakDuty cycle Strong Weak StrongSlew Strong Strong StrongFrequency Strong Strong StrongOperating voltage Mod. Strong Mod.Temperature Strong Mod. StrongStress time Strong Strong StrongRecovery Mod. Weak Strong




In light of above argument, it is also important to note the re-cent design trends – in terms of dominance of either EM mecha-nism or Joule Heating. As an example, it is easy to observe thatinterconnects within the SoC power network will have more DClike nature with intermittent surge in currents due to switchingactivities. On the other hand, interconnects in clock network willhave extreme AC nature and the average current of such intercon-nects will be, on the contrary, very small. Above characteristics ofthe interconnect can be nicely parameterized through an effectiveduty cycle ‘r’, which is defined as squared ratio of average and RMScurrent densities. Thus, a signal which is pure DC will have an ‘r’value close to 1 and a signal with very high RMS component is ex-pected to have a very small value of ‘r’. Accordingly, an ‘r’-map ofthe entire design can quickly help characterize the nature of thedesign.

Indeed, a design having a majority of signals with high ‘r’ valueis expected to be EM-limited, whereas the design with dominatinglow ‘r’ values will be RMS limited.

We have collected such data from several production designs on65 nm and 40 nm nodes, summarized for one of the designs inFig. 5. As can be seen, the design is indeed RMS limited. In lightof above discussion, it is extremely critical to compute the RMScurrent accurately, since that being the only knob to contain RMScurrents.

4. NBTI and CHC characterization approach

In the previous sections, we explained the key parameters wewould be focusing on and our motivation for this work. Now wepresent the approach we used for library modeling, primarilyfocusing on combinational and clock tree cells for NBTI/CHC char-acterization. To begin with, we go back to the circuit in Fig. 2b,where for the highlighted arc, we note that two critical parameterswill affect the arc-delay:

� Degradation (Vth shift) of all the transistors in that arc – this, inturn, depends on the effective duty cycle seen at each transistor,which is a function of the history of circuit operation – all arcs,slews and transitions.� Sensitivity of individual transistors to overall arc delay – this

depends solely on the circuit topology and response.

Duty Cycle distribution for all sigTotal Nets:

0.E+00

1.E+06

2.E+06

3.E+06

4.E+06

5.E+06

1.00E-07 1.00E-06 1.00E-05

Duty C

Occ

uran

ce

Fig. 5. Duty cycle distribution, highlig


Therefore, what we really need is the individual delay sensitiv-ities for each transistor to each arc, and the actual Vth degradationseen by each transistor on the arc. We noted that according to thestress conditions (i.e., the static probabilities of inputs, the togglerates at the inputs, the output load and input slew and the stressduration), each pMOS transistor’s Vgs sees an effective duty cycleaXMi. Thus, Eq. (2) yields the shift in Vth seen by each transistorXMi, which we denote by DVthXMi.

The methodology we propose involves accurately accountingfor NBTI effects by maintaining a delay-sensitivity library (i.e.change in cell delay per mV change in threshold voltage) of the cellwith respect to each of its pMOS transistors, per arc – denoted bySXMi. We also maintain the global delay sensitivity per arc, i.e., thechange in cell delay when the threshold voltages of every pMOStransistor are shifted by 1 mV. This is denoted by Sglobal.

Let the number of rise transitions of input A be denoted by NAr

and the number of fall transitions be NAf with similar notation forother inputs B, C and so on. Let toggle rate at input A be RA, at inputB be RB etc. and the total time of stress be t. Then,

NAr ¼ NAf ¼ðRA � tÞ

2ð5Þ

Now consider the arc A-Y with A rising and the other inputs atstatic values like B = 1, C = 1 etc., as shown in Fig. 2b. The arc-probability in this case is given by:

p arc A� Y jB ¼ 1C ¼ 1A rise

0BBBB@

1CCCCA ¼

NAr

t

� �� probðB ¼ 1; C ¼ 1 . . .Þ ð6Þ

Then, we propose replacing the different DVthXMi obtained asdiscussed previously by a single effective global threshold voltageshift for the arc, denoted by DVthglobal. Assuming delay sensitivityto be linear, DVthglobal is given by:

DVthglobalarcA�Y¼Pn

i¼1ðDVthXMi � SXMiÞSglobal

ð7Þ

where n is the total number of pMOS transistors in the cell.

nals in 45nm ASIC design~ 25M

1.00E-04 1.00E-03 1.00E-02

ycle (r)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

CD

F

occurancecumulative

hting proportion of Joule heating.




Therefore, the total delay of the cell would increase by thequantity DVthglobal � Sglobal if we were to degrade the Vth of eachpMOS by DVthglobal Y for the A-Y arc (with B/C = 1).

This Eq. (7) indicates a very important point: contribution of apMOS transistor towards the Vth shift of an arc depends on thecombination of both its individual Vth degradation and its sensitiv-ity towards arc delay. This means that even a pMOS with highdelay sensitivity may actually have no effect on NBTI if circuitconditions are such that it sees very little stress.

Note that derivation of DVthXMi depends on the duty cycle seenat XMi. As mentioned before, aXMi denotes the effective duty cycleof the Vgs of transistor XMi. In order to calculate this value, wemaintain a table of pMOS transistors and the list of input statesfor which each pMOS transistor is ‘stressed’, i.e., when their Vgs at-tains the value of (negative) VDD, for each cell. Now based on thestatic probabilities at the inputs, denoted by p(Input), we calculatethe probability of occurrence of each state, denoted by p(State). Weassumed that the multi-input switching does not happen. As anexample, we can state that:

pðState 010Þ ¼ pðA ¼ 0Þ � pðB ¼ 1Þ � pðC ¼ 0Þ ð8Þ

From this table of stress-states per transistor, and Eq. (8), wecan calculate the effective logical duty cycle of each pMOS transis-tor as simply the sum of the probabilities of all the states in whichthe transistor in stressed. The entire process is highlighted in Fig. 6.For example, in the 3 input gate of Fig. 2b, let pMOS XM5 bestressed in 010, 001 and 111.Then,

aXM5ðlogicalÞ ¼ pðState 010Þ þ pðState 001Þ þ pðState 111Þ ð9Þ

We now need to compute the effective slew seen by the Vgs ofthe pMOS transistor. We note that the input slews to the circuitand the output load governs the slew seen in the Vgs waveformof each internal pMOS transistor.

Indeed, going back the 3-input circuit of Figs. 2b and 7 show themagnitude of Vgs of the critical pMOS transistor (XM5 – tagged asoutput waveform) for different input waveforms at the 3 pins. Ascan be inferred, the duty cycle as well as the slew at the outputvaries according to conditions at the input.

As discussed in Section 3.1, NBTI has power-law behavior withthe stress time. This stress time must be slew-adjusted – meaningwe need to either subtract or add the slew to the logical duty cycleto get the final effective duty cycle aXMi. From the toggle rates andthe rise and fall slews at each input, we can exactly calculate thenumbers of transitions of the Vgs of each transistor during the timeof use, and with what slews these transitions occur.

In order to calculate the effective slew at a given pMOS transis-tor XMi, we proceed arc-wise. Let the slew in the Vgs of XMi due to

Sglobal

Degrade Vth of all pMOSes

Get delay sensitivity for

each arc

Calculate Sglobal

SXMi

Degrade Vth of each pMOS, one

by one

Get delay sensi�vity for

each arc

Calculate SXMi

ΔVthXMi

Generate list of stress states for

each pMOS

Get αXMi from input probabilities

Calculate ΔVthXMi

Fig. 6. Framework we use to obtain the effective Vth shift for each arc.


a rise at pin-A and static states of the other inputs fixed at somestate 1 be denoted by swAr (XMi) 1, and for rise at A and the nextpossible combination of static states of the other inputs fixed atsome state 2 be denoted by swAr (XMi) 2, and so on. Let the probabil-ity of the other static states (state 1 etc. in above notation) in statek be denoted by p(k), which we can calculate from (8). Also, let theslew at XMi due to a fall at A, other inputs at some fixed static state1 be denoted by swAf (XMi) 1 etc. Then, the time spent by the Vgswaveform of transistor XMi in slew regime is

¼XSwXMi

all inputs

Xk

½NArswArðXMiÞkpðkÞ þ NAf swAfðXmiÞkpðkÞ� ð10Þ

Therefore, the effective duty cycle at transistor XMi is:

aXMi ¼ aXMiðlogicalÞ �SwXMi

tð11Þ

Note that all the inputs required to compute the effective dutycycle can be easily derived from library characterization tool.

4.1. Incorporating temperature and Vdd dependency

In modern designs, dynamic voltage and frequency scaling is anorm. To address the same, we use equivalent stress approach,by appropriately scaling the stress time t to a new value t0 thathas an equivalent effect on Vth shift.

DVthðt0;V2; T2Þ ¼ DVthðt;V1; T1Þ ð12Þ

Here DVthðt;V1; T1Þ is calculated according to the Vth Eq. (2) wedescribed in Section 3.1.

5. Electromigration characterization

Over the past two decades, current densities in interconnects in-creased several orders, thereby making them extremely vulnerableto EM [6]. EM is a process in which mass transport takes place as aresult of interaction between the moving electrons and the metalions at high current densities. Typically, EM containment of adesign relies on ensuring current densities in interconnects –namely signals, power network and cell-internal, remain withinthe technology limits, as shown in Fig. 8a. While the Signal andPower network EM are reasonably well addressed through com-mercial EDA tools, the prevailing methodology of cell-internal EMvalidation is around estimating the safe-operating-frequency atlibrary-level and subsequent pass/fail flag at chip level (Fig. 8band c).

Such methods, however, cannot comprehend the vast spread ofload/slew/switching rates among different pins. We, hence,propose a novel method of computing the currents through eachresistor and comparing against the foundry-thresholds.

5.1. AC electromigration and EM recovery

An important contribution of this work is accurate assessment ofEM recovery and ‘recovered’ average current. The effect of EMrecovery on a resistor can be well understood by Fig. 9, whichshows the current waveform through the load resistor in the 3-input AND gate (Rxy of Fig. 2b). This waveform is derived basedon the input excitations of Fig. 7. Note that traditional EM calcula-tions for average current indicate Javg = 0, since the current inpositive and negative cycle cancel out. However, for such a currentwaveform (also shown in Fig. 10a), experimental measurementsreveal that even though the average current is zero, the resistor stillhas a finite failure time (typically an order higher than the lead withpure DC current density). The lifetimes can be inferred fromFig. 10b.



Fig. 7. Motivation for effective duty cycle and effective slew computation.

Fig. 8. Showcasing (a) different segments requiring EM checking (b) operating conditions based load/slew checks and (c) SPICE based checks.

Fig. 9. Currents through load resistor Rxy in 3-input AND gate.


It needs to be noted that most of the state-of-the-art EM assess-ment tools and models assume this EM recovery to be unity(meaning positive current flow cancels out EM effect in negativecycle), [14]. However, Fig. 10 conclusively asserts the need of incor-porating recovery into EM failures.


5.2. Current computation approach

In order to compute the RMS and AVG current, we note that cur-rent flow in any circuit can be bucketed as: (1) leakage current and(2) charging/discharging current. The first occurs when the inputs



Fig. 10. (a) AC current waveform and (b) lifetime evolution in DC and AC current waveform, indicating importance of recovery in EM calculations.


of the circuit are stable while the second occurs during switchingof an input. As discussed in earlier sections, we also need to ensurethat the average current computation in both the modes (leakage/switching) comprehends the recovery effect in EM. We nowdiscuss how we can compute the effective leakage current throughany resistor in the cell, followed by the switching current.

5.2.1. Leakage current induced electromigrationLeakage currents depend only on input state, when there are no

transitions. Using a circuit simulator (e.g.: Cadence Spectre), wecan obtain average and RMS currents through each resistor cyclingthrough all possible input states and maintain these as part of thecell library. Let the average leakage current through resistor Rj forstate k of the inputs be denoted by AVG(ileak)(Rj)(k). Then, the effec-tive average leakage current through resistor Rj considering partialrecovery would be:

Aleak ¼Xk

AVGðileakÞðRjÞðkÞ > 0

ðAVGðileakÞðRjÞðkÞpðkÞÞ

þXk

AVGðileakÞðRjÞðkÞ < 0

ðrAVGðileakÞðRjÞðkÞpðkÞÞ ð13Þ

Let the RMS leakage current through resistor Rj for state k ofinputs be denoted by RMS (ileak)(Rj)(k). Then the effectivemean-squared current through Rj is:

MSleakðRjÞ ¼X

k

pðkÞastfRMSðileakÞðRjÞðkÞg2 ð14Þ

p(k) can be calculated from (8).

5.2.2. Switching/charging current induced electromigrationIn order to compute the RMS and average current through every

resistor of the circuit under every possible arc, load, slew condition,we leverage the SPICE simulation framework of existing timingcharacterization software ALTOS Liberate. Since such simulationsare optimized for timing char., we also retain the duration usedfor making this measurement and store these in the cell library.Subsequently, we calculate the contribution of these switchingcurrents to the effective average and RMS current through eachresistor.

We continue the notation used in effective slew calculations inSection 4.1. In addition, let the average current through Rj due to arise at input A with the other inputs in static state k be denoted byAVG(Isw)(A,k,R)(Rj). We denote the time duration over which this


average was calculated by t(A,k,R)(Rj). Similarly we haveAVG(Isw)(A,k,F)(Rj) and t(A,k,F)(Rj) for fall at input A. Then, thecontribution of positive-valued average switching currents to theeffective average current through Rj is given by

Aþsw ¼X

allinputsz ¼ r; f

Xk

AVGðIswÞðA;k;zÞðRjÞ > 0

� ½pðkÞ � AVGðIswÞA;k;zðRjÞ � tðA;k;zÞðRjÞ �NAz�=t ð15Þ

The contribution of the negative-valued average switching cur-rents is written analogously.

A�sw ¼X

allinputsz ¼ r; f

Xk

AVGðIswÞðA;K;ZÞðRjÞ < 0

� pðkÞ � AVGðIswÞðA;K;ZÞðRjÞ � tðA;K;ZÞðRjÞ �NAz

h i=t ð16Þ

For RMS, the calculations are quite similar. The effective mean-squared switching current through resistor Rj is:

MSswðRjÞ¼X

allinputsz¼ r; f

Xk

½pðkÞ�fRMSðIswÞðA;k;zÞðRjÞg2 � tðA;k;zÞðRjÞ�NAz�=t

ð17Þ

Now, the effective EM average current through Rj can be calcu-lated by taking the sum of Aþsw r% of A�sw to account for partial recov-ery, and leakage effective value Aleak from (13).

AVGeff ðRjÞ ¼ Aleak þ Aþsw þ r � A�sw ð18Þ

The effective RMS current through Rj considering both leakageand switching is then given by the square root of the sum of thequantities in Eqs. (14) and (17).

RMSeff ðRjÞ ¼ fMSleakðRjÞ þMSswðRjÞg1=2 ð19Þ

Thus, depending on input and operating conditions, we can cal-culate the effective average and RMS currents through key resistorsin the cell and compare against the EM thresholds in the library tocheck for EM violations.

6. Discussion and validation

In previous sections, we presented the novel method for accu-rate NBTI, CHC and EM characterization. An important challengein solving the problem all the while has been the availability of



Effective RMS; SPICE versus Proposed Method

2.E+04

4.E+04

6.E+04

8.E+04

1.E+05

opos

ed M

etho

d (a

. u.)


infrastructure to compute effective slews, duty-cycles and currentsunder arbitrary operating conditions.

Consequently, in order to validate the estimates from theproposed methodology, we developed a waveform processor, whichcan take arbitrary current/voltage waveforms (as in Fig. 7) to com-pute the effective equivalents. This is done through custom devel-oped software for processing the simulation waveforms. For thesame 3 input AND gate (of Fig. 2), we tabulate the results from pro-posed method versus the waveform computed equivalent numbers.

0.E+000.E+00 2.E+04 4.E+04 6.E+04 8.E+04 1.E+05

SPICE (a. u.)

Pr

Fig. 11. Comparison between effective RMS current through Rxy from calculationsand from HSpice simulations.

6.1. Effective slew and duty cycle validation

Multiple combinations of varying input’ duty-cycles, rise/fallslews and the toggle rates were given so that we get an arbitrarywaveforms on the critical component. Through the custom wave-form processor, we compared the percentage time spent in logicalstates w.r.t the proposed method and results are captured inTable 2– establishing tight correlation.

Similarly, effective duty cycle validation was carried out. Theproposed method efficiently collapses the final waveform intothe one with an equivalent duty cycle, Table 3 – confirming theaccuracy of method.

Fig. 12. Showcasing layout of a standard cell and EM limiting via.

6.2. EM calculation validation

We validated our approach towards EM calculations by compar-ing the values of RMS currents through key resistors in a 3-inputAND gate (Fig. 11) obtained by applying Eq. (19) with thoseobtained from HSPICE measurements. We assumed the recoveryfactor r = 0.6.

While bulk of the work discussed in previous sections is aboutlibrary data generation, the key aspect of deriving the equivalentduty cycles of transistors is done at SoC level. For this purpose,the activity rates and signal probabilities at primary input pins ofcells is derived through state-of-the-art activity propagationengines like PT-PX or similar tool. Subsequently, the sensitivitylibraries will be loaded for each of these cells to eventually derivefor any given timing arc, the equivalent threshold voltage shift.

The solution also makes it very natural to perform asymmetricaging analysis, induced due to clock gating, as we will see in latersections.

Table 2Eff. slew comparison between SPICE and proposed method.

Rise slew (ps) Fall slew (ps)

A B C A B C

10 19 5 600 75 30075 10 5 75 10 575 38 19 75 38 1975 38 19 5 38 150

600 600 150 600 600 150600 600 600 600 600 600

Table 3Eff. duty-cycle comparison between SPICE and proposed method.

Rise slew (ps) Fall slew (ps)

A B C A B C

75 10 19 5 10 15019 19 19 19 19 19

600 600 600 600 600 60075 10 19 5 10 15010 19 5 150 75 300

600 600 600 600 600 600


7. Robust library design methodology

7.1. Electromigration perspective

In previous sections, we looked at the approach of accuratelymodeling the cell-reliability from an EM perspective, by capturingthe impact of the operating frequencies, loads and slews on the

Output load (fF) % Slew (SPICE) % Slew (this method)

5.57 4.59 4.395.57 3.83 3.74

27.85 3.63 3.745.57 6.46 6.56

27.85 6.75 6.5627.85 10.6 11.07

Output load (fF) Duty cycle (SPICE) Duty cycle (this meth.)

5.57 77.02 78.25.57 46.44 46.32

27.85 46.03 45.875.57 57.3 57.2

27.85 41.08 40.7877.85 63.2 67.4



0

0.2

0.4

0.6

0.8

1

1.2

0 0.5 1 1.5 2 2.5

Max

. Saf

e O

pera

�ng

Fre

quen

cy (a

. u.)

Opera�ng Load (a. u.)

Original LayoutImproved Layout

Fig. 13. Characterization of EM-safe frequency of the cell with the operating load/slew indices.


internal resistor current. In this section, we will look at how such amodel enables robust library-design, besides strengthening thechip level reliability.

Shown in Fig. 12 below, is a layout of a standard clock tree cellfrom 28 nm library. The methodology from prior sections isdeployed on this particular clock tree cell to characterize its EMproperty.

Vdd

Vss

DCB

AY

D

BA

C

(a) Circuit Style 1

16

3

Cell InpuSlew (AU

Fig. 14. (a) Circuit diagram for an AOI g

C

A

B

D

B

C

A

D

Y

Vss

Vdd

(a) Circuit Style 2

126

3

Cell InpuSlew (AU

Fig. 15. (a) Modified (optimized) circu


Fig. 13 below showcases the characterized EM-safe frequency ofthe cell with the original layout versus the operating load. Notethat this is generated at a fixed input slew, hence the Y-axis repre-sents the maximum allowed EM-safe frequency.

As expected, with the increase in operating load, the currentsflowing in the internal leads of the cell increase, causing them toeventually fail at the operating frequency. This failure, in termleads to a decrease in the safe-frequencies.

A close analysis of the layout (along with the EM-model) helpspinpoint that it is indeed the via on the power-line internal to thecell, which becomes limiting with the increase in operating load. Alayout fix (in terms of increasing the number of vias), does reflectin increased EM performance of the cell, also visible from theEM-model of the modified layout (in Fig. 13).

7.2. Transistor degradation perspective

Having seen the benefit of the EM model and the associatedimprovements in the cell reliability, next we look at the aspectsof transistor-degradation modeling and how it can be utilized todesign reliable libraries. Specifically, we will explore how NBTIdegradation in a circuit can be improved. Fig. 14a below showcasesa 4-input AOI gate. Using the characterization methodologydescribed in previous sections, the delay degradation of the A-Y

400200

10050

252

0.002.004.006.00

8.00

10.00

12.00

14.00

4 7 14 28 57 113 227 252

t )

Delay D

egradation

Operating Load (AU)

Degradation variations across load/slew spacefor a combinational cell

(b) Degradation Map

ate (b) degradation for the A-Y arc.

5025 0.00

1.00

2.00

3.00

4.00

5.00

6.00

7.00

4 7 14 28 57 113 22

7 252t

)

Delay D

egradation

Operating Load (AU)

Degradation variations across load/slew spacefor a combinational cell

100200

400

(b) Degradation Map

it diagram (b) degradation map.



Fig. 16. Delay degradation data (from conventional and proposed methods) acrossmultiple clock paths in the design.

Table 5Asymmetric aging impact at design level across multiple designs.

Design details(28 nm)

Timing violations withoutasymmetric aging

Violations withasymmetric aging

Design A 724 938Design B 617 631Design C 788 958


rising arc is shown in Fig. 14b, where the other inputs are held atstatic logic conditions.

As discussed in previous sections (4), the NBTI degradation inthis circuit, with respect to the A-Y arc, happens in proportionsto the logic-low probability of the input A. Clearly, with a rise in in-put slew or load, the pull-up contribution of the degraded transis-tor increases, causing an increase in the delay degradation. It canbe noted that few design techniques have been reported in litera-ture to mitigate NBTI degradation, [10]. However, in this elucida-tion, we will exploit the signal probabilities and the position ofthe switching device to alleviate the aging as well as the impactof aging. Based on the discussions in prior sections, it is clear thatthe degradation of the pMOS transistor ‘A’ in such a stacked-circuitcannot be computed accurately when treated alone, but has to be aconvoluted computation involving probabilities of other pMOStransistors.

Clearly, in such a case, the pMOS transistors which are directlyconnected to the power-supply are at a chance of undergoing high-

Time Zero = 1000ps

Time Zero500

Time Zero = 1000ps

Time Zero = 1000ps

Time Zero500

Time Zero = 1000ps

Fig. 17. Timing diagram for a circuit, showcasing impact o

Table 4Frequency degradation estimates with conventional and proposed methodologies.

Interaction (timer zero min. clockperiod required)

Frequency degradation estimation

With existing methods

Flops 1,2 interact EoL min. clock perio required = (1100 ps + 51100 ps) = 550 ps

Time zero requirement = 500 ps 10% degradation

Flops 2,3 interact EoL = (1100 ps + 1650 ps) – 1650 ps = 1100 pTime zero requirement = 1000 ps 10% degradation


er degradation as compared to the other ones. Such an assertion isalso true, when all the 4 inputs have same probabilities.

Using such principles, an alternate circuit/stack style for such acircuit, as shown in Fig. 15a, can be arrived at, where the criticaltransistor is swapped down the stack.

Indeed, the reduction in degradation (due to the reduced overallON probability), as well as the sensitivity of the device to circuitdelay is reflected through the graph in Fig. 15b.

8. Gate-level reliability verification

Having looked at the detailed aspects of the reliability modelingand very specific cases of how it can be used to improve the cellrobustness itself, we now look at a much broader application ofsuch models at gate-level assessment of reliability.

8.1. Application to accurate NBTI aware STA

While multiple approaches exist to analyze for the impact ofNBTI degradation in STA today, the most commonly used onesare either based on straight margining, or, through the use ofdegraded SPICE model (End-of-Life model). Specialized tools likeCadence-RelXpert, on the other hand, offer an accuracy of fullSPICE based estimation of degradation, including recovery effects.

In the current work, we benchmark the models developedthrough previous sections against the different methods from

= ps

Time Zero = 1500ps

Time Zero = 500psTime Zero = 500ps

= ps

Time Zero = 1500ps

Time Zero = 500psTime Zero = 500ps

f clock gating and analysis with the proposed models.

With proposed methods

50 ps – Gate 0 remains at logic ‘0’. EoL min. periodrequired = (1100 ps + 500 ps – 1000 ps) = 650 ps30% degradation

s Gate 0 at logic ‘0’. Gate 1 at logic ‘1’EoL = (1100 ps + 1650 ps) – (550 ps + 500 ps + 550 ps) = 1150 ps15% degradation



0

Fig. 18. Plot of the EM ‘severity ratio’ of every instance of a clock tree cell.


several clock-paths chosen from a high performance 28 nm design.The models of the clock tree cells were characterized and utilizedwith an input probability of 0.5. Fig. 16 shows the normalized per-centage delay degradation obtained from different methods.

As can be seen, the results from proposed model and its appli-cation closely track with Cadence-RelXpert, while being better ascompared to other approaches like margin or even a degradedSPICE model. The different responses of clock paths can be attrib-uted to the differences in the headroom and the operating loadassumptions.

8.2. Asymmetric aging analysis

Armed with the accurate modeling and probabilistic propaga-tion methodology, we now revisit the problem statement intro-duced through Fig. 1 with respect to the asymmetric aging onthe clocks. In particular, we look at a circuit extension of asymmet-ric aging through Fig. 17, below.

As discussed earlier, in such a timing circuit, the extent of clockgating on the gaters (Gate0, Gate1) can significantly alter the skewdevelopment through the clock circuit.

The key advantage of methodologies developed through thiswork is in facilitating the option of a bounded graph based analysis(apart from parameter sensitivities being an analysis by-product) –thereby also ensuring exhaustive coverage of all paths. The modelsenable an ultra-fast asymmetric aging analysis just by easy selec-tion of the activity rates at the primary clock-gates in the design.Consequently, Table 4 shows the results comparison as obtainedfrom a regular aging analysis versus our approach.

We note that for a 1X frequency degradation estimate throughregular aging analysis, up-to 3X frequency degradation can happenin the asymmetric aging case, rightly estimated through the newapproach. We now present the results from usage of above meth-ods on multiple advanced power-managed designs. As seen fromTable 5, application of such a method results in identifying newerrisk paths.

A detailed analysis of the violations and the clock path was sep-arately done to realize the nature of violations and the exact agingof certain portion of clock-trees.

8.3. Cell-internal EM analysis

Having looked at the application of the transistor-degradationmodels into the gate-level timing verification, we now look at


aspects of Electromigration. Specifically, we look at a clock tree ele-ment used generously across a 28 nm design. Based on the EMmodel developed for this particular cell, a safe-ratio for every in-stance in the design was determined. This ratio is essentially theratio of the safe-frequency (as queried from the model at therelevant operating load/slew), to the operating frequency of the in-stance, as plotted in Fig. 18. Here, the X-axis represents the safe-ratio and the primary Y-axis represents the occurrence of suchinstances, while secondary Y-axis is the CDF plot.

Clearly, such a model helped us identify the instances of theparticular cell (although handful – less than 0.1%) which operatebeyond the safe space. Particularly, the instances from Fig. 18, withsafe ratio > 1 were fixed, to either reduce the operating load orreplace the particular instance with a higher drive variant.

9. Conclusion

A novel and comprehensive framework for aging analysis waspresented in this work, comprehending degradation from BTI,hot-carriers and electro-migration. All the primary variables affect-ing the aging of an interconnect or the transistor: the equivalentduty-cycles, slew and frequencies were incorporated into thecalculation. Additionally, from electro-migration stand-point, theframework allows calculation of exact effective RMS and ‘recov-ered’ average current for every metal segment in the circuit, thusmaking it practically a universal model for aging analysis. Throughdetailed waveform processor developed for validation, weestablished that the aging model arrived in such manner is within5% of SPICE calculations. Immediate application of such a modelwas shown in terms of library improvements through layout andcircuit modifications. Finally, the model was applied duringgate-level verification with different applications like NBTI awareSTA analysis, asymmetric aging and EM verification for cell-internal safety. Using all the proposed techniques, we demon-strated specific risk areas in designs – in terms of asymmetric agingor in terms of specific instances of a given cell operating at unsafeconditions.

References

[1] Krishnan AT et al. NBTI impact on transistor and circuit models mechanismsand scaling effects [MOSFETs]. Proc IEDM 2003.

[2] Krishnan AT et al. Product drift from NBTI: Guardbanding circuit and statisticaleffects. Proc IEDM 2010.

[3] Meyer et al. IBM JRD, 2007.


http://refhub.elsevier.com/S0026-2714(14)00092-4/h0005






[4] Huard V. IRPS Tutorial 2010.[5] RelXpert User Manual, <www.cadence.com>.[6] Jain P et al. Current estimation for reliability analysis. IEEE TVLSI 2012.[7] Wang W, Yang S, Cao Yu, et al. The imapct of NBTI effect on combinational

circuits. IEEE TVLSI 2010.[8] Wang S, Chen Tehranipoor J. Representative critical reliability paths for low-

cost and accurate on-chip aging evaluation. ICCAD 2012.[9] Lu et al. Statistical reliability analysis under process variation and aging effects.

DAC 2009.[10] Stempkovsky et al. Calculation of stress probability for NBTI-aware timing

analysis. ISQED 2009.


[11] Schlitmann Lorenz. Efficiently analyzing the impact of aging effects on largeintegrated circuits. Microelectron Reliab J 2012.

[12] Kumar et al. NBTI-aware synthesis of digital circuits. DAC 2007.[13] Wang Cao W et al. ISQED 2008.[14] Lee K. EM recovery and short lead effect under bipolar-and unipolar-pulse

current. IRPS 2012.[15] Jain P et al. Asymmetric aging: introduction to the problem and solution for

power managed designs. TVLSI 2012.[16] Suresh S, et al. 100 MHz DC–DC switching converter with tracking control.

IECON, 2008.



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Design-in-reliability: From library modeling and optimization to gate-level verification