Design Example - Drag Strip “Christmas Tree ”

et438b-8.pptx 1

LECTURE NOTES PART 8ET 438B Sequential Control and

Data Acquisition

et438b-8.pptx 2

DESIGN EXAMPLE - DRAG STRIP “CHRISTMAS TREE”

lane 1 lane 2

ready

3 sec

3 sec

3 sec

Y

Y

Y

G

G A simplified starting timer is to be constructed for a drag strip. To enable the start timing for a race both cars must actuate sensor switches at the start line that indicate they are in position. When the cars are in position, the race judge receives a green light on his control panel and a green light comes on of the “Christmas Tree”. He then presses a race initial button on his control panel. The Christmas tree times through the sequence shown at left.

3et438b-8.pptx


When the lower pair of green lamps come on the racers begin. A pair of photo eyes located at the finish line indicate the winner by lighting a blue light for a winner and a amber light for a loser. after the race results are indicated, the judge can press a reset button to prepare the system for the next race

Bu

A

lane 1

lane 2

lane 1

lane 2

car 1

car 2

finishsensors

finishindicators

start sensors

et438b-8.pptx 4


Design Problem1.) Identify the states, conditions and actions for this system2.) Construct a flow chart of the logic for this system3.) Construct a state transition diagram for this system4.) Design a ladder logic system to implement these functions

Part 1: States, Conditions, Actions

StatesS0 : resetS1: cars at start lineS2: 1st set red lamps onS3: 2nd set red lamps onS4: 3rd set red lamps onS5: Green lamps on (race

start)S6: Lane 1 WinsS7: Lane 2 Wins

et438b-8.pptx 5


Define conditions (Inputs)

Conditions I0: reset pressedI1: racer 1 positionedI2: racer 2 positionedI3: race timing initiatedI4: 1st set red lamps timed outI5: 2nd set red lamps timed outI6: 3rd set red lamps timed outI7: lane 1 finish photo eye trippedI8: lane 2 finish photo eye trippedI9: start pressed

et438b-8.pptx 6


ActionsO0: light green ready lampO1: light red lamps set 1O2: light red lamp set 2O3: light red lamp set 3O4: light green lamp setO5: light blue lamp 1 if lane 1 winsO6: light blue lamp 2 if lane 2 winsO7: light amber lamp 1 if lane 1

losesO8: light amber lamp 2 if lane 2

loses

Define actions (Outputs)

et438b-8.pptx

7

Part 2 Flow chart

Reset

Car 1positioned

Yes

no

no

Yes

1

light judgereadylamp

light treereadylamp

2

Car 2positioned

Raceinitiatepressed

sequenceX-mas treelights

Red set 1 on3 sec

Red set 2 on3 sec

Red set 3 on3 sec

Green lampson

race in progress

lane 1 sensor trip

Yes

nolane 2sensor trip

Yes

no

lane 1 winnerlane 2 loser

lane 2 winnerlane 1 loser

2

Bu lane 2 onA lane 1 on

1

8et438b-8.pptx

Example State Transition Diagram

S0

Reset

S1

Cars 1 & 2positioned

Ready

O0lightreadylamps

S2

Red set 1 on

Timing initiated

S3 Red set 2 on

Set 1 time-out

O1lightLampsO0 not

O2lightlamps

S4

Set 2 time-out

3rd red seton

O3lightlamps

S5

Racestart

O4light greenlamps

S6Lane 1 wins

O6, O7 Light correct lamps

Resetpressed

2I1I 3I

0I

4I

5I

6I

7I

S7

Resetpressed

0I

Lane 2 wins

8I


9I

Startpressed

9

Construct State Equations

et438b-8.pptx

S0S1

2I1I

0I

State 0

S6

)0S2I1I()9I)7S6S(0I0S(0S 1

)0S2I1I()9I)7S6S(0I0S(0S 1

0S)9I)7S6S(0I(2I)9I)7S6S(0I(1I)9I)7S6S(0I(0S0S2I0S1I0S0S 1

0S9I0S)7S6S(0I)2I1I()7S6S(0I)2I1I(9I)2I1I(0S0S 1

0S]9I)7S6S(0I[)2I1I(]9I)7S6S(0I[)2I1I(0S0S 1

DeMorgans

Expand and Simplify

0

Factor

Regroup

S7

0I

9I

Startpressed

et438b-8.pptx 10


State 0 continued

1

)2I1I)(9I)7S6S(0I0S(0S 1

]0S)2I1I)[(2I1I)](9I)7S6S(0I()2I1I(0S[0S 1

]0S1[)]9I)7S6S(0I(0S[)2I1I(0S 1

)]9I)7S6S(0I(0S[)2I1I(0S 1

Simplify &Regroup

Reduced Equation

Factor

et438b-8.pptx 11

S0

S0

RST

SLS1

SLS2

S7

S6

START

Construct Ladder Logic

)2I1I()9I)7S6S(0I0S(0S 1

)II( 21)9I)7S6S(0I0S(

et438b-8.pptx 12


S0S1

2I1I 3IState 1

)1S3I()0S2I1I1S(1S 1

)1S3I()0S2I1I1S(1S 1

1S0S2I1I3I0S2I1I1S1S3I1S1S 1

)1S3I(0S2I1I)3I(1S1S 1

1S0S2I1I0S2I1I0I)3I(0S2I1I)3I(1S1S 1

0S2I1I)1S1)(3I()3I(1S1S 1

0S2I1I)3I()3I(1S1S 1

)3I)(0S2I1I1S(1S 1

et438b-8.pptx 13

)3I)(0S2I1I1S(1S 1

Construct Ladder LogicState 1 Output Equation

10 SO

S1S0

S1

SLS2

SLS1INIT

)SIIS( 0211 )3I(

et438b-8.pptx 14

S2

S3O1lightLampsO0 not

4I

Set 1 time-out

3I

Construct State EquationsState 2

TON#(c,t)=On-delay timer #c = input conditiont = time delay

)4I()3I2S(2S 1

done timer)3,2S(1TON4I

)3,2S(1TON()3I2S(2S 1

S3

Set 1 time-out

O2lightlamps

S4

Set 2 time-out

4I

5I

State 3

)3,3S(2TON()2S)3,2S(1TON3S(3S


)5I()2S4I3S(3S

1

1

State 2 Output Equation 21 SO


so

)3,2S(1TON()3I2S(2S 1

et438b-8.pptx 15


S4

O3lightlamps

6I

S5

5IState 4

)3,4S(3TON()3S)3,3S(2TON4S(4S


)6I()3S6I4S(4S

1

1

43 SO State 4 Output Equation

S5

O4light greenlamps

S6

6I

State 5

))8I7I(()4S)3,4S(3TON5S(5S


))9I8I(()4S6I5S(5S

1

1

7I

S7

8I

et438b-8.pptx 16


State 5 simplification

))8I7I(()4S)3,4S(3TON5S(5S 1

)8I7I()4S)3,4S(3TON5S(5S 1


S6

Resetpressed

0I

7I


S0State 6

)0I()5S8I7I6S(6S 1

State 6 Output Equations

68

65

SO

SO

Block Lane 2

et438b-8.pptx 17


State 7

S0


S7

8I

0I

Resetpressed

Lane 2 wins

)0I()5S8I7I7S(7S 1

Block Lane 1

State 7 Output Equations

77

76

SO

SO

et438b-8.pptx 18

S6S5

S6

FLS1 I0FLS2

S6

O5

O8Lane 1 Wins


)0I()5S8I7I6S(6S 1

68

65

SO

SO

State 6

et438b-8.pptx 19


S7S5

S7

FLS1 I0FLS2

S7

O6

O7Lane 2 Wins

State 7)0I()5S8I7I7S(7S 1

77

76

SO

SO

et438b-8.pptx 20

Complete System

S0

S0

RST

SLS1

SLS2

S1S0

S1SLS2

SLS1INIT

INIT

S7

S6

START I9

S1

O0

S2

TON1(S2,3) S2

TON1S2

Racers Staged

S2O1

RedSet 1

I1

I2

I0

I3

I1 I2

I3

I4

S3

TON2(S3,3) S3

S2TON1(S2,3)

TON2S3

S3O2

RedSet 2

S4

TON3(S4,3) S4

S3TON2(S3,3)

TON3S3

S4O3

RedSet 3

I5

I6

et438b-8.pptx 21

Complete System

S6S5

S6

FLS1 FLS2

S6

O5

O8Lane 1 Wins

S7S5

S7

FLS1 FLS2

S7

O6

O7Lane 2 Wins

S5

S5

S4TON3(S4,3)

I7

FLS1 FLS2

I8

S5O4

I7 I8

RST

I0

I7 I8

RST

I0

et438b-8.pptx 22

Design Considerations

Fail-safe operation - component fail resultsin little or no damage or inconvenience

Common Practice1.) start sequence by closing NO contacts2.) stop a sequence by opening NC contact

Practice Results: if device fails to start process stops,If started would stop Example: Motor starter

Personnel and Equipment Safety

et438b-8.pptx 23

Troubleshooting Tips

Common causes of Failure1.) Dirty or oxidized contacts2.) Broken wire or loose connection3.) Up stream power source interrupted causing input device to de-activate

Other Issues

Contact operation sequencebreak-before-make standardSee previous example limit switches

et438b-8.pptx 24

Programmable Logic Controllers (PLC)

Microprocessor-based controller that implements ladder logic through software and hardware interface.

Definition of PLCDigital apparatus using programmable memory and stored programs forimplementing Logic Timing Sequencing Counting

Field devices (sensors)

INPUTMODULES

CPU

Fielddevices

(controlvalues,solenoids)

OUTPUTMODULE

MemoryProgrammerUSER

Basic Block Diagram of A PLC

et438b-8.pptx 25

PLC Operation in Run Mode1. Scan all InputsDetect change in status of field devices (Limit switches Pressure switches, etc.)

Time from 1 to 4 called scan time. Can be important in programs

2. Execute control program based on user logic design

3. Test output status against program values.

4. Update output to fit changes dictated by input change

et438b-8.pptx 26

Typical PLC Input/Output Modules

Solid state sensors (electronic)proximity switches, photo eyes etc.Voltage levels 24 - 240 Vac 24-240 Vdc

TTL levels, Sourcing and sinking I/O

PLC I/O designed to connect to industrial devices

Dry contacts (standard switches)motor contactorsPressure, temperature, limit, flow switches

I/O grouped on cards with 8, 16, 24,32

inputs

1 set terminals (com, n) = 1 I/O point

et438b-8.pptx 27

PLC I/O InterfacingPLC’s use memory mapped I/O

PLC uses microprocessors with 8-16 bit words. Each I/O point identified by location in memory. Terminals have unique addresses represented by decimal, octal or binary number. (commonly decimal)

Each memory word maps to group of I/O

points

Bits represent status of I/O field

devices1=on, 0=off

28et438b-8.pptx

Non-expandable PLCs use fixed addressing: All slot 0

PLC I/O InterfacingFor expandable PLCs

Level 1: Rack or chassis identifier

Level 2: Slot identifier (type of I/O

card)

Level 3: I/O point. Type of

point and terminal number

I/O Status Table

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

1 0 0 00 0 1 1 0 0 1 01 0 1 0

et438b-8.pptx 29

Addressing of I/O cards (Allen-Bradley (A-B))

X:n

A-B uses decimal expandable addressing for most PLCs

PLC I/O Interfacing

Slot Number

Function I/O

X:n/p

Addressing Specific I/O points (Allen-Bradley)

Function I/O

Slot Number

Terminal Number

For fixed PLC designs, all I/O addressed to slot 0

et438b-8.pptx 30

PLC I/O Interfacing

I/O Addressing Examples

Function Chassis Slot Terminal # Addressinput 1 4 I:1/4output 2 13 O:2/13input 3 2 I:3/2input 4 4 I:4/4

Note: Decimal addressing used above

Other PLC data types: Bit data, unsigned integer, signed integer, BCD (binary coded decimal 0-9 binary)

et438b-8.pptx31

Input Modules

Sequential control uses discrete (binary) inputs (on/off) from field devices (switches sensors, etc.)

Typical Type of Input Modules

Ac Dc24, 48, 120, 240 V 24, 48, 1-60 120 Vdc120, 240 V isolated sink/source 5-50 Vdc24 Vac/dc 5 V TTL

5/12 V TTL

Input module considered load of field device(switch)

commonsource

field devices

et438b-8.pptx 32

Input Module Specifications

Explanation of Specifications

Backplane draw current - module current drawn by electronicsMaximum signal delay - time required for PLC to sense change in field device and store it in memoryMaximum off state current - max current that can flow so that input remains in off state. (leakage I from solid state sensorsNominal input current - current drawn by the input point with nominal voltage applied

et438b-8.pptx 33

Input Module SpecificationsAdditional Specifications

Useful when applyingactive (solid-state)switches and proximitysensors

Voltage DropLeakage Current

Load CurrentPower-up

Delay

Ileakage

1.7-3.5 mAmust flow to keepsensor active(2 wire sensor)

Leakage CurrentVoltage Drop

Vs

Vs must be lowTypically 6-10for 2-wiresolid state sensor

et438b-8.pptx 34

Inputs with Solid State SensorsWhen solid-state 2-wire sensor is used with switch, sensor will be inactive until circuit is completed

Power-up Delay

OpenCkt

Dealing with power up delay - add parallel resistor.

Must allow enough current to activate sensor but not turn on input module

et438b-8.pptx 35

Inputs with Solid State Sensors

Dealing with power up delay - add parallel resistor.

Example: size R Vs = 115 VacIL = 1.7 mA

R = 115 V/ 1.7 mA

R = 67.647 kW

et438b-8.pptx 36

Inputs with Solid State Sensors

Minimum load current-lowest I value that keeps the sensor active

May need to parallel a resistor with the input card if it has a high impedance input or sensor needs more current than card can handle without turning on the input

R

R called bleeder resistor. Usually sized according tomanufacturer charts

Based on concept of current division

Documents

Design Example - Drag Strip “Christmas Tree ”