Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

2300 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 10, OCTOBER 2005

Design Criteria of High-Voltage LateralRESURF JFETs on 4H-SiC

Kuang Sheng, Member, IEEE, and Shuntao Hu

Abstract—Integrated power electronics on SiC have great po-tential in future power electronics applications. In this paper, anovel vertical channel lateral junction field-effect transistor struc-ture with reduced surface electric field effect is proposed for thefirst time on 4 H-SiC to address existing challenges in lateral powerdevices on SiC. Based on an experimentally proven channel design,the detailed design procedure of such a device has been investi-gated. Design criteria to optimize device forward blocking as wellas conduction characteristics are studied. Parameter tolerance anddesign windows are discussed considering practical issues in devicefabrication. Designs that will lead to an optimized tradeoff betweendevice breakdown voltage and specific on-resistance are shown.With an 8- m-long drift region, a 1535-V breakdown voltage and3.24 m cm2 specific on-resistance can be achieved. This rep-resents a figure-of-merit of 737 MW/cm2, about 100 times higherthan that of the best normally off lateral power devices reported inthe literature. The proposed device can be an attractive candidatefor power integrated circuit on SiC.

Index Terms—High voltage, junction field-effect transistor(JFET), power integrated circuits, power semiconductor switches,reduced surface electric field (RESURF) effect, SiC.

I. INTRODUCTION

S iC has drawn significant attention in recent years as the ma-terial for power semiconductor devices due to its superior

physical and electrical properties. Compared with silicon, SiChas a larger bandgap (3.26 V for 4 H SiC), a breakdown electricfield V/cm almost one order of magnitude higherthan that of silicon, high electron saturation velocity

cm/s , and high thermal conductivity (3.0–3.8 W/cm K). Aspecific on-resistance limit of unipolar power devices made ofSiC is almost three orders of magnitude lower than those madeof silicon with a similar breakdown voltage. Vertical unipolarSiC power devices have already demonstrated a specific on-stateresistance of m cm with a blocking voltage of 1726 V [1].This is equivalent to a figure-of-merit V as high as830 MW/cm , 85 times higher than the theoretical limit of sil-icon unipolar devices.

For integrated power electronics, lateral devices are preferredbecause of their flexibility in realizing a system-on-a-chip.However, the specific on-resistances of lateral devices reportedso far are much higher than those of vertical devices. Numerousworks have been done on an SiC lateral MOSFET. There areseveral problems associated with SiC MOSFET that limit the

Manuscript received November 23, 2004; revised June 27, 2005. The reviewof this paper was arranged by Editor M. A. Shibib.

The authors are with the SiCLab, Department of Electrical and ComputerEngineering, Rutgers University, Piscataway, NJ 08854-8058 USA (e-mail:[email protected]).

Digital Object Identifier 10.1109/TED.2005.856177

device performance. First, it is well known that due to thequality of SiC/SiO interface, the carrier mobility of MOSFETchannel ( 30–50 cm Vs for inversion layer in the usable re-gion) is significantly lower than bulk mobility ( cm Vsfor electron), thus increasing the on-state resistance greatly.Second, the implanted reduced surface electric field (RESURF)region of the LDMOS reported also greatly increases the totaldevice on-resistance. RESURF is the principle most lateralpower devices employ to achieve high blocking voltage withrelatively high doping. Limited by the device structure, in allSiC lateral inversion mode MOSFETs reported, the N RESURFdose is introduced through ion implantation. Since this NRESURF region is also responsible for forward current con-duction, the mobility degradation, caused by the implantationresults in high on-resistance. Furthermore, there is a tradeoff ofa RESURF dose between blocking voltage and on-resistance.The lower the RESURF dose, the higher the on-resistance whilethe breakdown of device is limited by gate-oxide breakdownif the RESURF dose is high. There is typically very high elec-trical field inside the gate-oxide at the gate contact edge thatusually causes device premature breakdown before the criticalelectrical field inside SiC is reached [2]–[10]. These problemspose great challenges to SiC MOSFET while remain unsolved.

In this paper, an alternative that avoids the above problems isproposed with the design of the world’s first high-voltage SiClateral junction field effect transistor (LJFET). The proposed de-vice achieves an on-resistance of m cm with a blockingvoltage of 1535 V. This shows an on-state resistance two ordersof magnitude lower than the best reported lateral power devicewith a similar blocking voltage [9].

II. PROPOSED DEVICES AND DESIGN CRITERIA

A. VC LJFET With Double Uniform RESURF Region

1) Device Structure: The structure of the proposed verticalchannel JFET (VC-JFET) is shown in Fig. 1. A traditional NRESURF epi-layer is grown on top of the p substrate with anacceptor doping cm . The N layer consists of tworegions, namely the drift region and the channel region, bothof which have the same donor concentration. The channel issandwiched between two P N junctions with heavily dopedP regions introduced by tilted ion implantation. The devicefunctions in the same way as a vertical JFET (VJFET) [1] exceptthat the voltage blocking and current conducting drift regionis now a lateral region. In power electronics applications, it isimportant to have power devices that are normally off whichmeans the devices can block necessary voltage without an activebias on the control terminal. In order to achieve normally offdevice characteristics, the channel of this device is designed in

0018-9383/$20.00 © 2005 IEEE

SHENG AND HU: DESIGN CRITERIA OF HIGH-VOLTAGE LATERAL RESURF JFETs ON 4H-SiC 2301

Fig. 1. Structure of VC-LJFET with an uniform doped RESURF region.

the same way as in [1]. The N-channel width is designed insuch a way that zero-bias depletion regions of the two P Njunctions have sufficient overlap to ensure that the device blocksvoltage up to the avalanche breakdown with a negligible lowleakage current. Such a channel structure to ensure normally offdevice performance has been experimentally demonstrated byour laboratory for vertical power devices on 4 H-SiC [1].

The drift region length is chosen to be 8 m from the rightside of the gate to the drain for the 1.2–1.6 kV breakdownvoltage targeted. As shown in the figure, an additional topRESURF region is added inside the N layer. The top RESURFregion is 5.5 m long and 0.5 m deep for good performanceand good implantation process compatibility, right to the gatecontact inside the drift region.

The device is simulated in a two-dimensional numerical sim-ulator with models calibrated to our experiments on SiC powerdevices [11], [12]. The area of the simulated device is set to1 cm for simplicity of evaluation.

2) Normally Off Channel Design: A device structure asshown in Fig. 1 was simulated to determine the design criteriaof achieving a normally off channel while still maximizingchannel width to reduce device on-resistance. Device channelwidth was varied for different channel doping to find out themaximum channel width. The channel length is set to 1.8 mto avoid processing complication during the device fabrication.A channel too long will corresponds to a deep mesa etchingwhich might cause fabrication difficulty in the process stepsthat follow. A channel too short will make the normally off de-sign very difficult. Fig. 2 shows the maximum channel openingto achieve a normally off device for different channel doping.Fig. 3 is the reverse current–voltage (I–V) characteristics at hightemperature K with the channel length varied from1.2 to 1.8 m, and channel width 0.55 m. Fig. 3 shows that tokeep the reverse leakage current at a low level A/cm ,a channel length more than 1.7 m is required. This is alsoconsistent with previous choice of 1.8 m length channel.

3) RESURF Region Design: RESURF region is the mostimportant region for a lateral power device since it dominates itsvoltage blocking as well as the on-state resistance performances.

In the proposed VC-LJFET structure, the N-epi-drift regionis the current conduction layer, as opposed to lateral power

Fig. 2. Maximum channel width�channel doping for normally off device withchannel length 1.8 �m, dotted line is the calculated maximum channel width toallow the zero-bias depletion layers of two P/N junctions to overlap.

Fig. 3. Reverse I–V characteristics (I –V ) for uniform-doped 2 �10 P RESURF device width channel length varies from 1.2 to 1.8 �m. The Nepi-layer doping is 3� 10 cm , thickness 4 �m.

MOSFET, in which the RESURF region is responsible for thecarrier transportation. An as-grown epi-layer for current con-duction is critical in reducing device on-resistance because ofthe carrier mobility degradation in the ion-implanted regions. Tominimize the on-state resistance, a drift layer with high donordoping as well as large drift layer thickness is preferred. On theother hand, according to the RESURF theory, it is essential thatthe RESURF region be fully depleted along vertical directionbefore the lateral electrical field reaches its critical value. Thisrequires that the thickness of the N layer be within certain rangeto allow the full vertical depletion of the N layer [13], [14]. Thisalso implies that the N layer doping should also be within certainrange since highly doped region is hard to be depleted. A theoret-ical approximation for the single-RESURF N doping limit is [14]

(1a)


Thus

(1b)

According to (1b), for a 1- m-thick N epi-thickness, and a Psubstrate doped at cm , the N epi-doping should belower than cm in order for the RESURF to takeeffect.

To further increase the possible N epi-layer doping, anothertop P-RESURF region can be added, thus forming a doubleRESURF structure as shown in Fig. 1.

Similarly, the following equations can be derived for double-RESURF structure [14]:

(2a)

(2b)

In the case of N , the depletion extension into theN epi-layer from the junction is much less than thatof from junction. So the second term in (2b)can be ignored. For a top P-RESURF with a uniform thickness

m, (2a) and (2b) becomes

(2c)

(2d)

It can be calculated from (2d) that for the same 1- m Nepi-thickness, the maximum doping of N epi-could be as highas cm with the double RESURF structure. A com-parison with the maximum N-epi-doping of cm inthe single RESURF structure with the double RESURF struc-ture shows that adding a top P-RESURF layer can increase thepossible N layer doping by a factor of more than two, hence re-ducing the device on-state resistance.

However, when the drift layer N doping is very high, acorresponding heavy top RESURF acceptor doping is requiredin order to obtain the optimum dose in the drift region. Forthe same reason mentioned previously, that it is difficult fora heavily doped RESURF region to be fully depleted. If thedoping is too high, the device usually breaks down before theRESURF effect comes into play, and device voltage-blockingcapability is compromised. For optimized RESURF region, thedonor doping should be within certain values such that allowsfull depletion of both N epi-layer and top P-RESURF layerbefore the critical field along lateral direction is reached.

A device structure as shown in Fig. 1 was simulated withN drift layer thickness set to 1, 2, and 4 m, respectively.

Fig. 4. Breakdown voltage versus implanted P-RESURF doping for N driftlayer doping 8�10 , 1�10 , 1:3�10 , 1:5�10 , and 1:7�10 cm .The N epi-layer thickness is 1 �m.

An optimum channel design identified in the previous sectionthat ensures normally off performance was adopted in thesestructures.

For each N drift layer thickness, a set of N epi-layer dopingwas tested. And for each N layer doping, various P-RESURFdoping was evaluated to achieve the best device blockingcapability. Figs. 4– 6 show the breakdown voltage as a functionof implanted P-RESURF doping for various N drift layer donorconcentration at room temperature. Those figures show thatfor each N epi-thickness, there exits not only a maximum Nepi-doping as described previously, but also a minimum Nepi-doping as well. Below that minimum level, the RESURFeffect becomes ineffective. The highest blocking voltage isachieved when the N drift layer doping lies in the windowbetween maximum and minimum doping.

Since there exits an optimum net balanced charge of the dis-cussed structure for a certain N epi-thickness, the N epi-dosemust be higher than the optimum balanced charge so that theoptimum net charge after doping compensation can be achievedwith a top P-RESURF layer to ensure a double RESURF struc-ture. Otherwise, an extra implantation of donor dose (N-type)will be required to compensate for the difference between Nepi-dose and optimum dose. The implanted N dose in the topRESURF region makes it more difficult to be depleted than theN epi-region. The double RESURF structure thus is reduced toa traditional single RESURF structure.

For N epi-thickness 1 m, the highest blocking voltage of1348 V occurs when the N epi-doping is cmand corresponding implanted top P-RESURF doping is

cm . The total charge in the drift region can be calculatedby adding the total charge inside the drift region when both Nepi-and top P RESURF are fully depleted

m m cm

m m cm cm


Fig. 5. Breakdown voltage versus implanted P-RESURF doping for N driftlayer doping 4 � 10 , 5 � 10 , 6 � 10 , 7 � 10 , and 8 � 10 cm .The N epi-layer thickness is 2 �m.

Fig. 6. Breakdown voltage versus implanted P-RESURF doping for N driftlayer doping 2�10 , 3�10 , and 4�10 cm . The N epi-layer thicknessis 4 �m.

The first term is the total acceptor charge, and the second thetotal donor charge. This means that the optimum balancedcharge is donor like and the total positive charge along the driftregion is cm. This positive charge is compen-sated by the negative charge in the depleted P substrate whenblocking reverse voltage.

Similarly, the net charge for structures with N epi-dopingequal to cm , cm , cm ,and cm can be calculated. Table I summarized theresults for each N epi-doping, with N epi-thickness equals 1 m.

From Table I, the optimum balanced charge is approximatelycm , thus we can calculate the corresponding min-

imum N epi-doping by dividing the optimum balanced charge

TABLE IBALANCED CHARGE FOR VARIOUS N epi-DOPING AND N epi-THICKNESS 1 �m

(OBC) by the drift layer length and drift layer thickness:

OBC

cmm m

cm

cm (3)

The maximum N epi-doping to facilitate RESURF effect wascalculated by (2d), which yielded a value of cm .The optimum effective doping in the n-epi-is therefore wellbelow the maximum level predicted by (2d). This was also con-firmed by the simulation results, as shown in Fig. 4. When Nepi-doping is either lower than cm or higher than

cm , the highest blocking voltage drops quicklybelow 1300 V. The dashed line indicated that shows the enve-lope of the highest blocking voltage for various N epi-doping.For N epi-thickness of 1 m, the N epi-doping has a certainwindow from cm to cm , in which thehighest blocking voltage is over 1300 V.

Similar conclusion can be drawn for the N epi-thickness 2-and 4- m cases, as can be seen from Figs. 5 and 6.

Results show that for a 8- m drift region, the highest blockingvoltage achievable is 1408 V, when the drift layer thickness is 2

m and the N epi-doping and implanted P-RESURF doping arecm and cm , respectively. That cor-

responds to an average electrical field of 1.76 MV/cm along thedrift region, about 73.4% of the critical electrical field of SiC.

In a vertical power device, without the RESURF or super-junction effect, the electric field takes a triangular or trapezoidalprofile for nonpunch-through and punch-through designs, re-spectively. When the peak electric field reaches the critical elec-tric field , the device will experience avalanche breakdown.For a nonpunch-through structure, with a triangular electric fielddistribution, the maximum achievable average electric field is

45% of the critical electric field if a 90% efficient edge termi-nation is assumed. The average electric field for punchthroughstructures is somewhat higher because of the trapezoidal elec-tric field profile.

In comparison, the average electric field of inthe drift region for the proposed lateral JFET is substantiallyhigher than vertical devices and is also significant for a lateral


TABLE IIBREAKDOWN VOLTAGE TOLERANCE ON ACCEPTOR

POST-IMPLANTATION EFFICIENCY

device. It is worth noting that no edge termination is needed forthe proposed lateral JFET structure since it is self-terminated.

Figs. 4–6 also provide useful guidelines to the sensitivityof the breakdown voltage on the N-epi and the implantedP-RESURF doping.

Fig. 6 shows that for the N epi doping case, a peakbreakdown voltage of 1.36 kV can be obtained with a

cm P-RESURF doping. A design window of the im-planted P-RESURF doping from to cmensures a blocking voltage higher than 90% of the peak blockingvoltage. That allows an error of margin of acceptor implanta-tion doping from 12.5% to 15% with respect to the optimumdoping of cm . This is easily controllable with the ionimplantation process which typically offers accuracy of 5%.This design therefore offers a relatively large breakdown voltagetolerance on the active P-RESURF doping, as is summarized inTable II.

As shown in Table II, a blocking voltage higher than 1200 Vcan be achieved with a tolerance of 12.5% to 24.0% aroundthe optimum P-RESURF doping.

On the other hand, the sensitivity of the breakdown voltageto the N-epi doping can also be observed from the figure. At aP-RESURF doping of cm , the device breakdownvoltage varies from 1.12 to 1.3 kV for an N-epi-doping in therange of to cm . A doping tolerance withinthis range is currently obtainable from commercially available4 H-SiC wafers.

Similar observations can be made from Figs. 4 and 5 forN-epi-thicknesses of 1 and 2 m, respectively.

4) Forward I–V Characteristics: Another advantage of theRESURF lateral JFET structure is that, when compared to avertical structure, a substantially higher doping concentration inthe drift region can be used to obtain a given breakdown voltage.For example, to achieve a 1.4-kV breakdown, the doping of avertical structure should be kept below cm for avertical device, as given by

(4)

In contrast, Fig. 5 shows that the same breakdown voltage canbe achieved with a doping as high as cm , leadingto a reduced on-state resistance. On the other hand, it should bepointed out that because of the lateral nature of the structure and

Fig. 7. Forward I–V characteristics of the optimized structures for N-epi-thickness 1, 2, and 4 �m, respectively. The gate voltage is 2.6 V.

that the current flows laterally in the structure, it does not utilizethe chip area in a manner as efficient as the vertical device wherecurrent flows vertically.

Forward current versus voltage simulations were performedon the optimized structure for each combination of N-epi-thick-ness and doping, as shown in Fig. 7. On-state resistance is cal-culated at current density 100 cm and gate voltage 2.9 V.

The total device resistance is the sum of the drift region re-sistance and the channel resistance, which can be written asfollows:

(5)

where q is the electron charge, is the electron mobility, isthe n-epi-doping, is the channel doping, Z is the depthof the lateral device, is the spreading resistance fromthe end of the channel to the RESURF region and and

are the effective undepleted drift region thicknessand channel width, respectively. In the proposed structure, thechannel uses the same N-epi as the drift region and therefore hasthe same doping and .

The results are summarized in Table III. It is found that an in-crease in N epi-doping does not yield a proportional decrease inthe device on-state resistance. Because when the N epi-dopingis increased, the channel width has to be reduced to keep the de-vice normally off at zero gate bias, increasing the channel resis-tance. For the devices studied, the channel typically contributesa 20% to 40% of the total device resistance, depending on thedevice parameters.

In Table III, the best device figure of merit (FOM:) is 571 MW/cm , when the drift layer thickness is 4 m

and the N epi-doping and corresponding implanted P-RESURFdoping are cm and cm , respectively.The device blocking voltage for this structure is 1360 V with


TABLE IIIOPTIMIZED DRIFT REGION DESIGNS FOR N epi-THICKNESS 1, 2, AND 4 �m

a specific on-state resistance of 3.24 m cm . Discussionsbelow will focus on this specific structure.

With careful analysis, resistance distribution of approxi-mately 40%, 33%, and 27% for channel resistance ,spreading resistance ( , of the “L” shaped area) and driftregion resistance , respectively can be found. Detailedanalyses are attached in the Appendix. Further optimization onthe device resistance is possible by addressing each of the threecomponents.

As the biggest portion of the three, optimizing the channelresistance is important. As has been discussed in Section II-A-2and shown in Fig. 3, the channel length can be reduced from 1.8to 1.3 m if the criteria on the leakage current at 250 C canbe increased to 10 A/cm for a reverse bias voltage of 1.2 kV,which is still negligible for most practical applications. With theshorter channel, the channel resistance can be reduced by 28%or the total device resistance can be reduced by 11%.

The spreading resistance can be reduced by shortening theP-gate width between the channel and the RESURF regionwhich will have minimal effect on the device breakdownvoltage. Considering mask alignment tolerance, a 2 m widthis used in the current design and can be easily reduced if bettermask alignment tolerance is obtainable.

B. VC-LJFET With an Etched Super RESURF Region

Drift region of the LJFET can be further optimized to improvethe device breakdown voltage for a given drift region length. Thestructure, namely the VC-LJFET with an etched super RESURFregion, is shown as in Fig. 8. The structure is identical to theone investigated in Section II-A except that part of the drift re-gion is etched and then filled with passivation SiO . The etchingprocess can be carried out by inductively coupled plasma (ICP)etching and its depth can be controlled with very high preci-sion. This extra etching step is introduced to create a graduallydecreasing P-RESURF dose from the left side of the drift re-gion to the right side. This gradually changing charge profilewas proven to be effective and optimum in obtaining a uniform

Fig. 8. Structure of etched drift region VCLJFET, the etch width is 5 �m,etching depth is varied to achieved optimum blocking voltage.

Fig. 9. Breakdown voltage versus implanted P-RESURF doping for variousetching depth.

electric field in the drift region and hence a maximum break-down voltage [16], [17]. Furthermore, the precisely controlledetching depth can be used to adjust the net P-RESURF dopingaccurately around its optimum value.

Such an approach has been adopted in multiple junction ter-mination extension (MJTE) technique, which has experimen-tally proven to be one of the most efficient edge terminationtechniques by yielding a device blocking voltage almost 100%of the ideal parallel plane junction breakdown voltage. In devicefabrication, repetitive ICP etching can be used and the devicebreakdown voltage can be measured between each ICP etchingto determine the optimum etching depth that will result in a max-imum blocking voltage.

In this structure with an etched drift region, as shown in Fig. 8,the etching length is 5 m from left to the drain of the device.Etching depth of 0.15, 0.20, 0.225, 0.25, 0.275, and 0.30 mwere studied. For each etching depth, the optimum structure forimplanted P-RESURF was found as shown in Fig. 9.

As in Fig. 9, the device breakdown voltage as a function ofimplanted RESURF doping for various etching depth is plotted.


TABLE IVBREAKDOWN VOLTAGE TOLERANCE ON ACCEPTOR POST-IMPLANTATION

EFFICIENCY FOR ETCHED DRIFT REGION

Fig. 10. Specific on-resistance of the high voltage LJFET in comparison toother reported lateral SiC devices as well as the best vertical device reported inthe literature.

The highest device blocking voltage is 1535 V at an etchingdepth of 0.25 m and implanted P-RESURF doping concentra-tion cm . This corresponds to an average electricalfield 1.92 MV/cm along the drift region, or 80% of the criticalelectrical field at this N doping level of cm . Themaximum electrical field inside the oxide is less than 4 MV/cm,which can give reasonably good oxide reliability even at ele-vated temperature. Fig. 9 shows a RESURF acceptor doping“window” from cm to cm inwhich the blocking voltage will be 1500 V. That allows a

9.6% post implantation activation efficiency uncertainty withrespect to the optimum P-RESURF doping at the same time stillensures a blocking voltage higher than 1500 V. This windowsize would change to from to cm tomake the blocking voltage 1400 V, equivalent to a 19.2% to

23.1% RESURF doping window. The results are summarizedin Table IV.

At room temperature, the specific on-resistance of the devicewith the highest breakdown voltage (1535 V) was found to be3.24 m cm , resulting in a figure-of-merit of 727 MW cm .This number is approximately two orders of magnitude higherthan that of the best lateral device reported in the literature [11],[18] and is similar to the best vertical device figure-of-meritreported so far, as can be seen in Fig. 10.

III. DISCUSSION

The proposed VC-LJFET device has two regions, namely thechannel region and the drift region with P-RESURF. The investi-gation carried out in this work shows that the two regions can bedesigned with relatively independent criteria. The decoupled de-sign criteria significantly simplify the device design procedure.

The two regions affect the device off-state blocking charac-teristics in different ways. The channel region mainly affectsthe device off-state leakage current and therefore is critical inobtaining a normally off device that offers low-leakage currentuntil the device reaches avalanche breakdown. As expected, witha higher channel doping, the zero-bias depletion region widthbecome lower and a narrower channel width is needed to keep thechannel normally off. As a design example, a channel doping of

cm requires a channel no more than 0.48 m wideto remain normally off. Such a submicrometer dimension canbe obtained by creating a 1.2 m wide mesa through accuratephotolithography process and careful side-implantation controlto give an implantation depth of 0.35 m on both side of themesa. However, high level of channel width uniformity acrossa reasonably large area will be essential if a device with con-siderable current capability is to be achieved. Since a channelnarrower than 0.2 m will give substantial series channel resis-tance and increase the total device on-state resistance, the overalluniformity for the channel width will be around 0.28 m for thewhole device. Depending on the device fabrication facility andability of process control, this could be challenging. Therefore,an N-epi-doping lower than cm will be desirable tomake the channel fabrication robust against process variations.

The RESURF region design dominates the avalanche break-down voltage of the structure. A properly designed RESURFregion is essential in obtaining a VC-LJFET with a good break-down voltage. Through the investigation of the two structuresproposed, it is clear that for each combination of N-drift regionthickness and doping, an optimum P-RESURF doping can befound to give a maximum breakdown voltage. The optimumtotal net charge in the drift region including the N-epi andP-RESURF regions is around a fixed value q/cm forall different combinations of N-epi-thickness and doping. Theetched P-RESURF structure, which gives a gradually decreasingP doping from the gate to the drain side of the device, resultsin a more uniform lateral electric field distribution in the driftregion and a higher breakdown voltage. This is consistent withother lateral RESURF structures with gradually varying dopingprofile in the drift region reported in the literature for silicon.

In addition to maximizing the device breakdown voltage, an-other major design target is to minimize the device on-resis-tance. While the channel resistance is largely determined by thenormally off criteria of the channel, the drift region resistanceis optimized in combination with the P-RESURF design. It isnoted that for a given N-epi-thickness (e.g., 2 m), the highestbreakdown voltage can be obtained with a specific combina-tion of N-epi-doping and P-RESURF doping (e.g., N

cm , P cm in Fig. 5). An N-epi dopinghigher than the optimum will decrease the breakdown voltage.However, a higher N-epi is desirable in reducing the deviceon-resistance. It was demonstrated that the best figure-of-meritcan be obtained with an N-epi slightly higher than that gives thehighest breakdown voltage, as evident from Table II.


When compared to the existing lateral SiC MOSFET struc-tures, the major advantages of the proposed structures are fourfold. First and most importantly, a “fresh” N-epi-layer is respon-sible for conducting forward current rather than an implantationdamaged N-RESURF region. The N-epi-layer gives a muchhigher electron mobility and hence a significantly improved driftregion resistance. Second, the channel region is also built onthe N-epi-layer that has high electron mobility. This is prefer-able when compared to the problematic SiC MOS inversionchannel mobility which remains a major challenge despite recentimprovements. Thirdly, being a device free of gate oxide, it isalso free of the oxide reliability problem when operating at anelevated temperature which was found to be substantially moresevere than the silicon MOS devices. Lastly, with the optimizedgradually varying P-RESURF profile, an average electric field80% of the SiC critical electric field is achieved in the driftregion, which is significantly higher than what is achievable invertical devices and is one of the highest among lateral structures.

IV. SUMMARY AND CONCLUSION

In this paper, two VC-LJFET structures were proposed andtheir detailed design procedures investigated. Such structureswere proposed to address the issues associated with the existingSiC lateral MOSFET devices. It is demonstrated that the channeland drift regions of the proposed devices can be designed withrelatively independent criteria. Design criteria are studied fordifferent channel doping to obtain a channel that minimizeschannel on-resistance while remaining normally off with zerogate bias up to the device avalanche breakdown voltage. Simi-larly, device drift region design is also investigated extensivelyby studying a matrix of devices with different drift region thick-ness, doping and P-RESURF doping. Design criteria to optimizethese parameters to obtain a high breakdown voltage are studied.Parameter tolerance and design windows for achieving certainbreakdown voltage target are discussed considering practical is-sues in device fabrication. Designs that will lead to an optimizedtradeoff between device breakdown voltage and specific on-re-sistance are shown.

It was shown that by introducing an implanted P-RESURFregion on the surface of the N-epi-layer, the N-epi-layer dopingcan be increased and the device on-state resistance can be re-duced. It is also revealed that by etching part of the drift region

and hence creating a P-RESURF profile gradually decreasingfrom gate to drain along the drift region, a higher breakdownvoltage can be achieved.

It was demonstrated that with a 4- m-thick N-epi-dopedcm , a breakdown voltage of 1535 V can be achieved by

a 0.25- m etching of a part of the 8- m-long drift region. Thedevice has a specific on-resistance of 3.24 m cm , resulting ina figure of merit of 727 MW cm . This figure of merit is about100 times higher than that of the best lateral device reported sofar in the literature. The drastic improvement is resulted fromthe novel proposed device structure and a comprehensive devicedesign optimization.

The proposed VC-LJFET structures can therefore be attrac-tive for 4 H-SiC lateral power devices. The design criteria pre-sented in the paper will provide a useful guideline for the designof these devices or others with similar structures.

APPENDIX

This section includes the detailed analyses the resistance dis-tribution for the optimized structure described in Section II-A-4.

Simulation of this structure with channel length 1.2 minstead of 1.8 m and same drift region yields an on- stateresistance of 2.80 m . This indicates that for this N epi-doping,the channel resistance per unit length m is approximately

m m m (A1)

The resistance for a 1.8 m long channel is

m m m m (A2)

which is about 40% of the total device on-resistance.For N drift layer doping cm , the mobility of electron

is calculated using the analytic low field mobility model from(A3), shown at the bottom the page. in which ,

, , ,, , ,

, ,, and .

These parameters are widely acknowledged and confirmed byexperimental data [15]. According to (A3), the mobility of elec-tron is 772 cm for donor doping cm at roomtemperature. Thus the drift region resistance can be calculatedby using (A4), shown at the bottom of page. In the equation,

(A3)

mm m

m (A4)


“ ” is the electron concentration of N layer and is themobility of electron at this donor doping of cm . Sim-ulation result shows that at on-state, when the current density is100 cm , the potential drop across the drift region is 0.086 V,corresponds to a drift resistance 0.86 m , which agrees wellwith the value calculated in (A4) and account for 26.5% of thetotal device resistance.

The spreading resistance , or the resistance of the“L” shaped area, which connects drift region and channel re-gion, is thus equal to the total device on-resistance subtractedby the drift region and channel region on-resistance. The resis-tance of this part of the device is thus 1.06 m cm , accountingfor 32.7% of the total device resistance.

REFERENCES

[1] K. Tone, J. H. Zhao, L. Fursin, P. Alexandrov, and M. Weiner, “4 H-SiCnormally off vertical junction field-effect transistor with high currentdensity,” IEEE Electron Device Lett., vol. 24, no. 7, pp. 463–465, Jul.2003.

[2] S. Sridevan and J. Baliga, “Lateral n-channel inversion mode 4H-SiCMOSFETs,” IEEE Electron Device Lett., vol. 19, no. 7, pp. 228–230,Jul. 1998.

[3] J. Spitz, M. R. Melloch, J. A. Cooper, Jr., and M. A. Capano, “2.6 kV4H-SiC lateral DMOSFETs,” IEEE Electron Device Lett., vol. 19, no. 4,pp. 100–102, Apr. 1998.

[4] K. Chatty, S. Banerjee, T. P. Chow, R. J. Gutmann, and M. Hoshi, “High-voltage lateral RESURF MOSFETs on 4H-SiC,” in Proc. Device Re-search Conf., 1999, pp. 44–45.

[5] K. Chatty, S. Banerjee, T. P. Chow, and R. J. Gutmann, “High-voltagelateral RESURF MOSFETs on 4H-SiC,” IEEE Electron Device Lett.,vol. 21, no. 7, pp. 356–358, Jul. 2000.

[6] S. Banerjee, K. Chatty, T. P. Chow, and R. J. Gutmann, “Improvedimplanted RESURF MOSFETs in 4H-SiC,” in Proc. Device ResearchConf., 2000, pp. 129–130.

[7] , “Improved high-voltage lateral RESURF MOSFETs in 4H-SiC,”IEEE Electron Device Lett., vol. 22, no. 5, pp. 209–211, May 2001.

[8] S. Banerjee, T. P. Chow, and R. J. Gutmann, “Robust, 1000 V, 130m=cm , lateral, two-zone RESURF MOSFETs in 6H-SiC,” in Proc.Int. Power Semiconductor Devices and ICs Symp., 2002, pp. 69–72.

[9] , “1300-V 6H-SiC lateral MOSFETs with two RESURF zones,”IEEE Electron Device Lett., vol. 23, no. 10, pp. 624–626, Oct. 2002.

[10] W. Wang, S. Banerjee, T. P. Chow, and R. J. Gutmann, “930-V 170mcm lateral two-zone RESURF MOSFETs in 4H-SiC with NO an-nealing,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 185–187, Apr.2004.

[11] M. Ruff, H. Mitlehner, and R. Helbig, “SiC devices: Physics and nu-merical simulation,” IEEE Trans. Electron Devices, vol. 41, no. 6, pp.1040–1054, Jun. 1994.

[12] M. Bakowski, U. Gustafsson, and U. Lindefelt, “Simulation of SiC highpower devices,” Phys. Stat. Sol. (A), vol. 162, pp. 421–440, 1997.

[13] A. W. Ludikhuize, “A review of RESURF technology,” in Proc. Int.Power Semiconductor Devices and ICs Symp., 2000, pp. 11–18.

[14] M. Imam, Z. Hossain, M. Quddus, J. Adams, C. Hoggatt, T. Ishiguro,and R. Nair, “Design and optimization of double-RESURF high-voltagelateral devices for a manufacturable process,” IEEE Trans. Electron De-vices, vol. 50, no. 7, pp. 1697–1700, Jul. 2003.

[15] M. Roschke and F. Schwierz, “Electron mobility models for 4H, 6H, and3C SiC,” IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 1442–1447,Nov. 2001.

[16] R. Ng, F. Udrea, K. Sheng, K. Ueno, G. A. J. Amaratunga, and M.Nishiura, “Lateral unbalanced super junction (USJ)/3D-RESURF forhigh breakdown voltage on SOI,” in IEEE Int. Symp. Power Semicon-ductor Devices and ICs (ISPSD), Osaka, Japan, 2001, pp. 395–398.

[17] S. Merchant, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S.Mukherjee, and H. Pein, “Dependence of breakdown voltage on driftlength and buried oxide thickness in SOI RESURF LDMOS transis-tors,” in Proc. ISPSD, May 18–20, 1993, pp. 124–128.

[18] K. Fujikawa, K. Shibata, T. Masuda, S. Shikata, and H. Hayashi, “800V 4H-SiC RESURF-Type Lateral JFETs,” IEEE Electron Device Lett.,vol. 25, no. 12, pp. 790–791, Dec. 2004.

Kuang Sheng (M’00) received the B.Sc. degree fromZhejiang University, Hangzhou, China, in 1995 andthe Ph.D. degree from Heriot-Watt University, Edin-burgh, U.K., in 1999, both in electrical engineering.

He worked as a Reseacher, Cambridge University,Cambridge, U.K., for three years and is currently anAssistant Professor, Rutgers University, Piscataway,NJ. His research areas include SiC power semicon-ductor device fabrication, packaging and power elec-tronics applications, power IC technologies, new de-vice concepts, and power management. He has au-

thored or coauthored more than 50 technical papers in international journalsand conferences and is the inventor of one patent.

Shuntao Hu received the B.S and M.S degrees inphysics from Fudan University, Shanghai, China, in1996 and 1999, respectively. He received the M.S de-gree in electrical engineering from Rutgers Univer-sity, Piscataway, NJ in 2005, where he is currentlypursuing the Ph.D degree in the Department of Elec-trical and Computer Engineering. His doctoral workfocuses on SiC lateral power devices.

His research has encompassed topics ranging fromohmic contact for SiC, edge termination for powerdevices, silicon dioxide reliability under elevated

temperature, and high electrical field strength.

Documents

Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC