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Design and Verification Tools - DVT TM The Complete Development Environment for Hardware Design and Verification OVERVIEW The Design and Verification Tools (DVT TM ) platform is a powerful, yet easy to use programming environment for e, SystemVerilog, Verilog, and VHDL. It enables faster and smarter code development and simplifies legacy code maintenance for novices and experts alike. Based on the integrated development environment (IDE) concept, DVT is similar to well-known programming tools like Visual Studio and IntelliJ. An intuitive graphical user interface (GUI) integrates a smart code editor with a parser that runs in the background and a complete suite of tools for code navigation and debugging. In addition, the DVT IDE includes several domain specific capabilities such as structural browsing of design entities, verification methodology support, and an innovative linting framework. IEEE Standard Compliant Parser The DVT parser complies with the IEEE 1800 SystemVerilog, IEEE 1647 e Language, and IEEE 1076 VHDL standards. Besides fully supporting the design and verification languages, DVT also signals the use of non-standard compliant language constructs, which ultimately increases simulator compatibility. Integration with Simulators and Other Tools DVT integrates seamlessly with all major hardware simulators to enable simplified simulation analysis. It also works with revision control systems like CVS, Git, Subversion, ClearCase and bug tracking systems such as Bugzilla and ClearQuest. Eclipse Ready The DVT solution is built on the powerful Eclipse platform used by tens of thousands of engineers worldwide and inherits the best features and practices collected into the platform core. The Eclipse platform’s extensible architecture allows DVT to integrate within a large plug-in ecosystem and work flawlessly with third-party extensions. EFFICIENT CODE WRITING AND SIMPLIFIED MAINTENANCE Advanced Code Development Features The DVT IDE incorporates advanced code editing features such as: Syntax and semantic checks with errors highlighted as you type Autocomplete In-line reminders for task tracking Code templates Macro expansion Code formatting Refactoring When writing code using DVT’s smart editor, there is no need to invoke the simulator to make sure the code compiles with no errors. DVT performs on-the-fly incremental compilation. Therefore, the editor highlights the errors in real time, as you type. As a result, users can make the necessary corrections on the spot. Moreover, all the errors and warnings are collected in a dedicated section of the DVT GUI. Therefore, the developer or reviewer can quickly locate and fix various issues spread throughout the code. 10 REASONS TO CHOOSE DVT 1. Use advanced code development features 2. Easily create and reuse code and project templates 3. Continuously improve the code using refactoring 4. Link the simulator output with the source code 5. Debug pre-processing macros 6. Automatically generate documentation 7. Track tasks and place reminders 8. Easily understand the project using high level structural views and hyperlinks 9. Inspect the architecture through dynamically created UML diagrams 10. Automatically check methodology compliance BENEFITS Speeds up code writing Ensures higher quality code development Simplifies debugging and legacy code maintenance Allows easy navigation through complex code Simplifies simulation analysis Lowers language learning curve Accelerates verification methodology adoption Increases productivity and reduces time to market www.dvteclipse.com For e, SystemVerilog, Verilog, and VHDL

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Design and Verification Tools - DVTTM

The Complete Development Environment for Hardware Design and Verification

OVERVIEWThe Design and Verification Tools (DVTTM) platform is a powerful, yet easy to use programming environment for e, SystemVerilog, Verilog, and VHDL. It enables faster and smarter code development and simplifies legacy code maintenance for novices and experts alike.

Based on the integrated development environment (IDE) concept, DVT is similar to well-known programming tools like Visual Studio and IntelliJ. An intuitive graphical user interface (GUI) integrates a smart code editor with a parser that runs in the background and a complete suite of tools for code navigation and debugging. In addition, the DVT IDE includes several domain specific capabilities such as structural browsing of design entities, verification methodology support, and an innovative linting framework.

IEEE Standard Compliant Parser The DVT parser complies with the IEEE 1800 SystemVerilog, IEEE 1647 e Language, and IEEE 1076 VHDL standards. Besides fully supporting the design and verification languages, DVT also signals the use of non-standard compliant language constructs, which ultimately increases simulator compatibility.

Integration with Simulators and Other ToolsDVT integrates seamlessly with all major hardware simulators to enable simplified simulation analysis. It also works with revision control systems like CVS, Git, Subversion, ClearCase and bug tracking systems such as Bugzilla and ClearQuest.

Eclipse Ready

The DVT solution is built on the powerful Eclipse platform used by tens of thousands of engineers worldwide and inherits the best features and practices collected into the platform core. The Eclipse platform’s extensible architecture allows DVT to integrate within a large plug-in ecosystem and work flawlessly with third-party extensions.

EFFICIENT CODE WRITING AND SIMPLIFIED MAINTENANCE Advanced Code Development FeaturesThe DVT IDE incorporates advanced code editing features such as:

▶ Syntax and semantic checks with errors highlighted as you type

▶ Autocomplete

▶ In-line reminders for task tracking

▶ Code templates

▶ Macro expansion

▶ Code formatting

▶ Refactoring

When writing code using DVT’s smart editor, there is no need to invoke the simulator to make sure the code compiles with no errors. DVT performs on-the-fly incremental compilation. Therefore, the editor highlights the errors in real time, as you type. As a result, users can make the necessary corrections on the spot. Moreover, all the errors and warnings are collected in a dedicated section of the DVT GUI. Therefore, the developer or reviewer can quickly locate and fix various issues spread throughout the code.

10 REASONS TO CHOOSE DVT 1. Use advanced code development

features

2. Easily create and reuse code and project templates

3. Continuously improve the code using refactoring

4. Link the simulator output with the source code

5. Debug pre-processing macros

6. Automatically generate documentation

7. Track tasks and place reminders

8. Easily understand the project using high level structural views and hyperlinks

9. Inspect the architecture through dynamically created UML diagrams

10. Automatically check methodology compliance

BENEFITS ▶ Speeds up code writing

▶ Ensures higher quality code development

▶ Simplifies debugging and legacy code maintenance

▶ Allows easy navigation through complex code

▶ Simplifies simulation analysis

▶ Lowers language learning curve

▶ Accelerates verification methodology adoption

▶ Increases productivity and reduces time to market

www.dvteclipse.comFor e, SystemVerilog, Verilog, and VHDL

The autocomplete feature provides a context sensitive list of proposals for partially entered text. This capability helps avoid typos and eliminates the need to search for an entity name in other files. As a result, DVT users can develop code faster.

In-line reminders, such as TODO, FIXME, and other customized tags can be placed in code comments. These reminders are collected and listed in the Tasks view. Having all the tasks handy, users can go directly to the code lines where they need to work on a specific task.

In-line reminders are also useful when performing code review. Since the action items are inside the source code, they are always up to date and visible to the whole team. The reminder list can also be used to estimate the code status and remaining development effort.

Code templates are parameterized code snippets. Combined with the embedded TODO annotations, this capability enables engineers to easily follow the project development guidelines.

Errors inside macros can be difficult to investigate. With the DVT’s macro expansion feature, engineers can examine and debug macro code fragments in context with the source code. This feature can as well be used for nested macros. Refactoring allows users to perform semantic changes in code. While a plain text editor or grep/sed utility is limited to simple search and replace actions, DVT can perform powerful operations like “rename method foo() of class bar” or “rename signal x of module y”. All the definitions and places where the method or signal is used are precisely updated.

Code and Project Navigation Features

Maintaining tens of thousands of lines of code can be challenging. DVT helps to simplify maintenance by providing capabilities like:

▶ Hyperlinks

▶ Semantic search

▶ Class and structural browsing

▶ UML diagrams

These features enable users to navigate easily through complex code, locate the relevant information faster, and understand the source code quickly. They also contribute to reduce project costs, by allowing users to avoid locking a simulator license just to inspect the environment architecture.

Figure 1: The DVT IDE Overview

The Hyperlinks feature helps navigate faster through multiple project files. It practically eliminates the need of using the grep command or memorizing various details such as file names and locations. To look up the definition of an entity, one can simply move the mouse over the entity name to turn it into a hyperlink. In this way, users can go directly to the entity definition instead of searching for it, and therefore save time. Semantic search lets engineers quickly find out where “method foo” is defined, who is calling “method foo” or who is using “signal clk of module fifo”. The results are very precise.

To view at a glance and better understand the project structure, DVT offers class and structural browsing for examining class hierarchy, design hierarchy, and aspect-oriented programming (AOP) layers.

The checks view feature shows all the checks, while coverage view displays the coverage definitions inside the code.

In addition, DVT enables system architecture inspection and documentation through dynamically created UML diagrams. The diagrams are hyperlinked with the source code.

VERIFICATION METHODOLOGY SUPPORTThe DVT IDE supports the Universal Verification Methodology (UVM), Open Verification Methodology (OVM), and Verification Methodology Manual (VMM) and their libraries and guidelines. It also features an OVM to UVM migration wizard, which provides advanced automated transition capabilities using refactoring scripts.

Automated OVM/UVM Compliance CheckingDVT includes an automated OVM/UVM compliance-checking capability. As such, DVT helps verification engineers to automate the process of checking their VIP against the OVM/UVM Compliance Checklist. With this capability, they can effortlessly and consistently apply the OVM/UVM rules and ensure compliance to the official OVM/UVM SystemVerilog User Guide.

DVT allows users to change a rule severity, filter failures, go directly to the problematic source code, easily reapply checks while fixing errors, and generate an OVM/UVM Compliance HTML Report.

The OVM/UVM compliance-checking feature works in both batch and GUI modes.

Figure 2: Automated UVM Compliance Checking

SIMULATOR INTEGRATIONOne can invoke the simulator and visualize and browse its output on the DVT console. The log includes simulation errors and warnings with hyperlinks that take the user directly to the source code. To simplify the log reading, different colors are assigned to the text in accordance with the message source and severity. By providing simulator log recognition, DVT significantly simplifies simulation analysis and debugging.

In addition, the DVT external builder interface enables engineers to use any external tools for code analysis. Errors and warnings are back annotated to the source code in order to speed up debugging.

AUTOMATED DOCUMENTATION EXTRACTIONDVT automatically extracts HTML documentation from code comments. The documentation is always synchronized with the source code and easily available to be shared with other team members or customers. The extracted documentation also includes structural information like UML diagrams and design hierarchy. Moreover, any additional documentation can be easily linked to the extracted documentation.

INCREASING DESIGN AND VERIFICATION PRODUCTIVITY AND QUALITYFaster and Smarter Code DevelopmentThe DVT IDE was developed with maximizing the design and verification productivity in mind. A DVT user does not have to switch from the editor to the simulator, browser or console and thus, the user can stay focused on the code writing or review. He or she has neither to perform repetitive tasks nor spend time to identify, for example, a method call or module. Nor has he or she to search for relevant information in large source code files or documentation.

By using DVT’s hyperlinks, autocomplete, in-line documentation, semantic search, task-tracking, and smart log view features one can find what he or she needs, through a click or shortcut. As a result of all these capabilities, the speed and quality of code development increase significantly.

Efficient Project Management DVT also helps manage design and verification projects more efficiently. The in-line reminders listed in the Tasks view allow the team lead or manager to better organize and control the development effort. Furthermore, the easy inspection of the source code, integrated OVM/UVM compliance checking, source code formatting, and HTML documentation extraction are of great help to maintain better control over project deliverables.

The structural views help to easily understand the project; the UML diagrams simplify architecture inspection. Together, these two sets of features enable both managers and engineers to see the whole picture clearly and control a project from a higher perspective.

Lower Language Learning CurveBeginners feel comfortable with the DVT friendly GUI. The access to integrated documentation and features like compilation errors highlighted as you type, as well as autocomplete combined with code templates speed up the learning process.

TECHNICAL SUPPORTThe technical support team is available to promptly answer your questions, provide you with training, and work with you to determine your needs.

Your requirements and feedback are important. Whether you are looking for technical support or new features to improve your design and verification flow, AMIQ’s technical support team strives to answer your requests in a timely manner.

ABOUT AMIQAMIQ focuses on adding value to the design and verification domains through its EDA proprietary tools and consulting expertise spanning various design and verification projects worldwide. Founded in 2003, AMIQ has today two business lines: design and verification tool development (AMIQ EDA) and ASIC verification consulting services (AMIQ Consulting) . AMIQ launched the beta version of DVT in 2006 and the commercial version in 2008. Since then, AMIQ’s engineers have consistently incorporated new ideas based on the feedback received from customers and contributors, raising the bar in quality and innovation.

The alliances established with Cadence Verification Alliance, Synopsys Catalyst, Mentor Vanguard, and OVM/UVM World along with their contributions to the IEEE 1647 e Language come to prove the quality of the DVT solution. They also acknowledge the significance of introducing the IDE concept into the design and verification domains.

AMIQ serves customers around the world and strives to deliver high quality solutions and customer service responsiveness, while maintaining a friendly and flexible environment.

CONTACT AMIQSupport & Evaluation: [email protected]: [email protected] Web: www.dvteclipse.com

Copyright 2012 AMIQ EDA S.R.L. All rights reserved. The information contained herein is subject to change without notice. DVT is a trademark of AMIQ EDA S.R.L. All others are properties of their respective holders. DVT-0512-3L