Design and Test of Fault Tolerant Quantum Dot Cellular Automata

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NortheasternU N I V E R S I T Y

Design and Test of Fault Design and Test of Fault Tolerant Quantum Dot Tolerant Quantum Dot

Cellular AutomataCellular Automata

Electrical and Computer

Department

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NortheasternU N I V E R S I T Y Outline

Introduction: QCA TechnologyExample QCA circuitsTesting Majority Voter, Networks of MVDFT for QCANovel Complex Universal Gate: AOI (And-OR-

Inverter) GateSynthesis with QCA technologyFuture Research Directions

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NortheasternU N I V E R S I T Y QCA Introduction(I)

• Motivation» Approaching physical limits of CMOS sizing» Alternative technologies need to be investigated.» QCA as a nano scale solution

• New method of computation and information transformation.

• Current Manufacturing Status of QCA» Micro-sized QCA devices

• latch and 2-bit shift register have been manufactured» Research focused on

• molecular QCA devices for room temperature operation. • Initial analysis of a simple molecular systems reported.

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NortheasternU N I V E R S I T Y QCA Introduction(II)

• Speed*» @42 nm spacing: 25GHz» @4.2 nm spacing: 2.5THz

• Clocking Zone Size*» assuming 5x20 cell zone size

In 42 nm: 0.16sq m In 4.2 nm: 0.0016sq m

» In 0.05 m CMOS: Size of typical transistor = 0.56sq m Top area of minimum wire contact =0.01sqm

* In “Architectural Issues and Possibilities in Quantum Cellular Automata (QCA)” by M.T.Niemier and P.M.Kogge in NSF

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NortheasternU N I V E R S I T Y QCA Cell

• QCA cell consisting of 4 “dots” and 2 extra electrons;• Information stored not as voltage level

» Positions of electrons• Coulomb interaction between cells• No current in information transformation• Very low power dissipation.

Binary ‘0’Binary ‘1’

Quantum dot

electron

Rotated cells

QCA cell

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NortheasternU N I V E R S I T Y Cell Interaction

• Information is transferred by the Coulomb Interaction.

Input Cell

State Propagation Direction

Binary Wire

QCA cell

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NortheasternU N I V E R S I T Y Basic QCA Devices

A

B

CMajority Voter: F=AB+AC+BC

F

Coplanar Wire Crossing

Inverter

0 1 0

1

1 0

QCA cell

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NortheasternU N I V E R S I T Y 4-phase Clocking

QCA cell

Switch Hold Release Relax

Clock Field Strength

Clock Zone Phase

• Timing in 4 time zones

• 4 phases in each clock zone

State Propagation Direction

Zone 1 Zone 2 Zone 3 Zone 4

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NortheasternU N I V E R S I T Y QCA Full Adder

• The full adder consists of» 3 MVs» 2 Inverter

• Different Shades of color represent clock zones

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NortheasternU N I V E R S I T Y QCA Memory Cell

• Memory stored in a loop.

• Different Shades of color represent clock zones

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NortheasternU N I V E R S I T Y Majority Voter (MV)

• Implement logic AND/OR functions, by setting an input to:» 0 for AND,» 1 for OR gate.

ABC

FMV

Input A

Input B

Input C

Device cell

Output F Output F as the majority of inputs:F=MV(A,B,C)=AB+AC+BC

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NortheasternU N I V E R S I T Y Test Sets for MV

• No built-in VDD or ground lines in QCA designs. • 2 extra inputs connected to logic “1” and logic “0”

» Called control lines connected to one MV input» Implementing AND and OR logic functions.

0

A

BAB

AB

MV

U0 1

AB

MV

U1

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NortheasternU N I V E R S I T Y Testing MV

ABC

dZ

ABC

dZ

0 1

(a)

MV MV

U0 U1

Control Inputs U1/U0 to setthe MV to OR/AND gates

• 100% single stuck-at fault test set:» ABC= (010, 100, 101, 110)» Fault List:

• A/1 (A stuck-at 1), A/0, B/1, B/0, C/1, C/0, d/1, d/0, Z/1, and Z/0

• 100% single stuck-at fault test set:» ABCU0U1= (11100, 00011)» Fault List:

• A/0, B/0, C/0, d/0, and Z/0• Additionally,

» ABCU0U1 = (10011, 01100)• detects all faults on U0U1

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General Test Set for a Network of MVs

• A logic network composed only of AND and OR gates» AND/OR implemented using QCA MVs.

• 2 extra control inputs other than primary inputs:» U0,U1

ABCDEF

g

hi j

Z

AB

CD

EF

g

hi j

Z

MV1

MV2MV3 MV4

MV5

U11

U00

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• Only 2 vectors needed to detect all SSFs» The 1st test vector

• sets all primary inputs to “0” • sets 2 control inputs to “1” (all MVs OR gates) • detects all (multiple) stuck-at-1 faults

» The 2nd test vector• sets all primary inputs to “1” • sets 2 control inputs to “0” (all MVs AND gates)• detects all (multiple) stuck-at-0 faults

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• Additional Vectors needed to detect faults in control lines (U0U1)

• Conventional (combinational) ATPG tools used» MV replaced by a hierarchical cell implementing

the majority function. » Network of MVs transformed into a hierarchical

gate-level netlist. » Use ATPG for the pin faults on the control inputs

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Testing NetworksAND, OR, INV

• Universal Logic: AND, OR & INV• INVs prevent fault propagation by 2 test

vectors AB

CDEF

g

h

i1 j

Z

i2

AB

CD

EF

g

hj

Z

MV1

MV2

MV3 MV4MV5

1

U00

i1 i2

U1

Without INV:• ABCDEFU0U1 = (00000011• detects all stuck-at-1 faults With INV:• ABCDEFU0U1 = (00000011)• cannot detect E/1 and F/1 • multiple faults masked

» e.g. g/1 and E/1

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Testing Networks of AND, OR & INV

Prim

ary

Inpu

ts Inve

rtin

g B

lock

Non-Inverting Majority Voters

U0

U1

Prim

ary

Out

puts

Control line

Prim

ary

Inp

uts

+ Li

tera

ls

• Push all inversions to the primary input level. • An equivalent network of only AND and OR

» take literals as inputs.

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NortheasternU N I V E R S I T Y Pushing Back Inversions

ABCD Z

AB

CDD

Z

Push all inversion to the primary input

ABCD

D

Z

MVMV

MVMV

U0

U11

0

MV implementation

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NortheasternU N I V E R S I T Y QCA Manufacture Defects• Manufacture consists of Synthesis and Deposition • Defects in Synthesis part results in imperfect

cells:» missing/extra dots; missing/extra electrons

• Defects in Deposition part results in cell misplacement:» cell displacement, misalignment, etc.

• Defect are much more likely to appear in the Deposition part

* Personal correspondence with Prof. M. Lieberman in department of Chemistry and Biochemistry, University of Notre Dame

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NortheasternU N I V E R S I T Y Fault model

• Cell displacement: » defective cell is misplaced within original

direction;• Cell misalignment:

» direction of defective cell is misplaced;• Cell omission:

» particular cell is missing compared to the defect-free design.

Majority Voter

Here we consider only cell misplacement faults caused in the deposition part.

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NortheasternU N I V E R S I T Y Synthesis Results

• Synthesis tool: Synopsis Design Compiler and Synopsis Library Compiler

• Synthesis results show that existing tools can not make efficient use of MV

• Note: AND2 and OR2 can be implemented with MV

Majority Voter

GatesCIrcuit

AND2 OR2 INV MV

Behav 74 86 36 0C432

Struc 74 86 36 0Behav 158 239 134 0

C449Struc 184 208 136 0

C1355 Struc 235 248 141 0C880 Struc 177 155 91 0

C1908 Struc 140 162 79 0C2670 Struc 307 245 127 2C3540 Struc 352 373 129 0C5315 Struc 855 547 277 0

Behav 1164 1163 666 44C6288

Struc 985 958 481 0

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NortheasternU N I V E R S I T Y AOI (And-Or-Inverter) Gate

• Motivation» MV is not universal, doesn’t have INV function» Not favorable for synthesis by existing tools

• AOI gate» Universal complex gate, 7 cells» With embedded AND, OR and INV functions» Desirable for Synthesis» Arranged as two nested MVs

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NortheasternU N I V E R S I T Y Layout and Schematic

• F=MV(D,E,MV(A’,B,C’))• Two nested Majority Voters• Cell B has stronger effect on

device than other input cells; » therefore placed further

than other inputs25nm

25nm

25nm

25nm

25nm

35nm

20nm

5nm

ABC

MV1

D

E

FMV2

MV1MV2

A

B

C

D

E

F

AOI Gate

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NortheasternU N I V E R S I T Y Wired AOI Gate

• AOI gate is stable• Connect AOI gate to

binary wire while preserving original logic function

• Place wires apart to reduce interference

MV1

E

MV2

D

20nm5nm

25nm

25nm

25nm

25nm

35nm

10 15

15

15

15 1515 15

ABC

B

A

C

D

E

AOI Gate

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NortheasternU N I V E R S I T Y Properties

Property 1. All input values are inverted output value is

inverted;

Property 2. Consider an arbitrary network of AOI gates with primary input vector V. If all bits are flipped, V V’,all nodes in network are flipped.

Property 3. For any node in an arbitrary network of AOI gates, stuck-at-u fault is detected by input vector V stuck-at-u’ is detected by V’.

AOI Gate

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NortheasternU N I V E R S I T Y Logic Functions

AOI Gate

• AOI gate can be programmed into various 1-level and 2-level logic

gates C

F

E

B

ABC

MV

D

E

FMV

ORAND Gate

A=0 D=0

NANDAND Gate

B=1 D=0

FC

E

A

C

AF

B=1 D=0 E=0

NAND Gate

C

BF

A=0 D=1 E=0

NOTOR Gate

(2-level)

(2-level)

(1-level)

(1-level)

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NortheasternU N I V E R S I T Y Synthesis Results(I)

• Library consists of 8 two-level gates and 5 one-level gates derived from AOI gate• Area (# of cells) improvement compared to synthesis results using MV and INV

AOI Gate

Various AOI GatesCircuit# of 1-level Gates # of 2-level Gates Improvement

Behav 14 83 41.47%17C432Struct 17 102 28.19%Behav 64 247 34.53%C499Struct 16 265 40.75%

C1355 Struct 20 292 42.9%C880 Struct 54 197 31.23%C1908 Struct 15 187 38.52%C2670 Struct 93 326 27.4%C3540 Struct 82 427 27.51%C5315 Struct 227 146 25.49%

Behav 225 1618 11.82%C6288Struct 263 1601 10.2%

C7552 Struct 204 1009 21.23%

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NortheasternU N I V E R S I T Y Synthesis Results(II)

C432 C2607 C7552CircuitsBehav Struct Struct Struct

ANDAND 8 13 24 27ANDOR 5 15 50 291INV 3 8 42 128NAND2 9 4 40 25NANDAND 0 3 11 30NANDOR 8 7 31 16NOR2 2 5 11 51NORAND 9 4 5 11NOROR 3 4 26 46NOTAND 16 32 87 266NOTOR 5 10 55 154ORAND 15 6 32 168OROR 14 8 5 0Improvement: 41.47% 28.19% 27.4% 21.23%

AOI Gate

• Library Consists of 8 two-level gates and 5 one-level gates derived from the AOI gate• Gate count for each type of gates are shown• Area (# of cells) improvement compared to synthesis results using MV and INV are shown

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NortheasternU N I V E R S I T Y Defect Characterization(I)

AOI Gate

Faulty AOI Gate:• F=MV(B,D,E)• Acts as a MV, •Cell A and C has no effect on output

30nm 25nm

25nm

25nm

25nm

25nm

A

C

E

B

D

Input Cell B Displacement Fault

20nm

5nm

Fault-Free AOI Gate:• Cell size 20x20 sq.nm• Dot size 5nm• F=MV(MV(A’,B,C’),D,E)

25nm

25nm

25nm

25nm

25nm

35nm

A

C

E

B

D

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NortheasternU N I V E R S I T Y Defect Characterization(II)

AOI Gate

Faulty AOI Gate:• F=B• Output determined by horizontal input B alone

Input Cell B Displacement Fault

10nm

25nm

25nm

25nm

25nm

25nm

A

C

E

B

D20nm

5nm

Fault-Free AOI Gate:

• Cell size 20x20 sq.nm• Dot size 5nm• F=MV(MV(A’,B,C’),D,E)

25nm

25nm

25nm

25nm

25nm

35nm

A

C

B

D

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NortheasternU N I V E R S I T Y Defect Characterization(III)

Faulty AOI Gate: F=D’E’+(D’+E’)

(A’B+BC’+A’B’C’)

30nm

15nm

25nm

25nm

25nm

25nm

A

C

B

D

Output Cell Displacement Fault

AOI Gate

Fault-Free AOI Gate:

• Cell size 20x20 sq.nm• Dot size 5nm• F=MV(MV(A’,B,C’),D,E)

25nm

25nm

25nm

25nm

25nm

35nm

A

C

B

D20nm

5nm

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NortheasternU N I V E R S I T Y Test Sets• Test set with 100% coverage to detect all cell

displacement defects:» only 2 vectors needed » ABCDE={00000,00001}

• Test set with 100% coverage to detect all PIN stuck-at faults:» 4 vectors needed» ABCDE={01110,00101,00000,00001}

• Test sets generated using PIN fault model can cover all internal structural faults, very useful in test vector generation

AOI Gate

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NortheasternU N I V E R S I T Y Full Adder

• Full adder with MV, INV:» 3 MVs, 1 INV» 25 cells for active device

AOI Gate

AOIA

B

EC

D

F

MV

E

MV

D

ABC

Wired AOI gate

F

AOIA

B

EC

D

F

a b cin

cout=a*b+b*cin+a*cin

sum=a xor b xor cin

• Full adder with AOI:» 3 AOI gates» 14 cells for active device

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NortheasternU N I V E R S I T Y Future Research:Circuits

• Establish Electrical Model for QCA• Design Sequential Modules in QCA• Delay Faults due to Defects (Kink Effect)• Interface Circuitry Between QCA and

CMOS

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NortheasternU N I V E R S I T Y Future Research: Systems

• Develop QCA-Driven Synthesis• Timing Characterization Across QCA

Modules• Cell Placement/Routing for Room

Temperature Operation• Pipeline Design for High Performance

Documents

Design and Test of Fault Tolerant Quantum Dot Cellular Automata