Design and Implementation of Early-Late Gate Bit Synchronizer for Satellite Communication

Design and Implementation of Early-Late Gate Bit

Synchronizer for Satellite Communication P.N.Ravichandran

1, Satish Sharma

2, Sunil Kulkarni

3 and P.Lakshminarsimhan

4

Digital Systems Group, ISRO Satellite Centre, Bangalore-5600171




Email: [email protected], [email protected], [email protected], [email protected]

Abstract—The paper presents hardware design of digital signal

processing (DSP) based Early-Late gate Bit Synchronizer. The

system is developed for onboard 4KBPS Telecommand system. It is

designed and integrated with BPSK demodulator to recover the

clock. Apart from the implementation, paper describes the

mathematical modeling of bit synchronizer. The whole design is

accommodated in a XILINX xc2v3000-4fg676 FPGA. the design is

tested in real dime for 4KBPS data rate and simulation results are

presented here. Paper also highlights the programmable nature of

the design and methods to reduce the hardware requirement.

Index Terms— Field programmable gate arrays, Signal

processing, Bit Synchronizer, Satellite communication.

I. INTRODUCTION

Power–efficient digital receivers generally require the existence

of a digital clock synchronized to the received bit stream to

control the integrated–and–dump detection filters or to control

otherwise the timing of the output bit stream and therefore

synchronization concept plays a major role in the fields of

communications engineering, digital data transmission, radar

sonar and navigation. The Bit Synchronizer is fundamentally a

Phase Locked Loop(PLL). The synchronizer is designed to

provide phase lock between an internally generated data clock

and an input data steam. Moreover, it can perform the traditional

task of providing phase lock between two clocks. Bit

synchronizers are also required when a nearly synchronous bit

stream is received over a cable transmission system and must be

detected and perhaps multiplexed with other parallel bit streams.

The bit synchronizer can be classified in to two categories open

and closed loop [1]. The former one is used for high SNR

application. In closed loop there are mainly two bit synchronizer

In-phase / Mid-phase bit synchronizer and Early-Late Gate bit

synchronizer. Because of its simplicity in implementation and

less sensitivity towards DC offset early-late gate is first choice

for on-board Telecommand system.

First, the complete system is described, followed by separate

descriptions of bit synchronizer. Next section deals with the y

Xilinx implementation with emphasis on hardware reduction.

Finally test setup and results are discussed.

II. COMPLETE SYSTEM

The complete system consists of the input OP-AMP buffer,

which can receive the BPSK, modulated input from either

receiver or ground checkout system (GCO)[2]. An antialiasing

filter follows this, which is a low pass analog filter. The output

of antialiasing filter is digitized using a 8-bit A to D converter.

The digitized signal from A to D converter is fed to Xilinx

FPGA, where the input signal is demodulated using Costas loop

demodulator and clock is recovered using Early-Late Gate bit

synchronizer. In addition the corresponding bit-sync lock &

Inv

Clk

Demod

Lock

Bit Sync

Lock

Op-Amp

Buffer

Ant-aliasing

Filter

8 bit A/D

BPSK

Demodulator

Fig 1. Implementation of Complete System.

Xilinx FPGA

Inv

Data

Clk

Bit

Synchronizer

Analog Portion

From

RX

From

GCO

Data

Digital Portion

NCC 2009, January 16-18, IIT Guwahati 15

carrier lock signals are also generated. Figure 1 gives the top-

level implementation block diagram for complete system.

The complete digital design is written in VHDL code. As in case

of any DSP based design the basic unit involved is multiplier and

adder. To overcome the problem of overflow and also to limit

the word-length in multiplier, overflow detection & saturation

algorithm is implemented [3] .

III. EARLY-LATE GATE BIT SYNCHRONIZER

The block diagram of the analog domine early-late gate bit

synchronizer is shown in Figure 2 The circuit contains a pair of

gated integrators called early and late gates, each performing its

integration over a time interval of T/2. The input bit stream is

∑ an P(t-nT)

where T is the symbol duration and p(t) denotes a rectangular

pulse width duration T. Integration by the early and late gates are

performed over the time intervals T/2, just before and after,

respectively, the estimated location of data transition. Gate

intervals adjoin each other, but do not overlap.

•

Figure 2 Early-Late gate Bit Synchronizer

The operation of clock recovery is explained in figure 3. If the

timing error is zero, then the data transition falls just on the

boundary between the operation of the early and late gates. In

this case, the estimated and incoming data transitions coincide

with each other, and the output of the two integrators, stored in

the hold capacitors CH, are equal. As a result, the error voltage

vd(t) becomes zero. Because the error voltage is produced from

the absolute values of the integrator outputs, it is also zero if the

data transition is missing. If a transition of input data does not

coincide with the estimated time instant of a transition, then a

timing error denoted by in Figure 3 appears.

Fig 3. Typical waveforms of early-late gate clock recovery

circuit.

In this case, the data transition falls not on the boundary of

operation of the early and late gates, but occurs within the

operation interval of one of gates. Since the input signal changes

its polarity during the gate operation, the associated integration

reaches a smaller magnitude than for the other gate, where a

transition does not occur. Comparing the magnitudes of the two

integrators gives the error voltage vd(t) which is used after low-

pass filtering to control the VCO frequency.

The bit synchronizer can be modeled as a PLL with feedback

system as shown in figure 4. Given the requirement of bit

synchronizer in terms of natural frequency ωn and damping

factor ξ, system can be modeled in terms of Kpd , Kvco, K1 and

K2 which are defined below. The close loop transfer function

[2] is given by.

Fig 4. Phase locked loop.

( )

( )S

sFKvcopdK1

S

sF

vco.KpdK

CLTF(s)

+

= (1)

Where pdK = Phase detector gain in Volts /radian

Kvco = Sensitivity of VCO in rad/sec/volts

F(s) = Loop filter transfer function

Depending on the choice of F(s) the CLTF(s) can be of either

first or second order system. For example, for type 2 systems [4],

loop filter structure is shown in figure 5. The equation (1) can be

rewritten as

Phase

Detector Loop

Filter

F(s)

Gain

(k) VCO

H(s) =1

fi fo

Early

integrator

Late

integrator

Timing VCO F(S)

.

CH

CH I/P Bit

stream

Early gate

Late gate

Received

clock

.

- -

+


( )

( )( )

( )sKFS

sKF

S

sFK1

S

sFK

+=

+

= (2)

Where F(s) = K1 + K2/s

Figure 5. Loop filter structure.

The equation (2) becomes

CLTF(s) = 2*1*

2*1*2

KKsKKs

KKsKK

++

+ (3)

Which is of type 2, 2nd

order system. Using servo theory, (3) is

of the form

=22

2

2

2

nn

nn

ss

s

ωξω

ωξω

++

+ (4)

where K = pdK covK , The value of pdK and covK depends on

sf and the magnitude of the accumulator. The value of K1 and

K2 can be calculated by

2KKK VCOpdn =ω (5)

n

VCOpd KKK

ωξ

2

1= (6)

The equations (1) to (6) are sufficient to model the bit

synchronizer, and by changing the value of K1 and K2 we can

control the performance and characteristics of demodulator loop.

The stability of the system can be verified by transforming S-

domain closed loop transfer function to Z-domain.

IV. FPGA IMPLEMENTATION & HARDWARE REDUCTION

Before FPGA implementation a system level simulation has

been carried out on System Vue software tool for fine tuning of

the design parameters. After checking the performance on

software, the design is coded in VHDL and ported in to Xilinx

FPGA. The Early-Late gate bit synchronizer FPGA

implementation is shown in figure 6.

Fig 6. FPGA implementation of Bit synchronizer

The same design can be used for different specification by

changing the design parameter. The system is tested for different

data rates. The maximum frequency that system can support

depends on the loop delay and filter operating frequency. The

complete system with demodulator takes 14% while standalone

bit synchronizer takes 2% of xc2v3000-4fg676 FPGA.

A noticeable hardware reduction can be achieved by

implementing loop filter multipliers using shifting technique and

phase detector by Multiplexer. The hardware can be further

reduced by choosing the number of bits of accumulator

appropriately, as we can calculate the magnitude of accumulator

output depending on sampling rate & data rate. Instead of using

NCO, only digital controlled oscillator (DCO) [4] can be used, to

avoid the large look up table, but this result in little performance

degradation.

V. TEST SETUP & RESULTS

The Standalone test is carried out on the system by giving NRZ

data at 4 KBPS to the bit synchronizer FPGA from a PN

sequence data generator as shown in figure 7, the output of

FPGA is monitored on oscilloscope. This testing was carried out

for different data rates between 125 BPS to 500 KBPS.

Fig 7. Standalone hardware test setup

K2

Early Phase

Accumulator

Late Phase

Accumulator

Loop

Filter DCO Timing

Circuit

Cos _clock

Early gate

Register

Late gate

Register

Sin _clock

Input

Data

32

14

K1 14

32

14

14

+

-

Data

generator

Bit Synchronizer

XILINIX FPGA

xc2v3000-4fg676

Oscilloscope

14

To VCO

Phase detector

output

Accumulator 1/fs


The bit synchronizer is integrate with BPSK demodulator and

tested at system level. The input to the bit synchronizer is BPSK

demodulated data as shown in the figure 8.

XILINX FPGA xc2v3000-4fg676

Fig 8. Integrated hardware test setup

Figure 9 to 11 shows the system Vue and modelSim output wave

forms of loop filter for 4 KBPS

Fig 9. ModelSim loop filter output for 4KBPS data rate,

frequency offset=0Hz, Tacq=220 ms

Fig 10. System Vue loop filter output for 4KBPS data rate,

frequency offset=0Hz, Tacq=220 ms

Fig 11. ModelSim output for 4KBPS data rate

VI. CONCULISION

Clock recovery is important part of a communication system.

The paper presented the design & implementation of Early-Late

Gate Bit synchronizer circuit from equations to FPGA realization

for NRZ data. The developed system can be used for any data

rate, depending on the sampling speed supported by the device.

The paper highlighted the programmable nature of design and

methods for reducing the hardware. The new design circuit is

easily accommodated in RH FPGA. The design is tested for its

performance by interfacing with the demodulator and also

standalone by giving input from PN sequence data generator, and

it found to be working satisfactorily.

REFERENCES

[1] J.J Spilker,Digital Communication by Satellite, Belmont CA, Prientice

Hall Inc, 1977.

[2] Sunil Kulkarni and Satish Sharma “A multiple bit rate BPSK

demodulator with inphase / midphase bit synchronizer –A detail

design Report “ Digital systems group , ISRO, Doc.No.ISRO-

ISAC-TR-0720, Apr. 2005.

[3] A. Landauro and J. Lienard , “On Over Flow Detection And

Correction in Digital Filter”, IEEE transactions on Computers, Vol.C-24,

No.12, pp-1226- 1228, Dec-1975.

[4] Ulrich.L.Rohde, Digital PLL Frequency Synthesizer :Theory & Design,

Printice Hall Inc ,1983

Oscilloscope BPSK

Demodulator

Bit

Synchronize

r


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Design and Implementation of Early-Late Gate Bit Synchronizer for Satellite Communication