Design and Implementation of AMBA ASB APB Bridge

Proceedings of 2013 International Conference on Fuzzy Theory and Its Application National Taiwan University of Science and Technology, Taipei, Taiwan, Dec. 6-8, 2013

AbstractThe 32 bit AMBA ASB APB Bridge provides an interface between the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). It inserts wait states for burst of read or write transfers when the ASB must wait for the APB. The bridge is designed to respond to transaction requests from the currently enabled ASB master. The ASB transactions are converted into APB transactions. APB peripherals do not need a clock input as the APB access is timed with a strobe signal generated by the ASB to APB bridge interface. The AMBA ASB APB Bridge is modeled using Verilog HDL and validated on SPARTAN 3E and results are visualized on ChipScope Pro.

Keywords:- AMBA, ASB, APB, Verilog, SoC

I. INTRODUCTION TO AMBA

The Advanced Microcontroller Bus Architecture (AMBA) interconnect protocol is developed by ARM and it is the de facto industry-standard on-chip inter-connect specification that serves as a framework for SoC designs, effectively providing the digital glue that binds IP process together. It is also the backbone of ARMs design reuse strategy. AMBA specifies a hie-rarchy of bus types, tailored to differing priorities found across the interconnect structure of SoC designs.

A. AMBA Buses

Three distinct buses are defined within the AMBA specifications [1]. Advanced High-performance Bus (AHB), Advanced System Bus (ASB), Advanced Pe-ripheral Bus (APB). Figure 1 shows, Microprocessors, DMA controllers, memory controllers and other higher performance blocks are suited for connection to the AHB/ASB. Lower per-formance blocks such as UARTs, General Purpose In-put/Output (GPIO) and Timers are suited for connection to the APB. The AMBA specification has been derived to satisfy four key requirements. 1) To facilitate the right-first-time development of embedded microcontroller products with one or more CPUs or signal processors. 2) To be tech-nology independent and ensure that highly reusable pe-ripheral and system macro cell can be migrated across a diverse range of IC processes and be appropriate for full-custom, standard cell and gate array technologies. 3) To encourage modular system design to improve

Fig. 1. Advanced Microcontroller Bus Architecture [1]

processor independence, providing a development road map for advanced cached CPU cores and the develop-ment of peripheral libraries. 4) To minimize the silicon infrastructure required to support efficient on-chip and off-chip communication for both operation and manu-facturing test.

II. AMBA ASB

The Advanced System Bus (ASB) specification de-fines a high-performance bus that can be used in the de-sign of high performance 16 and 32-bit embedded mi-crocontrollers. AMBA ASB supports the efficient con-nection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions. The bus also provides the test in-frastructure for modular macrocell test and diagnostic access. The ASB is a high-performance pipelined bus, which supports multiple bus masters. The basic flow of the bus operation is, the arbiter determines which master is granted access to the bus, when granted a master in-itiates transfers on the bus and the decoder uses the high order address lines to select a bus slave and then the slave provides a transfer response back to the bus master and data is transferred between the master and slave. There are three types of transfer that can occur on the ASB: NONSEQUENTIAL: Used for single transfers or for the first transfer of a burst. SEQUENTIAL: Used for transfers in a burst. The ad-dress of a sequential transfer is always related to the previous transfer. ADDRESS-ONLY: Used when no data movement is required. The three main uses for address only transfers are for idle cycles, for bus master handover cycles and for speculative address decoding without committing to a data transfer.

Manu B.N Prabhavathi P M.Tech Student Associate Professor

Department of Electronics and Communication Department of Electronics and Communication BNM Institute of Technology, Bangalore, India BNM Institute of Technology, Bangalore, India

e-mail: [email protected] e-mail: [email protected]

Design and Implementation of AMBA ASB APB Bridge


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III. AMBA APB

The Advanced Peripheral Bus (APB) is part of the AMBA hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The AMBA APB appears as a local secondary bus that is encapsulated as a single ASB slave device. APB pro-vides a low-power extension to the system bus which builds on ASB signals directly. The APB Bridge appears as a slave module which han-dles the bus handshake and control signal retiming on behalf of the local peripheral bus. By defining the APB interface from the starting point of the system bus, the benefits of the system diagnostics and test methodology can be exploited. The AMBA APB should be used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface.

IV. IMPLEMENTATION

The implementation technique involves modeling the following:

1) Arbiter2) Decoder3) APB Bridge4) Reset controller5) Remap and pause controller

A. Arbiter

The AMBA bus specification is a multi-master bus standard. As a result, a bus arbiter is needed to ensure that only one bus master has access to the bus at any particular point in time. Each bus master can request the bus, the arbiter decides which has the highest priority and issues a grant signal accordingly. Every system must have a default bus master which is granted use of the bus during reset, or when no other bus master requires the bus. The ASB arbitration is controlled by the AREQ, AGNT, BLOK and BWAIT signals. When an ASB master requires use of the bus, it sets its AREQ output line HIGH. This is sampled by the arbiter, on the falling edge of BCLK, and the AGNT outputs change according to the arbitration priority scheme used by the system. The BLOK and BWAIT signals are used to extend the granted period to allow masters to finish transfers before bus master handover begins. If BLOK is set HIGH by the current master, and a higher priority master requests the bus, handover will not start until BLOK is set LOW, showing that the locked transfer has finished. The following arbitration priorities (from highest to lowest) are implemented in the default system: Test in-terface controller (highest), Bus master 1, Bus master 2, ARM processor (lowest).

B. Decoder

The decoder performs three functions, it generates the slave select signals (DSELx) for each of the bus slaves, indicating that a read or write access to that slave is

Fig. 2. Decoder memory map [2]

Fig. 3. FSM Without decode cycle [2]

Fig. 4. FSM With decode cycle [2] required, it generates the slave response signals (BWAIT, BLAST and BERROR) during address-only transfers, when no slave is selected, it can act as a simple protection unit which prevents attempts to access a pro-tected area of the memory map shown in Figure 2. The decoder can be implemented in two ways with and without decode cycles as shown in Figure 3 and Figure 4 respectively.

C. APB Bridge

The APB Bridge provides an interface between the ASB and the APB. It continues the pipelining of the ASB by inserting wait cycles on the ASB only when they are needed. It inserts them for burst transfers or read trans-fers when the ASB must wait for the APB. The imple-mentation of this block contains: a state machine, which is independent of the device memory map, ASB address, and data bus latching, combinatorial address decoding logic to produce the peripheral select PSELx


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Fig. 5. Peripheral memory map [2]

Fig. 6. APB Bridge state machine [2]

signals. Figure 5 shows the peripheral memory map of the peripheral bridge. The finite state machine which controls the working of the peripheral bridge is shown in Figure 6.

D. Reset Controller

The AMBA specification defines a single reset signal BnRES which indicates the current reset status of the system. Assertion (the falling edge) of BnRES is asyn-chronous to BCLK. De-assertion (the rising edge) of BnRES is synchronous to the falling edge of BCLK. BnRES is only asserted during a Power-On Reset con-dition, caused by the assertion of the POReset signal. The POReset input is an asynchronous input, and hence a synchronizing d-type is required to eliminate propaga-tion of metastable values.The state machine which controls the working of reset controller is shown in Figure 7.

E. Remap and Pause Controller

The remap and pause controller has three modes. Reset status: This enables software to determine whether the last reset was a Power On Reset (POR) or a soft reset.

Fig. 7. Reset controller state machine [2]

Remap memory: On reset the internal RAM is mapped out and the external memory is mapped into location 0x00000000 which is the boot location for the ARM processor. The reset memory map is cancelled by writing to a register in this peripheral. Pause mode: The microcontroller only supports one simple power saving mode called Pause. This halts all bus activity (but not the system clock) and waits for an interrupt signal from the interrupt controller before res-tarting the system. The Remap output register is used to hold the value of Remap, which is used to determine the memory map that is used by the system. It is set LOW on reset, and is set HIGH when the Remap address is written to with any value. Once set HIGH, it can only be set LOW by a system reset.

V. SPECIFICATIONS

The design of AMBA ASB APB Bridge has the fol-lowing specifications:

50 MHz bus clock 32 bit address bus 32 bit data bus Decode and without decode cycles Arbitration: Fixed priority [1:4] No. of bus masters: 4 Peripheral: Remap and Pause

VI. SIMULATION RESULTS

Xilinx 13.2 is used for modeling of AMBA ASB APB Bridge and ISim is used for simulation results. Figure 8 shows the results with the priority based arbitration scheme and the read and then the write operations performed on the remap and pause peripheral. PSELx indicates that the peripheral is chosen and when BWRITE is low it indicates read operation and when high a write operation is performed on the peripheral. The status of remap and pause peripheral is shown in Figure 9 when no interrupts are coming from the ARM processor the system stays in a low power mode, when interrupted the pause signal goes high. The remap signal indicates if the system has recovered from a power on reset state and when high divides the internal memory into internal and external memory.The RTL schematic is shown in Figure 12. The design is implemented on SPARTAN 3E and the results are analyzed using ChipScope Pro which is shown in Figure 10 and 11. The synthesis reports are shown in Table 1 and Table 2.


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Fig. 8. Simulation results of ASB APB Bridge

Fig. 9. Remap and Pause outputs

Fig. 10. Chipscope Pro analysis

Fig. 11. ChipScope Pro analysis with active high power on reset

Table 1. Area report Instance Cells Cell Area Net Area Wireload

Bridge 234 2141 0 (D)

Table 2. Power report Instance Cells Leakage

Power (nW) Dynamic Power (nW)

Total Power (nW)

Bridge 234 5591.030 32217.318 37808.347

Fig. 12. RTL Schematic

ARBITER GRANTS

ARBITER REQUESTS

READ

WRITE

PERIPHERAL SELECTED

REMAP ADDRES

PAUSE ADDRESS

GRANT

REQUESTS

DEFAULT MASTER

POWER ON RESET

RESET CONTROLLER

APB BRIDGE

DECODER

REMAP AND PAUSE

ARBITER


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VII. CONCLUSIONS

This paper presents modeling and simulation results of

AMBA ASB APB Bridge. From the simulation results

we can conclude that upto four masters can be connected

over the ASB with a priority based arbitration scheme

and these masters can communicate with the peripherals

over the APB Bridge. In a way the APB Bridge provides

a direct translation of the ASB masters to the peripherals

connected to the APB.

VIII. REFERENCES

[1] AMBA Specifications 2.0, Copyright ARM Limited 1999. [2] ASB Example AMBA System, Technical Reference Manual. [3] Kanchan Warathe, Dinesh Padole, Preeti Bajaj A Design Ap-

proach To AMBA (Advanced Microcontroller Bus Architecture) Bus Architecture with Dynamic Lottery Arbiter

978-1-4244-4859-3/09/$25.00 IEEE 2009. [4] Anurag Shrivastavastava, G.S. Tomar, Kamal K Kalra Efficient

Design and Performance analysis for AMBA bus Architecture Based System-on-Chip, 2010 International Conference on Computational Intelligence and Communication Networks.

[5] ZHANG Qing-li, W Ming-yan, WANG Jin-xiang, YE Yi-zheng, LAI Feng-chang, The Design of AMBA AHBNCI Wrapper

0-7803-7889-X/03/$17.00@2003 IEEE. [6] USHA A. JADHAV, M.M Jadhav A HIGH THROUGHPUT

AMBA AHB PROTOCOL, International Journal of Engineering Science and Technology, Vol. 2(5), 2010,1233-1241.

[7] Verilog HDL by Samir Palnitkar, Prentice Hall 1996. [8] SPARTAN 3E and ChipScope Pro reference manuals by Xilinx Corp. [9] An Overview of SoC Bus Architectures, J. Ganesan Vojin

Oklobdzija/Digital Systems and Applications.


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Design and Implementation of AMBA ASB APB Bridge