Design and implementation of a motion coprocessor for the

MERITE beacon

D.Faura, O.Romain, K. Hachicha and P.Garda

SYEL group

Laboratoire des Instruments et Systèmes d’Ile de France, LISIF

Université Pierre et Marie Curie

FRANCE

Out line

1. Introduction2. The goal 3. Architecture of the beacon4. Implementation5. Experimental Results6. Conclusion

1. Introduction

Recent progress in the fields of : Processing architecture

Electronic implementation SoC, SIP, …

Wireless telecommunication Bluetooth, Wifi, Home RF, …

Ad Hoc networks

Design of new generation of autonomous Systems

Application domains Military and safety

Monitor the enemies Robot rescue

Environment Detection of forest fires

Transport To avoid car crash

Require the design of intelligent network sensors

Accident

Propagation of the alarm

2. Goal To propose and model a new architecture of an

intelligent wireless beacon for sensor networks applications To detect and transmit an alarm To distinguish between a false and a true alarm

To design an electronic implementation To test and verify the behaviour of the beacon in a

real conditions

To integrate To make an AMS System-On-Chip (RFVSoC Project)

3. Architecture

The architecture of the beacon that we propose is composed essentially of 3 units :

3.1 Sensor Unit

Environmental analog sensors

Video chain detection To give information

on the scene CCD or CMOS

cameras

3.1 Sensor Unit

Camera CA88 1/4” With Digital Output Low power

consumption (<100mW).

Data format -YCrCb 4:2:2, GRB 4:2:2, RGB

I2C interface

3.2 Processing Unit

Flexible and upgradeable architecture FPGA composed by a collection of IP

of each functional block

Processor IP to manage different tasks Data acquisition and transmission

Dedicated IPs for image processing Motion detection for triggered alarm Video compression

3.2.1 Alarm detection

Environmental Sensor A simple threshold predefined

Camera A spatio temporal Markov Detector

Past binary difference frame

rpr r

rrr

rr

r

Future binary difference frame

rf

Current binary difference frame

s

3.2.2 Algorithme principle

CodeurProduitId(t)Détection

I(t)

R

Carte binaire de mouvement

Buffer

P

ICM

VAR

O(t)Buffer

S

Buffer

FbinO(t+1)AbsDétection

I(t+1)

R

3.2.3 ICM principle

Past binary difference frame

rpr r

rrr

rr

r

Future binary difference frame

rf

Current binary difference frame

s1

0 0 0

1

00 10

0

01

3.2.4 Example of results

Created binary motion map

3.2.5 Video compression

Used to reduce data rate for the transmission of video signals

2 encoders studied at present: Motion Markov JPEG2000 Standard MPEG4

MPEG4 MMJPEG200

Send bitstream via wireless module

4. Implementation

Experimental prototype designed around a HW/SW platform Co-Design Used Altera Nios tool kit

Based on a FPGA (Cyclone EP1C20 Altera) Architecture: interconnection of different IPs

Acquisition and Wireless Units are plugged

Required Hardware and Software Development

4.1 Hw dev : Sensor unit

Integrates 3 environmental sensors

Digital Thermo resistive sensor,DS1821 Gives 8-bit information on environmental

temperature with [-55,125°C] range

Analog Magneto Resistive sensor, HMC1002

To make electronic compass and detect possible ferromagnetic objects close to the beacon

Analog Atmospheric Pressure sensor, MPX2100AP (Motorola)

Analog measures converted by an ADC, AD7810

10-bit, 100kSPS

4.2 Hw dev : Wireless unit Why Bluetooth module ?

Ad hoc network easy to make Piconet and scatternet patterns

Data rate up to 780 kbit/s Enough

RfSolution Module BRM01 SPI interface Up to 480kbit/s

115kbit/s measured

4.3 HW dev : Video detection

Camera Interface

IP

Camera Interface

IP

MarkovIP

MarkovIP

NiosNios

DMADMA SDRAMSDRAMA

valo

n B

us

Ava

lon

Bus

Image of the Motion detection

stored in the memory

4.4 HW dev : Sensor unit

Camera/Avalon interface realized in Vhdl

Results : YUV signals

4.5 Design of Markov IP

difference

Variance

Binarizationmemory

model energy

Data energy

Energy comparison

4.6 Results LE %

CMOS sensor controller 99 0.9%

Threshold process 185 1.7%

Energy minimization 216 2.0%

VGA controller 156 1,5%

Logic elements not use 9914 93,9%

Bit %

Video controller 0 0

Threshold process 245760 27 %

Energy minimization 16768 2 %

VGA controller 262144 28 %

Memory not use 395776 43 %

Logic element partition Memory bit partition

multipliers %

CMOS sensor controller 0 0

Threshold process 12 25%

Energy minimization 1 1.2%

VGA controller 0 0

Not use 35 35.73 %

DSP block elements repartition

4.7 HW dev : Processing Unit

SOPC Builder GUI

Select & Configure Peripherals, IP

Configure Processor

Generate Nios IP Processor

Synthesis &Fitter

Markov IP

I2C IP Controller

Quartus II

AlteraPLD

HardwareConfiguration

File

HDL source files

APEX 20K

4.8 SW development

SOPC Builder GUI

Select & Configure Peripherals, IP

Configure Processor

Generate Nios IP Processor

AlteraPLD

C Header files

Custom Library

Peripheral DriversCompiler,

Linker, Debugger

GNUPro Tools ExecutableCode

User Code

Initialization

Acquisition

Processing

Transmission

Compression

Spatial

Temporel

PSNR

Intra

Basic MPEG4 coder

Inter

Tools

Scalabiliy

error resilience

sprite

background

Object

shape

Reduced resolution

4.9 MPEG4 Coder Overview

4.10 Performances.

Akyio_qcif Test 1 Test 2 Test 3 Test 4

Compression rate 119 200 293 385

Bit rate (kb/s) 63 37 25.975 19.725

Psnr 40.22 38.02 36.6 35.493

Coding time (ms)

VOL Intra Frame 16061

VOL Inter Frame 33281

VOP INTRA 15498

VOP INTER 32698

5. Experimental Results

Communication with a distant PC realized with an hyper terminal windows application Communication features :

20 meters in indoor 115kbit/s limited by

RS232 driver Visual C++ interface has

been developed to display data transmitted

5.1 Experimental Results

6. Conclusion

we have introduced

the architecture of an intelligent beacon for wireless sensor networks

first implementation : MERITE with following features Markov (HW) detector MPEG4 (SW) compressor Wireless compression

The End

Thanks you for your attention