Abstract—This paper describes the design and implementation

of a 2-GHz single-chip 0.25-µm CMOS receiver for a custom WCDMA system. A system-level simulation framework is used to explore the trade-offs between analog front-end impairments and system performance. System specifications are chosen in order to facilitate a low-power highly-integrated implementation. The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers. The receiver also integrates all baseband components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s Σ∆ analog-to-digital converter operating at 200 MHz. The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW.

I. INTRODUCTION

The desire for ubiquitous information access continues to drive the development of applications and services for new wireless systems. The success of these systems will depend heavily on the ability to provide high capacity while maintaining low cost, small form factor and low power consumption in the portable devices. These characteristics may be achieved by adhering to three design strategies. First, at the system level, implementation issues must be considered even during the earliest stages of system definition. Selecting system features which allow for relaxed hardware requirements is paramount to achieving single-chip low-power receiver implementations. Second, efficient implementations require careful partitioning of receiver functions between analog and digital hardware. The rapid improvements in mainstream CMOS technology facilitate the integration of increasingly more functionality onto a single chip. In particular, advanced signal processing algorithms, which are very amenable to low-power digital design techniques, can be used to relax the analog hardware requirements without sacrificing overall system performance. Third, low-power implementation techniques are required to minimize the power consumption of the analog front-end. Despite efforts to simplify the analog hardware, the analog front-end can still dominate overall receiver power consumption.

This paper describes the design and implementation of a low-power CMOS receiver which is intended to be used as the analog front-end of a wideband code-division multiple access (WCDMA) system with a carrier frequency of 2 GHz [1]. System specifications are chosen in order to facilitate the use of a direct-conversion architecture, which is amenable to high levels of integration [2]–[4]. All receiver components, including the low-noise amplifier (LNA), frequency synthesizer, mixer and analog-to-digital converter (ADC), are integrated onto a single chip. System specifications are also chosen in order to relax the performance requirements of the analog hardware without significantly degrading overall system performance. Low power consumption is achieved by taking advantage of these relaxed performance requirements as well as by using low-power implementation techniques.

Section II provides an overview of the system design, focusing primarily on the trade-offs between analog front-end impairments and system performance. Section III provides a brief description of the system-level simulation framework used to explore these trade-offs, while Section IV describes the implementation of the receiver prototype. Experimental results are presented in Section V, followed by a brief conclusion in Section VI.

II. SYSTEM OVERVIEW

By taking into account implementation issues during the earliest stages of system definition, system features can be chosen which relax hardware requirements without sacrificing overall performance [5]. Code-division multiple access (CDMA) is chosen as the multiple-access strategy for this system. This direct-sequence spread-spectrum technique is attractive from the system performance perspective since it provides immunity against multipath distortion [6]. In addition, because of the wide bandwidth of the CDMA signal,

Design and Implementation of a 2-GHz Low-Power CMOS Receiver for WCDMA Applications

Dennis Yee, David Sobel, Chinh Doan, Brian Limketkai, Johan Vanderhaegen, and Robert Brodersen Berkeley Wireless Research Center

Dept. of EECS, University of California, Berkeley dyee, dasobel, cdoan, bnl, jpv, rb@eecs.berkeley.edu

LNA90˚

0˚ LO (fc)

RF Filter

I

Q

ADC

ADC

RF Input (fc)

Fig. 1. Direct-conversion receiver architecture.

a simple, direct-conversion architecture can be used for the receiver front-end [7], [8]. This architecture is illustrated in Fig. 1. The RF signal appearing at the antenna is filtered and amplified before being downconverted to baseband along parallel in-phase (I) and quadrature (Q) signal paths. The frequency translation is performed using two mixers and a local oscillator (LO) fixed at the carrier frequency and operating in quadrature. The I and Q baseband signals are then amplified and low-pass filtered prior to analog-to-digital conversion. Because the RF signal is converted directly to baseband, this architecture eliminates all intermediate-frequency components and their associated design challenges, including the image-reject problem.

The wideband nature of the desired signal helps mitigate one key problem often associated with direct-conversion architectures: the DC-offset issue. DC offsets are problematic in direct-conversion receivers since the desired signal is downconverted directly to baseband. DC offsets can be caused by systematic offsets in the baseband circuitry, but a potentially more significant source of DC offsets is LO self-mixing. Due to imperfect isolation between the LO and RF ports of the mixer, the LO signal can couple to the RF signal path and mix with itself, resulting in a DC component. For this system, a transmission bandwidth of 32 MHz allows DC offsets to be eliminated with on-chip high-pass filtering. System-level simulations confirm that the degradation in system signal-to-noise ratio (SNR) is less than 1 dB for a high-pass corner frequency of 500 kHz. A similar approach is not feasible for most narrowband signals because a significant portion of the desired signal would be removed.

Although a wide transmission bandwidth facilitates the use of a direct-conversion architecture, it also presents design challenges in the ADC due to the high Nyquist rate requirement. A transmission bandwidth of 32 MHz offers a good compromise since a direct-conversion architecture can still be used without significantly exacerbating the performance requirements of the ADC.

The direct-sequence spread-spectrum signaling scheme also relaxes the noise requirements of the analog front-end, since the system processing gain enhances the SNR of the received signal. Fig. 2 illustrates the effect of processing gain on the constellation diagram of a quadrature phase-shift keying (QPSK) signal in the presence of additive white Gaussian noise (AWGN). This additional noise budget is partitioned between the various analog front-end components, relaxing the thermal noise requirements of the LNA as well as the quantization noise requirements of the ADC. Moreover, the system processing gain also mitigates the effects of frequency synthesizer phase noise, reducing the impact of reciprocal mixing caused by out-of-band phase noise as well as the amount of phase variation due to close-in phase noise.

Finally, in CDMA systems, all users transmit simultaneously in the same frequency band. For this system, channel selection is performed using multiuser detection (MUD) techniques, which are highly amenable to low-power

digital design techniques [9]. Since channel selection is performed by the baseband digital signal processing, the analog front-end does not need to provide channel-select filtering. In addition, the frequency synthesizer needs to generate only a single frequency, which further simplifies the frequency synthesizer design requirements.

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

before processing gain

after processing gain

Fig. 2. QPSK constellation diagrams before and after processing gain.

III. SYSTEM-LEVEL SIMULATION FRAMEWORK

The trade-offs between analog front-end impairments and system performance discussed in the previous section were explored using a system-level simulation framework implemented in Simulink, which easily interfaces with MATLAB , a popular tool used for communications systems development. Since short simulation times are critical for rapid evaluation, a modeling framework which simulates the analog front-end at the carrier frequency is unacceptable. For such a simulation, the maximum step size must be based on the carrier frequency whereas the total number of steps must be based on the symbol rate. Since the carrier frequency is typically much higher than the symbol rate in wireless communications systems, such a simulation would be prohibitively slow.

In order to decrease the simulation time, the simulation framework described here relies on baseband-equivalent models for the analog RF building blocks. The method is similar to envelope simulation techniques used in some RF circuit-level simulators [10]. The baseband-equivalent model for a mixer is described below as an example. First, let any real signal be represented by the following expression:

(1)

where sDC(t), sIn(t), and sQn(t) are baseband signals with bandwidths much less than ωc/2. The Fourier transform of s(t) is

,)]sin()()cos()([)()(1

∑=

++=N

ncQncInDC tntstntststs ωω

(2)

and an example spectrum is illustrated in Fig. 3. Second, let the transfer function of the mixer be expressed as

(3)

where yi(t), yLO(t), and yo(t) are the input, LO, and output signals, respectively. Next, let yi(t), yLO(t), and yo(t) have the same form as (1):

(4)

(5)

(6)

Finally, solve for yoDC(t), yoIn(t), and yoQn(t) in terms of yiDC(t), yiIn(t), yiQn(t), yLODC(t), yLOIn(t), and yLOQn(t). By pre-computing the relationship between these time-varying coefficients instead of keeping track of the actual signals, yi(t), yLO(t), and yo(t), the dependence on the carrier frequency is removed. Consequently, the maximum step size of the simulation is now determined by the symbol period rather than the carrier frequency. The additional simulation complexity of this model depends on the number of harmonics, N, which must be chosen in order to accurately model the effects of analog circuit impairments such as distortion. For typical wireless communications systems, the number of harmonics should be chosen to be at least three.

Although the baseband-equivalent model presented above applies only to mixers, a similar method can be used to derive baseband-equivalent models for other analog RF components such as amplifiers and oscillators. System-level simulations of RF components using these baseband-equivalent models

result in rapid simulation times without sacrificing accuracy. By specifying appropriate functions for the time-varying coefficients, these baseband-equivalent models inherently account for many circuit impairments in the RF components, including distortion, phase noise, quadrature phase offset, frequency offset, and DC offsets.

This simulation framework was used to explore the design trade-offs discussed in Section II. A complete system-level simulation was performed with the specifications listed in Table I. Fig. 4 illustrates the signal constellation diagrams at the output of the analog front-end and at the output of the digital signal processing block which implements the MUD algorithm. Even with these relaxed specifications, the receiver still achieves the required output SNR of 15 dB, which corresponds to an average bit-error rate of 10−4.

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

analog output

digital output

Fig. 4. Constellation diagrams from system-level simulation.

IV. RECEIVER PROTOTYPE

The direct-conversion receiver is integrated onto a single chip and implements all critical receiver functions, including low-noise amplification, LO signal generation, frequency translation, and analog-to-digital conversion. All circuits on this chip use a 2.5-V supply. A fully-differential signal path is used in order to mitigate the coupling between different receiver components as well as to reduce the amount of even-order distortion. The RF input signal and frequency synthesizer crystal reference are both converted to differential signals using external baluns. The LNA is capacitively coupled to the RF ports of the I and Q mixers, while the frequency synthesizer connects directly to the LO ports. In addition, the frequency synthesizer outputs are located immediately adjacent to the mixer LO ports in the layout, reducing the load capacitance to about 30 fF, and thus avoiding the use of clock buffers. Along each baseband signal path, a high-pass filter is used to eliminate DC offsets, while a Sallen and Key low-pass filter attenuates out-of-band signals

TABLE I RECEIVER SPECIFICATIONS FOR SYSTEM-LEVEL SIMULATION

Center Frequency 2 GHz Noise Figure (DSB) 13.5 dB Gain 45–82 dB I/Q Gain Mismatch 4% PLL Phase Noise −85 dBc/Hz @ 2.5 MHz I/Q Phase Mismatch 2.5° IIP2 −11 dBm IIP3 −18 dBm HPF Corner Frequency 500 kHz ADC 7-bit, 25-MS/s Σ∆

2ωcωc−ωc−2ωc 0 ω

S(ω)

... ...

SDC(ω) ½SI1(ω−ωc)−j½SQ1(ω−ωc)

½SI1(ω+ωc)+j½SQ1(ω+ωc)

½SI2(ω+2ωc)+j½SQ2(ω+2ωc)

½SI2(ω−2ωc)−j½SQ2(ω−2ωc)

Fig. 3. Example spectrum of s(t) in (1).

,)]sin()()cos()([)()(1

∑=

++=N

nciQnciIniDCi tntytntytyty ωω

,)]sin()()cos()([)()(1

∑=

++=N

ncLOQncLOInLODCLO tntytntytyty ωω

.)]sin()()cos()([)()(1

∑=

++=N

ncoQncoInoDCo tntytntytyty ωω

),()()( tytyty LOio ×=

)]()([

)]()([2

1)()(

1

cQncQn

cIn

N

ncInDC

nSnSj

nSnSSS

ωωωω

ωωωωωω

+−−−

++−+= ∑=

before the I and Q signals are each digitized by a sigma-delta (Σ∆) ADC. Each circuit block will now be described in more detail.

A. Low-Noise Amplifier

The LNA is implemented using the inductively-degenerated common-source amplifier topology [11], [12] illustrated in Fig. 5. Inductors L3 and L4 help to achieve 50-Ω input matching while load inductors L5 and L6 provide additional filtering at the LNA output. These four inductors are realized as on-chip spiral inductors which use the top three layers of metal to maximize inductor quality factor. Input tuning is performed through inductors L1 and L2, each of which is realized as a combination of the input bond wire and an external chip inductor. The LNA input bond pads are recessed about 300 µm from the edge of the chip in order to accommodate longer input bond wires, and consequently, higher inductance values.

The LNA is biased at 4.5 mA and is powered by a separate 2.5-V supply, which helps to isolate the LNA from the potentially noisy supplies of the other receiver circuits. While the cascode transistors M3 and M4 slightly degrade the noise performance of the LNA, they provide increased reverse isolation, reducing the amount of LO leakage from the mixer to the receiver input.

L1 L2

L3 L4

L5 L6

Vin+ Vin

-

Vout+Vout

-

Vbias

M1

M3

M2

M4

Fig. 5. Low-noise amplifier.

B. Frequency Synthesizer

The 2-GHz I and Q LO frequencies are generated using a fully-differential, wide-bandwidth phase-locked loop (PLL) depicted in Fig. 6. The PLL has a loop bandwidth of 3 MHz. An external 50-MHz crystal reference is used to lock the output signal from the voltage-controlled oscillator (VCO) to 2 GHz.

The VCO is implemented as a 4-stage ring oscillator, which inherently provides the I and Q outputs required for quadrature demodulation. The VCO I and Q outputs are connected directly to the mixer inputs, while a third output is connected to the divider. Dummy divider circuits are connected to the remaining VCO output in order to provide load matching for improved quadrature generation. The phase noise of the ring oscillator VCO is suppressed by the wide-bandwidth PLL [13], thus improving the overall phase noise performance of the frequency synthesizer.

Both the VCO and the high-frequency stages of the divider are realized using source-coupled logic. Although these circuits consume static power, this logic style minimizes the amount of high-frequency current noise injected into the substrate, which would be detrimental to the operation of other RF circuit components, such as the LNA. Finally, a separate 2.5-V supply is used for the phase-frequency detector (PFD) and the last stage of the frequency divider in order to prevent digital switching noise from coupling into the analog circuit components.

VCO

÷40

PFD

fref = 50MHz

fout = 2GHzCP/LF

Fig. 6. Phase-locked loop.

C. Mixer

Frequency translation from RF to baseband is performed by a pair of double-balanced Gilbert cell mixers, illustrated in Fig. 7. This topology provides excellent isolation between the LO and RF ports of the mixer, which is further improved by adding cascode transistors M3 and M4. The sizes of transistors M5–M8 are chosen as a compromise between flicker noise performance of the mixer and power consumption in the VCO. Since the VCO outputs are directly connected to these transistors, small device dimensions are desirable in order to reduce the capacitive loading on the VCO. On the other hand, large device dimensions are desirable for improved flicker noise performance. Because of the wideband nature of the desired signal, the mixer’s flicker noise performance is relaxed in favor of reduced power consumption in the frequency synthesizer.

The load devices M9 and M10 are biased in the linear region and their resistances can be changed by adjusting their gate bias voltages to provide variable gain capability. Each of the I

VLO

Vout

Vin

Vcascode

Vload

M1

M7

M10

M6 M8

M2

M9

M5

M4M3

Fig. 7. Gilbert cell mixer.

and Q mixers is biased at a tail current of 420 µA.

D. Baseband Amplification and Filtering

A block diagram of the baseband section [12], [14] is illustrated in Fig. 8. Immediately after frequency translation, shunt 1-pF capacitors in combination with the mixer output impedance provide first-order low-pass filtering of each of the baseband I and Q signals. A noninverting amplifier then provides moderate gain in order to reduce the impact of noise contributed by subsequent stages.

Each of the baseband signals then passes through a first-order high-pass filter, which removes DC offsets and flicker noise from previous receiver stages. Each filter is realized using on-chip passive structures, which include a pair of 40-pF capacitors and a pair of 45-kΩ resistors, placing the high-pass corner frequency at about 90 kHz. The 32-MHz bandwidth of the desired signal makes this method of DC-offset compensation practical since the high-pass corner frequency can be relatively high, which permits the use of only moderately sized on-chip passive structures.

Next, the output of the high-pass filter is buffered before passing through a second-order Sallen and Key low-pass filter. The poles of the Sallen and Key filter in combination with the pole at the mixer output provide an overall third-order Butterworth low-pass frequency response, which offers a good compromise between linear phase and maximally flat gain. This low-pass filter provides attenuation of out-of-band signals as well as anti-alias filtering for the subsequent Σ∆ ADC.

amplifier HPF buffer Sallen and Key LPF

Vin+

Vout+

Vin- Vout

-

Fig. 8. Baseband amplification and filtering.

E. Sigma-Delta Analog-to-Digital Converter

Since oversampling facilitates digital timing recovery, a Σ∆ converter becomes a natural choice for analog-to-digital conversion [15]. The baseband I and Q signals are digitized using a pair of 7-bit, 25-MS/s Σ∆ ADCs operating at 200 MHz. Since the high Nyquist rate of the baseband signals restricts the Σ∆ converter to a low oversampling ratio of 8, the required dynamic range is achieved by using a 2-1-1 cascade architecture with single-bit quantization in each stage (Fig. 9). Each of the 200-MHz output signals from the three stages is multiplexed into three slower output streams before being brought off the chip.

The switched-capacitor integrators are implemented using folded-cascode operational amplifiers with NMOS input

devices to maximize speed. The device sizes and bias points of each amplifier are optimized for minimum power consumption. In addition, dynamic comparators are used to implement the single-bit quantizers for reduced power consumption.

DAC

∫∑

1/3

-1/3

3/5

-2/5

5/6

-1/3

-1/2

1/3

-1/3

-1/3

∫∑

∫∑

DAC

∫∑

DAC

Fig. 9. 2-1-1 cascade Σ∆ architecture.

V. MEASUREMENT RESULTS

The direct-conversion receiver was fabricated in a 0.25-µm, single-poly, 6-metal CMOS process and occupies an area of 5.0 mm × 5.2 mm including bond pads. The circuit active area is about 5 mm2. A die photo is shown in Fig. 10.

The receiver prototype is directly attached to the testboard using chip-on-board packaging technology. An external balun provides a differential RF input signal to the receiver and a pair of chip inductors complete the LNA input tuning. The receiver performance measurements are summarized in Table II. The receiver input provides an excellent match to 50 Ω with an S11 better than −30 dB at 2 GHz, and the receiver noise figure is 8.5 dB, which includes approximately

LNA

mixer

PLLbaseband

filters

I Σ∆ Q Σ∆

Fig. 10. Chip micrograph.

1 dB of insertion loss from the external balun. The receiver gain is 41 dB with less than 0.5-dB gain mismatch between the I and Q paths, indicating excellent gain matching along the baseband signal paths.

The frequency synthesizer phase noise is −85 dBc/Hz at a 2.5-MHz offset, and the Σ∆ ADC has a dynamic range of 42 dB when operating at a frequency of 200 MHz. The receiver input 1-dB compression point is −31.1 dBm while the out-of-band IIP2 and IIP3 are −6.7 dBm and −18.3 dBm, respectively (Fig. 11). The receiver’s total power consumption is 106 mW.

TABLE II RECEIVER PERFORMANCE MEASUREMENTS

Center Frequency 2 GHz Noise Figure (DSB) 8.5 dB S11 < −30 dB Voltage Gain 41 dB −3-dB Bandwidth 89.8 kHz < f < 17.9 MHz −1-dB Compression −31.1 dBm IIP2 (27 MHz, 37 MHz) −6.7 dBm IIP3 (35 MHz, 60 MHz) −18.3 dBm PLL Phase Noise −85 dBc/Hz @ 2.5 MHz LO-to-RF Leakage −81 dBm Σ∆ Dynamic Range 42 dB @ 200 MHz Power Dissipation LNA 12 mW LO 25 mW I/Q Mixers 3 mW I/Q Baseband 7 mW I/Q Σ∆ ADCs 59 mW Total 106 mW

-45 -40 -35 -30 -25 -20 -15 -10 -5

-50

-40

-30

-20

-10

0

10

20

30

Receiver Input Power (dBm)

Bas

eban

d O

utpu

t Pow

er (

dBm

)

Fundamental

2nd Order IM

3rd Order IM

Fig. 11. Measured gain and distortion.

VI. CONCLUSION

By taking into account implementation issues during the earliest stages of system definition, system features can be chosen which relax hardware requirements without sacrificing overall performance. A system-level simulation framework is presented which facilitates the exploration of such trade-offs. This framework is used to determine specifications for a

custom WCDMA system and a 2-GHz direct-conversion receiver is designed to meet these specifications. The prototype receiver is implemented in a 0.25-µm CMOS process and integrates all critical receiver components, including the LNA, frequency synthesizer, mixers, baseband filters, and ADCs, onto a single chip. Low power consumption is achieved by taking advantage of the relaxed performance requirements as well as by using low-power implementation techniques.

ACKNOWLEDGMENT

The authors would like to thank J. Rudell, J. Ou, A. Niknejad, C. Teuscher, and K. Kundert for their advice and support. The authors would also like to acknowledge S. Alalusi and D. Coates for helping with the testboard and STMicroelectronics for wafer fabrication. This research was funded by DARPA and the industrial members of the Berkeley Wireless Research Center.

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